KR100787015B1 - Method for manufacturing semiconductor device capable of improving breakdown voltage characteristics - Google Patents

Abstract

In a method for manufacturing a MOS transistor, a MOS transistor isolation layer 16 is formed in the semiconductor substrate 11 to surround an area for forming the MOS transistor in the semiconductor substrate. Thereafter, the first impurity is implanted into the region of the semiconductor substrate to adjust the threshold voltage of the MOS transistor. Further, the second impurity is injected only into a portion of the periphery of the above-mentioned region adjacent to the MOS transistor isolation layer where the gate electrode 21 of the MOS transistor is to be formed.

MOS transistor, boron, gate electrode, isolation layer, STI layer

Description

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE CAPABLE OF IMPROVING BREAKDOWN VOLTAGE CHARACTERISTICS}

The invention will be more clearly understood from the following description when compared with the prior art with reference to the following drawings.

1A is a plan view for explaining a hump phenomenon generated in a semiconductor device.

FIG. 1B is a cross sectional view along line B-B in FIG. 1A; FIG.

FIG. 1C is a graph showing the concentration of boron atoms in the p-type impurity diffusion region of FIG. 1B after the p-type impurity diffusion region undergoes a heating or annealing process. FIG.

2A is a plan view for explaining a reverse-hump phenomenon generated in a semiconductor device.

FIG. 2B is a cross sectional view along line B-B in FIG. 2A;

FIG. 2C is a graph showing the concentration of arsenic (or phosphorus) atoms in the n-type impurity diffusion region of FIG. 2B after the n-type impurity diffusion region undergoes a heating or annealing process. FIG.

3A to 3J are cross-sectional views illustrating a conventional method for manufacturing a semiconductor device.

4A is a plan view of an n-channel MOS transistor obtained by the method shown in FIGS. 3A-3J.

4B is a cross sectional view along line B-B in FIG. 4A;

FIG. 4C is a graph showing the concentration of impurity atoms in the p-type impurity diffusion region of FIG. 4B after the p-type impurity diffusion region undergoes a heating or annealing process. FIG.

FIG. 5A is a graph showing sub-threshold characteristics of an n-channel MOS transistor obtained by the method shown in FIGS. 3A to 3J.

FIG. 5B is a graph showing the breakdown voltage of the n-channel MOS transistor obtained by the method shown in FIGS. 3A to 3J.

6A to 6J are cross-sectional views for explaining a first embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 7 is a plan view of the photoresist pattern layer of FIG. 6F. FIG.

8A is a plan view of an n-channel MOS transistor obtained by the method shown in FIGS. 6A-6J.

FIG. 8B is a sectional view along the line B-B in FIG. 8A; FIG.

FIG. 8C is a graph showing the concentration of impurity atoms in the p-type impurity diffusion region of FIG. 8B after the p-type impurity diffusion region has undergone a heating or annealing process. FIG.

9A is a graph showing the sub-threshold characteristics of an n-channel MOS transistor obtained by the method shown in FIGS. 6A-6J.

9B is a graph showing breakdown voltage characteristics of an n-channel MOS transistor obtained by the method shown in FIGS. 6A to 6J.

10A to 10U are cross-sectional views illustrating a second embodiment of a method for manufacturing a semiconductor device according to the present invention.

※ Description of the major symbols in the drawings

101 Silicon Substrate 102 Device Isolation Layer

103 p-type impurity diffusion region 104 silicon dioxide layer

105 gate electrode 106 n ⁺ -type impurity diffusion region

12, 16 silicon dioxide layer 13 silicon nitride layer

14, 18a opening 15 trench

17 p-type impurity diffusion region 18 photoresist pattern layer

The present invention relates to a method for manufacturing a semiconductor device, such as a metal oxide semiconductor (MOS) transistor, partitioned by a thick device isolation layer, such as a shallow trench isolation (STI) layer or a local oxide of silicon (LOCOS) layer.

When manufacturing a MOS transistor, impurities are injected into the silicon substrate under the gate electrode to adjust the threshold voltage of the MOS transistor. On the other hand, in order to divide the MOS transistors from each other, a thick device isolation layer such as a LOCOS layer or an STI layer made of silicon dioxide was introduced.

When the width and length of the channel are reduced, the so-called narrow channel width effect becomes noticeable. For example, in an n-channel MOS transistor, boron atoms are implanted into the silicon substrate under the gate electrode to regulate the threshold voltage, but in this case, the implanted boron atoms are thicker device isolation layers due to heating or annealing processes. Isolated by, the concentration of boron ions is lower at the end of the channel in the width direction than at the center of the channel. This is called a hump phenomenon that reduces the threshold voltage. Similarly, in a p-channel MOS transistor, arsenic (or phosphorus) atoms are implanted into the silicon substrate under the gate electrode to regulate the threshold voltage, but in this case, the implanted arsenic (or phosphorus) atoms are subjected to a heating or annealing process. Isolated by the thick device isolation layer resulting in, the concentration of arsenic (or phosphorus) atoms is higher at the end of the channel in the width direction than at the center of the channel. This is called the reverse-hump phenomenon, which increases the absolute value of the threshold voltage.

In the prior art methods for manufacturing semiconductor devices, to compensate for the hump or anti-humpe phenomenon, p-type impurities such as boron atoms are implanted into the entire periphery of the active region adjacent to the device isolation layer, so that the threshold The concentration of boron atoms or arsenic (or phosphorus) atoms to regulate the voltage becomes substantially uniform at the end of the channel and at the center of the channel after the heating or annealing process is completed. Therefore, the threshold voltage is not changed (see Japanese Patent Laid-Open No. 2000-340791 and US Pat. No. 6,492,220). This will be described in detail later.

However, in the above-described prior art manufacturing method, since the p-type impurity is injected into the entire periphery of the active region adjacent to the device isolation layer, the breakdown voltage characteristic is deteriorated.

The p-type impurity according to the present invention is implanted in a portion of the periphery of the active region adjacent to the device isolation layer which is only below the gate electrode. As a result, while the improvement of the sub-threshold characteristic is maintained, the breakdown voltage characteristic can be improved.

Prior to describing preferred embodiments, prior art methods for manufacturing a semiconductor device are shown in FIGS. 1A, 1B, 1C, 2A, 2B, 2C, 3A-3J, 4A, 4B, and FIG. It demonstrates with reference to 4c, FIG. 5A, and FIG. 5B.

First, the hump phenomenon is demonstrated with reference to FIG. 1A, FIG. 1B, and FIG. 1C. FIG. 1A is a plan view of an n-channel MOS transistor, FIG. 1B is a cross-sectional view along the BB line of FIG. 1A, and FIG. 1C is a diagram illustrating the adjustment of the threshold voltage V _thn after a p-type impurity region is subjected to a heating or annealing process. Is a graph showing the concentration of boron atoms in the p-type impurity region of FIG.

- in Figure 1a and Figure 1b, the reference numeral 101 denotes a p surrounded by an element isolation layer ⁽¹⁰²⁾ indicates the type single crystal silicon substrate, in this case, the element isolation layer 102 is made of silicon dioxide so as to define the field area STI layer. In addition, a p-type impurity diffusion region 103 is formed in the silicon substrate 101 in the active region to adjust the threshold voltage V _thn . In this case, the p-type impurity diffusion region 103 is _operated to increase the threshold voltage V _thn . In addition, the gate silicon dioxide layer 104 and the gate electrode 105 are formed on the active region. In addition, n ⁺ -type impurity diffusion regions 106S and 106D functioning as source and drain regions, respectively, are formed in the silicon substrate 101 in the active region by self-alignment with the gate electrode 105. .

The solid solubility of boron atoms is greater in silicon dioxide than in silicon. Thus, as shown in FIG. 1C, the boron atoms are moved from the silicon substrate 101 to the STI layer 102 by the heating or annealing process described above. As a result, boron atoms are sequestered by the STI layer 102 so that the concentration of boron atoms is lower at the end of the channel in the width direction than at the center of the channel. This is called a hump phenomenon that reduces the threshold voltage V _thn , especially in short channel type MOS transistors.

Next, the inverse humping phenomenon is explained with reference to FIGS. 2A, 2B and 2C. FIG. 2A is a plan view of a p-channel MOS transistor, FIG. 2B is a cross-sectional view along the BB line of FIG. 2A, and FIG. 2C is a diagram illustrating the adjustment of the threshold voltage V _thp after the n-type impurity region has undergone a heating or annealing process. Is a graph showing the concentration of arsenic (or phosphorus) atoms in the n-type impurity region of FIG. 2B.

Figure 2a and in Figure 2b the reference numeral 201 denotes a n surrounded by an element isolation layer (202) ^- - indicates the type single crystal silicon substrate, in this case, the element isolation layer 202 is made of silicon dioxide so as to define the field region STI Layer. In addition, an n-type impurity diffusion region 203 is formed in the silicon substrate 201 in the active region to adjust the threshold voltage V _thp . In this case, the n-type impurity diffusion region 203 serves to increase the absolute value of the threshold voltage V _thp . In addition, the gate silicon dioxide layer 204 and the gate electrode 205 are formed on the active region. In addition, p ⁺ -type impurity diffusion regions 206S and 206D each functioning as a source region and a drain region are formed in the silicon substrate 201 in the active region with the gate electrode 205 and self-alignment.

The solid solubility of arsenic (or phosphorus) atoms is smaller in silicon dioxide than in silicon. Thus, as shown in FIG. 2C, arsenic (or phosphorus) atoms are moved from the STI substrate 202 to the silicon substrate 201 by the heating or annealing process described above. As a result, the arsenic (or phosphorus) atoms are isolated by the silicon substrate 201 so that the concentration of the arsenic (or phosphorus) atoms becomes higher at the end of the channel in the width direction than at the center of the channel. This is called an inverse hump phenomenon that increases the absolute value of the threshold voltage V _thp , especially in short channel type MOS transistors.

In order to compensate for the above-described hump phenomenon, a prior art method for manufacturing a semiconductor device such as an n-channel MOS transistor is described with reference to Figs. 3A to 3J (Japanese Patent Laid-Open No. 2000-340791 and US Patent 6,492,220).

Referring first to Figure 3a, a silicon dioxide layer 302 and silicon nitride layer 303 is ^p-type single crystal silicon is deposited on the substrate (301). In this case, the silicon substrate 301 can be thermally oxidized to form the silicon dioxide layer 302. Thereafter, the opening 304 is penetrated into the silicon nitride layer 303 and the silicon dioxide layer 302 by a photolithography and etching process.

Next, referring to FIG. 3B, boron ions are implanted into the silicon substrate 301 using the silicon nitride layer 303 and the silicon dioxide layer 302 as masks. As a result, the p-type impurity region 305 is formed at the bottom of the opening 304 and below the silicon dioxide layer 302. That is, since the boron ions have a large diffusion coefficient with respect to the silicon substrate 301, the boron ions easily diffuse into the silicon substrate 301 along the horizontal and vertical directions.

Next, referring to FIG. 3C, the silicon substrate 301 is etched using the silicon nitride layer 303 and the silicon dioxide layer 302 as a mask. As a result, a trench (groove) 306 is formed in the silicon substrate 301.

Next, referring to FIG. 3D, the silicon dioxide layer 307 is formed in the trench 306 and silicon nitride layer 303 of the silicon substrate 301 by a thermal oxidation process and a chemical vapor deposition (CVD) process. And the opening 304 of the silicon dioxide layer 302.

Next, referring to FIG. 3E, the silicon dioxide layer 307, silicon nitride layer 303 and silicon dioxide layer 302 are planarized by a CMP (Chemical Mechanical Polishing) process. As a result, the silicon dioxide layer 307 remains only in the trench 306. Thus, the silicon dioxide layer 307 filled in the trench 306 functions as an STI layer to divide the element formation region (active area) from each other.

Next, referring to FIG. 3F, boron ions are implanted into the silicon substrate 301 to form a p-type impurity diffusion region 308 within the silicon substrate 301. The p-type impurity diffusion region 308 including the p-type impurity diffusion region 305 is used to adjust the threshold voltage V _thn of the n-channel MOS transistor to be formed.

Next, referring to FIG. 3G, after cleaning and rinsing the surface of the device, the silicon substrate 301 is thermally oxidized to form a silicon dioxide layer, and a polycrystalline silicon layer is deposited on the silicon dioxide layer by a CVD process. Thereafter, the polycrystalline silicon layer and the silicon dioxide layer are patterned by photolithography and etching processes to form the gate silicon dioxide layer 309 and the gate electrode 310.

Next, referring to FIG. 3H, arsenic ions are implanted into the silicon substrate 301 using the gate electrode 310 and the gate silicon dioxide layer 309 as masks. As a result, n for the LDD (Lightly-Doped Drain) ^{structure-type} impurity regions (311S, and 311D) are formed in the silicon substrate 301.

Next, referring to FIG. 3I, a silicon dioxide layer is deposited on the entire surface by a CVD process, and the silicon dioxide layer is etched again by an anisotropic etching process. As a result, sidewall silicon dioxide layer 312 is formed on the sidewalls of the gate silicon dioxide layer 309 and the gate electrode 310.

Finally, referring to FIG. 3J, arsenic ions are implanted back into the silicon substrate 301 using the gate electrode 310, the gate silicon dioxide layer 309, and the sidewall silicon dioxide layer 312 as a mask. As a result, n ⁺ -type impurity regions 313S and 313D each functioning as a source and a drain are formed in the silicon substrate 301.

4A is a plan view of an n-channel MOS transistor obtained by the method shown in FIGS. 3A-3J, FIG. 4B is a cross-sectional view along the BB line of FIG. 4A, and FIG. 4C is a p-type impurity region 305 and FIG. After 308 undergoes the heating or annealing process, the concentration of boron atoms in the p-type impurity region 308 including the p-type impurity region 305 of FIG. 4B to adjust the threshold voltage V _thn is adjusted. It is a graph to show.

As shown in Figs. 4A and 4B, a p-type impurity diffusion region 305 is provided on the entire periphery of the active region. Thus, as shown in FIG. 4C, when boron atoms are moved from the silicon substrate 301 to the STI layer 307 by the above-described heating or annealing process, because of the presence of the p-type impurity diffusion region 305, boron The concentration of atoms becomes uniform at the end of the channel in the center and width directions of the channel. Thus, the hump phenomenon can be compensated, which does not reduce the threshold voltage V _thn as shown in FIG. 5A where V _G is the gate voltage and I _d is the drain current. FIG. 5A is a graph showing sub-threshold characteristics of an n-channel MOS transistor obtained by the method shown in FIGS. 3A to 3J. That is, the sub-threshold characteristics of the n-channel MOS transistor obtained by the method shown in Figs. 3A to 3J, in which the p-type impurity diffusion region 305 is provided, are not provided with the p-type impurity diffusion region 305. Does not improve compared to the sub-threshold characteristics of n-channel MOS transistors. The improvement in the sub-threshold characteristics is mainly due to the p-type impurity diffusion region 305 located below the gate electrode 310, as shown by the hatching in FIG. 4A.

However, as shown in FIG. 5B, which is a graph showing breakdown voltage characteristics of an n-channel MOS transistor obtained by the method shown in FIGS. 3A-3J where V _D is the source-to-drain voltage and I _D is the drain current. Likewise, the breakdown voltage characteristic of the n-channel MOS transistor obtained by the method shown in FIGS. 3A to 3J in which the p-type impurity diffusion region 305 is provided is provided by the p-type impurity diffusion region 305. It is degraded compared to the breakdown voltage characteristic of the n-channel MOS transistor which is not. The degradation of the breakdown voltage characteristic is indicated by the heavily double-hatched portion in FIG. 4A, as shown by the p-type impurity diffusion region located in the source region 311S (313S) and the drain region 311D (313D). This is mainly due to 305. Therefore, especially when the degree of integration is improved to reduce the size of the impurity diffusion regions 311S (313S) and 311D (313D), the breakdown voltage characteristic is further degraded.

The prior art method described above is effective for p-channel MOS transistors in which the impurity diffusion regions 308, 311S (313S) and 311D (313D) of Figs. 3A to 3J are p-type. That is, even if the anti-hump phenomenon is compensated by the p-type impurity diffusion region 305 so that the sub-threshold characteristic is improved, the breakdown voltage characteristic is deteriorated.

A first embodiment of a method for manufacturing a semiconductor device, such as an n-channel MOS transistor, will now be described with reference to FIGS. 6A-6J.

First, referring to FIG. 6A, a silicon dioxide layer 12 and a silicon nitride layer 13 are deposited on the p ⁻ -type single crystal silicon substrate 11. In this case, the silicon dioxide layer 12 can be formed by thermally oxidizing the silicon substrate 11. Thereafter, the opening 14 is penetrated into the silicon nitride layer 13 and the silicon dioxide layer 12 by a photolithography and etching process.

Next, referring to FIG. 6B, the silicon substrate 11 is etched using the silicon nitride layer 13 and the silicon dioxide layer 12 as a mask. As a result, a trench (groove) 15 is formed in the silicon substrate 11.

Next, referring to FIG. 6C, the silicon dioxide layer 16 is formed of the trench 15 and the silicon nitride layer 13 and the silicon dioxide layer 12 of the silicon substrate 11 by a thermal oxidation process and a CVD process. The opening 14 is filled.

Next, referring to FIG. 6D, the silicon dioxide layer 16, silicon nitride layer 13 and silicon dioxide layer 12 are planarized by a CMP process. As a result, only the silicon dioxide layer 16 is left in the trench 15. Thus, the silicon dioxide layer 16 filled in the trench 15 functions as an STI layer to divide the element formation region (active region) from each other.

Next, referring to FIG. 6E, boron ions are implanted into the silicon substrate 11 to form the p-type impurity diffusion region 17 in the silicon substrate 11. The p-type impurity diffusion region 17 is used to adjust the threshold voltage V _thn of the n-channel MOS transistor to be formed.

Next, referring to FIG. 6F, a photoresist layer is applied on the entire surface, and the photoresist layer is patterned by a photolithography process, so that the STI layer 16 is only under the gate electrode 21 to be formed later. A photoresist pattern layer 18 having an opening 18a corresponding to a portion of the perimeter of the adjacent active region is formed. Photoresist pattern layer 18 is shown in FIG. 7. Thereafter, boron ions are implanted into the silicon substrate 11 using the photoresist pattern layer 18 as a mask. As a result, a p-type impurity diffusion region 19 not shown in FIG. 6F but shown in FIG. 7 is formed in the bottom of the opening 18a and in the p-type impurity diffusion region 17. That is, the boron ions have a large diffusion coefficient for the silicon substrate 11, i.e., the p-type impurity diffusion region 17, and the boron ions easily enter the p-type impurity diffusion region 17 along the horizontal and vertical directions. Spreads. Thereafter, the photoresist pattern layer 18 is removed by an ashing process or the like.

The size of the opening 18a in FIG. 6F is determined to compensate for the hump phenomenon of the p-type impurity diffusion region 17.

6G, after cleaning and rinsing the surface of the device, the silicon substrate 11 is thermally oxidized to form a silicon dioxide layer, and a polycrystalline silicon layer is deposited on the silicon dioxide layer by a CVD process. Thereafter, the polycrystalline silicon layer and the silicon dioxide layer are patterned by photolithography and an etching process to form the gate silicon dioxide layer 20 and the gate electrode 21.

In FIG. 6G, the gate silicon dioxide layer 20 is formed in self-alignment with the gate electrode 21 immediately after its formation, but before the silicide layer (not shown) is formed in a later step, the gate silicon dioxide layer ( 20) can be formed immediately.

Next, referring to FIG. 6H, arsenic ions are implanted into the silicon substrate 11 using the gate electrode 21 and the gate silicon dioxide layer 20 as a mask. As a result, n ⁻ -type impurity regions 22S and 22D for the LDD structure are formed in the silicon substrate 11.

Next, referring to FIG. 6I, a silicon dioxide layer is deposited on the entire surface by the CVD process, and the silicon dioxide layer is etched again by the anisotropic etching process. As a result, sidewall silicon dioxide layer 23 is formed on the sidewalls of the gate silicon dioxide layer 20 and the gate electrode 21.

Finally, referring to FIG. 6J, arsenic ions are implanted back into the silicon substrate 11 using the gate electrode 21, the gate silicon dioxide layer 20, and the sidewall silicon dioxide layer 23 as a mask. As a result, n ⁺ -type impurity regions 24S and 24D each functioning as a source and a drain are formed in the silicon substrate 11.

8A is a plan view of an n-channel MOS transistor obtained by the method shown in FIGS. 6A-6J, FIG. 8B is a cross-sectional view along the BB line of FIG. 8A, and FIG. 8C is a p-type impurity region 17 and 19) shows the concentration of boron atoms in the p-type impurity region 17 including the p-type impurity region 19 of FIG. 8B for adjusting the threshold voltage V _thn after this heating or annealing process. It is a graph.

As shown in Figs. 8A and 8B, a p-type impurity diffusion region 19 is provided on a portion of the periphery of the active region. Thus, as shown in FIG. 8C, when the boron atoms are moved from the silicon substrate 11 to the STI layer 16 by the above-described heating or annealing process, because of the presence of the p-type impurity diffusion region 19, boron The concentration of atoms becomes uniform at the end of the channel in the center and width directions of the channel. Thus, the hump phenomenon can be compensated, which does not reduce the threshold voltage V _thn , as shown in FIG. 9A where V _G is the gate voltage and I _d is the drain current. FIG. 9A is a graph showing the sub-threshold characteristics of the n-channel MOS transistor obtained by the method shown in FIGS. 6A to 6J. That is, the sub-threshold characteristic of the n-channel MOS transistor obtained by the method shown in Figs. 6A to 6J, in which the p-type impurity diffusion region 19 is provided, is provided with the p-type impurity diffusion region 305. It is improved in the same way as the sub-threshold characteristics of n-channel MOS transistors. The improvement of the sub-threshold characteristic is mainly due to the p-type impurity region 19 located below the gate electrode 21, as shown by the hatched portions in FIG. 8A.

At the same time, a graph showing the breakdown voltage characteristics of the n-channel MOS transistor obtained by the method shown in Figs. 6A to 6J when V _D is the source-to-drain voltage and I _D is the drain current is shown in Fig. 9B. As shown, the breakdown voltage characteristic of the n-channel MOS transistor obtained by the method shown in Figs. 6A to 6J, in which the p-type impurity diffusion region 19 is provided, is characterized by the p-type impurity diffusion regions 17 and 19. In comparison with the breakdown voltage characteristic of the n-channel MOS transistor, which is not provided), hardly deteriorates. In other words, the p-type impurity diffusion region 19 is not located at the periphery of the source regions 22S and 24S and the drain regions 22D and 24D. Therefore, especially when the degree of integration is improved to reduce the size of the impurity diffusion regions 22S, 24S and 22D, 24D, the breakdown voltage characteristic hardly deteriorates.

The first embodiment described above is effective for the p-channel MOS transistor in which the impurity diffusion regions 17, 22S (24S) and 22D (24D) in Figs. 6A to 6J are p-type. That is, the anti-hump phenomenon is compensated by the p-type impurity diffusion region 19 so that the sub-threshold characteristic is improved, and the breakdown voltage characteristic hardly deteriorates.

In the first embodiment described above, after the formation of the p-type impurity diffusion region 17, the p-type impurity diffusion region 19 is formed, but after the formation of the p-type impurity diffusion region 19, the p The -type impurity diffusion region 17 may be formed.

A second embodiment of a method for manufacturing a semiconductor device, such as two CMOS circuits, will now be described with reference to FIGS. 10A-10J. In this case, one CMOS circuit is a low breakdown voltage CMOS circuit formed by one n-channel MOS transistor Q _n1 and one p-channel MOS transistor Q _p1 powered at 3.3V, and the other The CMOS circuit is a high breakdown voltage CMOS circuit formed by one n-channel MOS transistor Q _n2 and one p-channel MOS transistor Q _p2 powered at 5V.

First, referring to FIG. 10A, an STI layer 32 is formed in the p ⁻ − type single crystal silicon substrate 31 similar to the silicon substrates of FIGS. 6A, 6B, 6C, and 6D. As a result, the element formation regions (active regions) for the transistors Q _n1 , Q _p1 , Q _n2 and Q _p2 are divided from each other.

Next, referring to FIG. 10B, a photoresist pattern layer 33 having an opening 33a corresponding to the n-channel MOS transistor Q _n2 is formed on the silicon substrate 31 by a photolithography process. Then, using the photoresist pattern layer 33 is used as a mask, boron ions are implanted at a relatively high energy into the silicon substrate (31), p ^{- -} type impurity to form the diffusion well 34. The

Next, referring to Figure 10c, the photoresist pattern by using the layer 33 as a mask, boron is ion implanted at relatively low energy into the silicon substrate (31), p ^{- -} type impurity doped in the well (34) p- The type impurity diffusion region 35 is formed. The p-type impurity diffusion region 35 is used to adjust the threshold voltage V _thn2 of the n-channel MOS transistor Q _n2 . Thereafter, the photoresist pattern layer 33 is removed by an ashing process or the like.

Next, referring to FIG. 10D, a photoresist pattern layer 36 having an opening 36a corresponding to the p-channel MOS transistor Q _p2 is formed on the silicon substrate 31 by a photolithography process. Then, using the photoresist pattern layer 36 as a mask, it is the arsenic (or phosphorous) ion implantation at a relatively high energy into the silicon substrate (31), ^n-type impurity diffusion to form a well (37).

Next, referring to Figure 10e, the photoresist pattern layer 36 is the arsenic (or phosphorous) ion implantation at relatively low energy into the silicon substrate 31 by using a mask, n ^- - type impurity doped well (34 N-type impurity diffusion region 38 is formed in the X-rays. An n-type impurity diffusion region 38 is used to adjust the threshold voltage V _thp2 of the p-channel MOS transistor Q _p2 . Thereafter, the photoresist pattern layer 36 is removed by an ashing process or the like.

Next, referring to FIG. 10F, the n-channel MOS adjacent to the opening 39a corresponding to the n-channel MOS transistor Q _n1 and the STI layer 32 which is only below the gate electrode 47 to be formed later. Activation of the n-channel MOS transistor Q _p2 adjacent the opening 39b corresponding to a portion of the periphery of the active region of the transistor Q _n2 and the STI layer 32 which is only below the gate electrode 47 to be formed later. A photoresist pattern layer 39 having an opening 39c corresponding to a portion of the periphery of the region is formed on the silicon substrate 31 by a photolithography process. Then, the picture by using the resist pattern layer 39 is used as a mask, boron ions are implanted at relatively low energy into the silicon substrate (11), which functions as a p-type impurity doped p- well in the ^case-type silicon substrate A p-type impurity diffusion region 40 is formed in 31. The p-type impurity diffusion region 40 is used to adjust the threshold voltage V _thn1 of the n-channel MOS transistor Q _n1 . At the same time, a p-type impurity diffusion region (not shown) is formed at the bottom of the opening 39b in the p-type impurity diffusion region 35 and at the bottom of the opening 39c in the n-type impurity diffusion region 38, It compensates for the hump phenomenon and the reverse-hump phenomenon. Thereafter, the photoresist pattern layer 39 is removed by an ashing process or the like.

The sizes of the openings 39b and 39c in FIG. 10F are determined to compensate for the hump phenomenon and the anti-hump phenomenon.

Next, referring to FIG. 10G, a photoresist pattern layer 41 having an opening 41a corresponding to the p-channel MOS transistor Q _p1 is formed on the silicon substrate 31 by a photolithography process. Then, using the photoresist pattern layer 41 as a mask is arsenic (or phosphorus) ions are implanted at a relatively high energy into the silicon substrate (31), ^n-type impurity diffusion to form a well (42).

Next, referring to Figure 10h, by using the photoresist pattern layer 41 as a mask is arsenic (or phosphorus) ions are implanted at relatively low energy into the silicon substrate (31), n ^{- -} type impurity doped well ( An n-type impurity diffusion region 43 is formed in 42). An n-type impurity diffusion region 43 is used to adjust the threshold voltage V _thp1 of the p-channel MOS transistor Q _p1 . Thereafter, the photoresist pattern layer 41 is removed by an ashing process or the like.

Next, referring to FIG. 10I, a relatively thick gate silicon dioxide layer 44 is formed on the entire surface. When the silicon substrate 31 is thermally oxidized to form a relatively thick gate silicon dioxide layer 44, a relatively thick gate silicon dioxide layer 44 is not formed on the STI layer 32.

Next, referring to FIG. 10J, a photoresist pattern layer 45 is formed on the gate silicon dioxide layer 44 only on the transistors Q _n2 and Q _p2 . Thereafter, the gate silicon dioxide layer 44 on the transistors Q _n1 and Q _p1 sides is selectively etched using the photoresist pattern layer 45 as an etching mask. Thereafter, the photoresist pattern layer 45 is removed by an ashing process or the like.

Next, referring to FIG. 10K, a relatively thin gate silicon dioxide layer 46 is formed on the entire surface. Although not shown in this case, the relatively thick gate silicon dioxide layer 44 also becomes thicker. When the silicon substrate 31 is thermally oxidized to form a relatively thin gate silicon dioxide layer 46, the relatively thin gate silicon dioxide layer 46 is not formed on the STI layer 32.

Thus, while relatively thin gate silicon dioxide layer 46 is used for the low breakdown voltage transistors Q _n1 and Q _p1 , the relatively thick gate silicon dioxide layer 44 is used for the high breakdown voltage transistors Q _n2 and Q _p2 ).

Next, referring to FIG. 10L, a polycrystalline silicon layer 47 is deposited on the gate silicon dioxide layers 44 and 46 by a CVD process. Thereafter, photoresist pattern layer 48 is formed by a photolithography process.

Next, referring to FIG. 10M, the polycrystalline silicon layer 47 is etched using the photoresist pattern layer 48 as an etching mask to form the gate electrode. Thereafter, the photoresist pattern layer 48 is removed by an ashing process or the like.

Next, referring to FIG. 10N, a photoresist pattern layer 49 having an opening 49a corresponding to the n-channel MOS transistor Q _n2 is formed on the gate silicon dioxide layer 44 by a photolithography process. do. Then, the photoresist pattern layer 49 for use as a mask is arsenic (or phosphorus) ions are implanted at relatively low energy into the silicon substrate (31), n for the LDD structure ^- the type impurity diffusion region 50 - Form. Thereafter, the photoresist pattern layer 49 is removed by an ashing process or the like.

Next, referring to FIG. 10O, a photoresist pattern layer 51 having an opening 51a corresponding to the p-channel MOS transistor Q _p2 is formed on the gate silicon dioxide layer 44 by a photolithography process. do. Then, using the photoresist pattern layer 51 as a mask, boron is ion implanted at relatively low energy into the silicon substrate (31), p for the LDD ^structure form a type impurity diffusion region 52. Thereafter, the photoresist pattern layer 51 is removed by an ashing process or the like.

Next, referring to FIG. 10P, a photoresist pattern layer 53 having an opening 53a corresponding to the n-channel MOS transistor Qn1 is formed on the gate silicon dioxide layer 46 by a photolithography process. . Then, using the photoresist pattern layer 53 as a mask, arsenic (or phosphorus) ions are implanted, n for the LDD structure at relatively low energy into the silicon substrate 31, ^- the type impurity diffusion region 54 - Form. Thereafter, the photoresist pattern layer 53 is removed by an ashing process or the like.

n ^- - type the concentration of the impurity diffusion region (54) n ^{- -} type breakdown voltage of the impurity diffused region 50 is further large, n- channel MOS transistor (Q _n1) than the concentration of the n- channel MOS transistor (Q _n2 ) is smaller than the breakdown voltage.

Next, referring to FIG. 10Q, a photoresist pattern layer 55 having an opening 55a corresponding to the p-channel MOS transistor Q _p1 is formed on the gate silicon dioxide layer 46 by a photolithography process. do. Then, using the photoresist pattern layer 55 as a mask, boron is ion implanted at relatively low energy into the silicon substrate (31), p for the LDD ^structure form a type impurity diffusion region 56. Thereafter, the photoresist pattern layer 55 is removed by an ashing process or the like.

p ^- - type the concentration of the impurity diffusion region (56) p ^{- -} type impurity breakdown voltage the p- channel MOS transistor (Q a diffusion region 52 more cursor, p- channel MOS transistor (Q _p1) than the concentration of Note that it is smaller than the breakdown voltage of _p2 ).

Next, referring to FIG. 10R, a silicon dioxide layer is deposited on the entire surface by a CVD process, and the silicon dioxide layer is etched again by an anisotropic etching process. As a result, sidewall silicon dioxide layer 57 is formed on the sidewall of the gate electrode 47.

Next, referring to FIG. 10S, a photoresist pattern layer 58 having openings 58a and 58b corresponding to n-channel MOS transistors Q _n2 and Q _{n1 is} formed by a gate silicon dioxide layer ( 44 and 46). Thereafter, using photoresist pattern layer 58 as a mask, arsenic (or phosphorus) ions are implanted into the silicon substrate 31 at a relatively high energy to form an n ⁺ -type impurity diffusion region 59. Thereafter, the photoresist pattern layer 58 is removed by an ashing process or the like.

Next, referring to FIG. 10T, the photoresist pattern layer 60 having openings 60a and 60b corresponding to the p-channel MOS transistors Q _p2 and Q _p1 is subjected to a gate silicon dioxide layer ( 44 and 46). Thereafter, boron ions are implanted at a relatively high energy into the silicon substrate 31 using the photoresist pattern layer 60 as a mask to form the p ⁺ -type impurity diffusion region 61. Thereafter, the photoresist pattern layer 60 is removed by an ashing process or the like.

Thus, a CMOS semiconductor device having two kinds of breakdown voltages is obtained as shown in Fig. 10u. Before the silicide layer (not shown) is formed in the post step, the gate silicon dioxide layers 44 and 46 are immediately removed on the impurity diffusion regions 59 and 61. However, the gate silicon dioxide layers 44 and 46 on the impurity diffusion regions 50, 52, 54, 56, 59, and 61 may be removed by self-alignment with the gate electrode 47 immediately after the gate electrode 47 is formed. Can be.

In the above-described second embodiment, the formation of p-type impurity regions (not shown) under the openings 39b and 39c in FIG. 10F is performed by the p-type impurity diffusion regions 40 under the opening 39a in FIG. 10F. Performed concurrently with the formation, no additional process for the previous p-type impurity diffusion region is needed, which does not increase the manufacturing step.

Further, in the above-described second embodiment, the p-type impurity region under the openings 39b and 39c is in a part of the active region adjacent to the STI layer which is only below the gate electrode, but as in the prior art, the entire periphery of the active region Even when such a p-type impurity diffusion region is formed, an additional process for this is unnecessary and does not increase the manufacturing step.

In the above embodiment, the thick device isolation layer is formed by the STI layer, but this thick device isolation layer may be formed by the LOCOS layer.

As described above, according to the present invention, the breakdown voltage characteristic can be improved while the hump phenomenon or the anti-hump phenomenon is compensated, so that the sub-threshold characteristic is maintained.

Claims (24)

Forming a MOS transistor isolation layer 16 in the semiconductor substrate 11 so as to surround a region for forming the MOS transistor in the semiconductor substrate 11, Injecting a first impurity into the region of the semiconductor substrate to adjust the threshold voltage of the MOS transistor, and Injecting a second impurity only into a portion of the periphery of the region adjacent to the MOS transistor isolation layer where the gate electrode (21) of the MOS transistor is to be formed. The method of claim 1, And the first impurity and the second impurity are both boron atoms. The method of claim 1, And the first impurity is an arsenic atom and the second impurity is a boron atom. The method of claim 1, And the first impurity is a phosphorus atom and the second impurity is a boron atom. The method of claim 1, Wherein said semiconductor substrate comprises a silicon substrate and said MOS transistor isolation layer comprises a silicon dioxide layer. The method of claim 5, And the silicon dioxide layer comprises a shallow trench isolation (STI) layer. The method of claim 5, And the silicon dioxide layer comprises a Local Oxidation of Silicon (LOCOS) layer. A method for manufacturing a semiconductor device comprising first and second MOS transistors (Q _n2 , Q _p2 ; Q _n1 ), Forming a MOS transistor isolation layer 32 in the semiconductor substrate 31 to surround the first and second regions for forming the first and second MOS transistors in the semiconductor substrate 31, respectively, Implanting a first impurity into the first region of the semiconductor substrate to adjust a first threshold voltage of the first MOS transistor, Injecting a second impurity into the second region of the semiconductor substrate to adjust a second threshold voltage of the second MOS transistor, and Implanting a third impurity only into a portion of the periphery of the first region adjacent to the first MOS transistor isolation layer where the gate electrode 47 of the first MOS transistor is to be formed, And the second and third impurities are the same impurity. The method of claim 8, And the implantation of the second and third impurities is performed simultaneously. The method of claim 8, And wherein the first, second and third impurities are all boron atoms. The method of claim 8, The first impurity is an arsenic atom, and the second and third impurities are boron atoms. The method of claim 8, And said first impurity is a phosphorus atom and said second and third impurities are boron atoms. The method of claim 8, And the breakdown voltage of the first MOS transistor is higher than the breakdown voltage of the second MOS transistor. The method of claim 8, And the semiconductor substrate comprises a silicon substrate and the MOS transistor isolation layer comprises a silicon dioxide layer. The method of claim 14, And the silicon dioxide layer comprises an STI layer. The method of claim 14, And the silicon dioxide layer comprises a LOCOS layer. A method for manufacturing a semiconductor device comprising first and second MOS transistors (Q _n2 , Q _p2 ; Q _n1 ), Forming a MOS transistor isolation layer 32 in the semiconductor substrate 31 to surround the first and second regions for forming the first and second MOS transistors in the semiconductor substrate 31, respectively, Implanting a first impurity into the first region of the semiconductor substrate to adjust a first threshold voltage of the first MOS transistor, Injecting a second impurity into the second region of the semiconductor substrate to adjust a second threshold voltage of the second MOS transistor, and Injecting third impurities into the entire periphery of the first region adjacent to the first MOS transistor isolation layer where the gate electrode 47 of the first MOS transistor is to be formed, And the second and third impurities are the same impurities, and implantation of the second and third impurities is performed simultaneously. As a method of manufacturing a field effect transistor, Forming a transistor isolation layer (16) surrounding a first region for forming said field effect transistor in a semiconductor substrate (11); Adjusting a threshold voltage of the field effect transistor by implanting a first impurity into the first region; And Implanting a second impurity into the second region in the first region, And the second region is disposed only adjacent to a cross line between the gate electrode (21) to be formed on the first region and the transistor isolation layer and the transistor isolation layer. The method of claim 18, And the field effect transistor is a MOS transistor. The method of claim 18, And the first impurity and the second impurity have the same conductivity type. As a method of manufacturing field effect transistors (Q _n2 , Q _p2 ; Q _n1 ), Forming a first isolation layer and a second isolation layer 32 in the semiconductor substrate 31 respectively surrounding the first region for forming the first field effect transistor and the second region for forming the second field effect transistor. Forming a first separation layer and a second separation layer, wherein the second region is different from the first region, and wherein each of the first region and the second region is in the semiconductor substrate; Adjusting a threshold voltage of the first field effect transistor by implanting a first impurity into the first region; And Implanting a second impurity into the second region and a third region within the first region, The second impurity into the second region is for adjusting the threshold voltage of the second field effect transistor, And the third region is disposed only adjacent to a cross point between the gate electrode (47) to be formed on the first region and the first separation layer and the first separation layer. The method of claim 21, Wherein each of the field effect transistors is a MOS transistor. The method of claim 21, And the first and second impurities have the same conductivity type. As a method of manufacturing a field effect transistor, Forming a transistor isolation layer (16) on a semiconductor substrate (11) surrounding a region for forming the field effect transistor; Adjusting a threshold voltage of the field effect transistor by implanting a first impurity into the region; And Selectively implanting a second impurity into a portion of the region disposed adjacent to the cross line between the region and the gate electrode 21 to be formed on the region and the transistor isolation layer, And the second impurity has the same conductivity type as the first impurity.

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