KR100774797B1 - Array Board of Thin Film Transistor Liquid Crystal Display - Google Patents

Abstract

The present invention discloses an array substrate of a thin film transistor liquid crystal display device which prevents light leakage and smudges caused by voltages between a data line and a pixel electrode. An array substrate of a thin film transistor liquid crystal display device according to the present invention, the transparent insulating substrate; A gate line and a data line arranged to be orthogonal to each other on the substrate; A thin film transistor disposed at an intersection of the gate line and the data line; A pixel electrode disposed in the pixel region defined by the gate line and the data line; And a metal pattern disposed below the data line so as not to be connected to the gate line and having an ITO pattern and a gate line interposed between the metal pattern disposed below the data line and the upper portion of the data line. And a metal box including a connection pattern interconnecting adjacent ITO patterns.

Description

Array substrate of thin film transistor liquid crystal display

1 is a plan view showing an array substrate of a conventional thin film transistor liquid crystal display device.

2 is a plan view showing an array substrate of a thin film transistor liquid crystal display device according to the present invention;

3A to 3E are cross-sectional views illustrating processes for forming a metal box in an array substrate according to the present invention.

Explanation of symbols on the main parts of the drawings

1: glass substrate 2: gate line

2a: gate electrode 3: gate insulating film

4: channel layer material 5: ohmic layer material

6: data line 6a: source electrode

6b: drain electrode 7: insulating film

8 pixel electrode 10 thin film transistor

12 metal pattern 13 via hole

14: ITO pattern 15: connection pattern

20: metal box 30: ground

The present invention relates to a thin film transistor liquid crystal display device, and more particularly, to an array substrate of a thin film transistor liquid crystal display device which prevents light leakage and smudges caused by an unwanted electric field between a data line and a pixel electrode.

Liquid Crystal Display is widely used in electronic calculators, electronic clocks, office automation devices, display devices of automobiles and aircrafts in place of CRT (Cathode Ray Tube) due to its light weight, thinness and low power consumption. Has been.

In particular, the thin film transistor liquid crystal display device (hereinafter, TFT-LCD) having a thin film transistor (Thin Film Transistor) as a switching element for each pixel realizes high quality and large size display screen comparable to the CRT. Of course, the TV market is in the spotlight.

In the typical TN (Twist Nematic) mode, the TFT-LCD has a black matrix, a color filter, and a common electrode on an array substrate and a glass substrate in which gate lines, data lines, thin film transistors, and pixel electrodes are formed on a glass substrate. The formed color filter substrate has a structure where the color filter substrate is bonded under the interposition of the liquid crystal layer composed of a plurality of liquid crystal molecules, and a polarizing plate is formed on each of the outer surfaces of the substrates to realize white and dark. It is attached.

1 is a plan view illustrating an array substrate of a conventional TFT-LCD, which will be described below.

As shown, the gate line 2 and the data line 6 are arranged on the glass substrate 1 so as to intersect with each other, and the switching portion of the gate line 2 and the data line 6 is a switching element. The TFT 10 is disposed, and a pixel electrode 8 made of a transparent metal such as ITO is disposed in the pixel region defined by the gate line 2 and the data line 6. Here, the TFT 10 is disposed on a gate electrode 2a extending to the gate line 2, a channel layer (not shown) disposed on the gate electrode 2a, and one side of the channel layer. And a source electrode 6a in contact with the pixel electrode 8, and a drain electrode 6b drawn from the data line 6 and disposed on the other side of the channel layer.

Subsequently, a shield bar 9 is disposed in the space between the data line 6 and the pixel electrode 8 to reduce the bonding margin between the array substrate and the color filter substrate during assembly of the substrates. Specifically, the shield bar 9 is a member that is formed together when the gate line 2 is formed. The data line 6 and the pixel electrode 8 may be formed even when a slight misalignment occurs when the array substrate and the color filter substrate are bonded together. By blocking the light transmitted through the space between the), as a result, it serves to secure the bonding margin between the substrates.

Although not shown, an insulating film is interposed between the gate line 2 and the data line 6 and between the data line 6 and the pixel electrode 8 for electrical insulation, respectively, and the channel layer and the source. An ohmic layer is interposed between the / drain electrodes 6a and 6b in order to improve contact characteristics therebetween.

However, the conventional array substrate described above has the following problems.

In general, unwanted capacitance, that is, parasitic capacitance, is generated between the pixel electrode and the data line in the array substrate, and the parasitic capacitance may vary in size depending on the degree of misalignment in the mask process. In particular, since the array substrate of the TFT-LCD is formed through a split exposure process, the parasitic capacitance may be different for each pixel. If the parasitic capacitance is different for each pixel, the pixel driving is adversely affected.

In detail, when manufacturing the array substrate, if the gap between the pixel electrode and the data line is narrowed due to misalignment, parasitic capacitance is increased, and thus, the arrangement characteristics of the liquid crystal at the edges are different from those of the center of the pixel. The charge is induced at the edges of the adjacent pixel electrodes in connection with the application of the signal voltage to the data line, and the induced charges change according to the swing of the data signal, so that the driving of the edge liquid crystal is more strongly influenced than the center portion. As a result, light leakage or spots occur at the pixel edges. Here, the induced charge Q is proportional to the capacitance Cdp between the pixel electrode and the data line and the voltage V, that is, the voltage difference between the pixel electrode and the data line, respectively. (Q = C · V)

On the other hand, since the parasitic capacitance generated between the pixel electrode and the data line decreases as the distance between them increases, the problem caused by the parasitic capacitance can be solved by maintaining a constant distance.

However, the voltage between the pixel electrode and the data line, more specifically, the voltage applied to the data line should continue to change between positive and negative, which is to be maintained for one period by an arbitrary pixel voltage. Liquid crystals are influenced by the induced charge generated by the difference between the pixel voltage and the signal voltage at the edge of the pixel, for example, a voltage of +5 V is applied to the pixel electrode and -5 V is applied to the data line. Therefore, the problem caused by the voltage between the pixel electrode and the data line, that is, the problem of light leakage and smearing at the pixel edge cannot be solved.

In addition, the problem caused by the voltage between the pixel electrode and the data line is currently solved by covering the pixel edge region with the black matrix of the color filter substrate. As a result, the aperture ratio is reduced.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and an array of TFT-LCDs is provided to prevent variations in liquid crystal array characteristics at pixel edges caused by voltage variations between pixel electrodes and data lines. The purpose is to provide a substrate.

Another object of the present invention is to provide an array substrate of a TFT-LCD having improved screen quality by preventing liquid crystal array characteristic variation at the pixel edge.

In addition, it is another object of the present invention to provide an array substrate of a TFT-LCD in which the aperture ratio reduction is prevented by not masking the pixel edge region with a black matrix.

In order to achieve the above object, the present invention, a transparent insulating substrate; A gate line and a data line arranged to be orthogonal to each other on the substrate; A TFT disposed at an intersection of the gate line and the data line; A pixel electrode disposed in the pixel region defined by the gate line and the data line; And a metal pattern disposed below the data line so as not to be connected to the gate line and having an ITO pattern and a gate line interposed between the metal pattern disposed below the data line and the upper portion of the data line. It provides an array substrate of a TFT-LCD comprising a; metal box consisting of a connection pattern for interconnecting adjacent ITO patterns.

Here, the metal pattern is connected to the ground at the outside of the display area.

The metal pattern is formed with a gate line.

The connection pattern is made of ITO and integrally formed with the ITO pattern.

The ITO pattern and the connection pattern are formed together with the pixel electrode.

An insulating film is interposed between the metal pattern and the data line and between the data line and the ITO pattern, and the ITO pattern is connected to the metal pattern through a straight via hole parallel to the data line provided in the insulating film.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a plan view illustrating an array substrate of a TFT-LCD according to an embodiment of the present invention. Here, the same parts as in Fig. 1 are designated by the same reference numerals.

As shown, the array substrate of the present invention comprises a glass substrate 1 which is a transparent insulating substrate, a gate line 2 and a data line 6 arranged so as to be orthogonal to each other on the glass substrate 1, and the gate. TFT 10, which is a switching element disposed at the intersection of the line 2 and the data line 6, and the pixel electrode 8 disposed in the pixel region defined by the gate line 2 and the data line 6; And a metal box 20 formed in the data line forming portion so as not to be connected to the gate line 2.

Here, the TFT 10 is disposed on a gate electrode 2a extending to the gate line 2, a channel layer (not shown) disposed on the gate electrode 2a, and one side of the channel layer. And a source electrode 6a in contact with the pixel electrode 8, and a drain electrode 6b drawn from the data line 6 and disposed on the other side of the channel layer.

The metal box 20 is a member for preventing light leakage or spots at the edge of the pixel due to the voltage between the data line 6 and the pixel electrode 8, and is formed under the gate line. A metal pattern 12 formed under the interposition of the metal pattern 12 and the data line 6 interposed between the ITO pattern 14 and the gate line 2 electrically connected to the metal pattern 12. And a connection pattern 15 for interconnecting the adjacent ITO patterns 14. In this case, the metal pattern 12 is connected to the ground 30 outside the display area. That is, the metal pattern 12 disposed outside the display area is connected to the ground 30. The ITO pattern 14 is connected to the metal pattern 12 through a straight via hole formed in the insulating film in parallel with the data line 6. The connection pattern 15 is made of ITO, and preferably, is integrally formed with the ITO pattern 14.

As described above, the array substrate of the present invention in which the metal box 20 is formed to surround the data line 6 has the data line 6 at the pixel edge, that is, in the region between the data line 6 and the pixel electrode 8. ) And the liquid crystal array are changed by the voltage between the pixel electrode 8 and the light leakage or spots are prevented.

Specifically, the pixel electrode 8 charged by the signal applied through the data line 6 maintains a constant voltage for one period, while the voltages applied to the data line 6 are positive (+) and negative ( As the voltage of-) changes, the voltage between the data line 6 and the pixel electrode 8 changes. Thus, an unwanted liquid crystal array variation occurs at the pixel edge. In the present invention, since the data line 6 is surrounded by the metal box 20, the voltage applied to the data line 6 is positive. Even if it changes to +) and negative (-), the liquid crystal at the edge of the pixel is not affected.

That is, in FIG. 1, when the pixel electrode 8 is charged with (+), a relatively strong voltage is formed when the data signal is negative, thereby affecting the liquid crystals at the edge of the pixel, as shown in FIG. 2. In the present invention, since the data box 6 is surrounded by the metal box 20 and the metal box 20 is connected to the ground 30, the swinging electric field of the data line 6 does not come out. Therefore, only a weak electric field between the pixel electrode 8 and the ground 30 is generated. As a result, the arrangement fluctuation of the liquid crystal at the pixel edge and consequently light leakage or staining are prevented.

Therefore, the array substrate of the present invention can effectively prevent the liquid crystal array characteristic variation at the pixel edge caused by the voltage variation between the data line and the pixel electrode, thereby improving the screen quality of the TFT-LCD.

In addition, since the array substrate of the present invention does not need to cover the pixel edge region with the black matrix, the aperture ratio can also be increased.

Hereinafter, a method of forming the metal box 20 will be briefly described with reference to FIGS. 3A to 3E. 3A to 3E are cross-sectional views corresponding to the line AA ′ of FIG. 2.

Referring to FIG. 3A, a metal pattern 12 is formed on the glass substrate 1. The metal pattern 12 is formed together with a gate line including a gate electrode, and is formed to be disposed in an area where a data line is to be formed in a range that is not in contact with the gate line and does not overlap the pixel electrode. In this case, the metal pattern 12 disposed outside the display area is preferably formed to be connected to the ground.

Referring to FIG. 3B, a gate insulating film 3 is formed on the entire surface of the substrate 1 to cover the metal pattern 12. Next, an active pattern is formed on the gate insulating layer on the metal pattern 12. The active pattern is formed of a laminated film of the channel layer material 4 and the ohmic layer material 5, and is formed together when the channel layer and the ohmic layer of the TFT 10 are formed. Preferably, the active pattern is formed in a region where a data line is to be formed.

Referring to FIG. 3C, the data line 6 is formed to surround the active pattern. At this time, when the data line 6 is formed, the source / drain electrodes of the TFT are formed together at the intersection of the gate line and the data line 6. Next, an insulating film 7 is formed on the entire surface of the resultant material to cover the data line 6.

Referring to FIG. 3D, the insulating layer 7 and the gate insulating layer 3 are etched to form straight via holes 13 exposing the metal pattern portions on both sides of the data line 6. Here, the via holes 13 are formed together during the etching of the insulating film 7 for exposing the source electrodes of the TFTs.

Referring to FIG. 3E, an ITO thin film is deposited on the insulating film 7, and then patterned to form an ITO pattern 14 electrically connected to the metal pattern 13 through the via hole 13. As a metal box 20 according to the present invention is formed. Here, the ITO pattern 14 is formed together when forming the pixel electrode in the pixel region.
At this time, although not shown, when the ITO pattern 14 is formed, a connection pattern 15 for interconnecting adjacent ITO patterns 14 with a gate line therebetween is integrally formed with the ITO pattern 14. Are formed together.

As described above, the present invention connects the metal box to the ground while forming the metal box in a form surrounding the data line, thereby preventing the liquid crystal array characteristic variation at the pixel edge caused by the voltage variation between the data line and the pixel electrode. It is possible to effectively prevent and, therefore, to improve the screen quality of the TFT-LCD.

In addition, in the array substrate of the present invention, the pixel edge region does not have to be covered by the black matrix of the color filter substrate, so that the aperture ratio can be improved.

As mentioned above, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (9)

Transparent insulating substrates; A gate line and a data line arranged to be orthogonal to each other on the substrate; A thin film transistor disposed at an intersection of the gate line and the data line; A pixel electrode disposed in the pixel region defined by the gate line and the data line; And It is formed to surround the data line so as not to be connected to the gate line, with a metal pattern disposed below the data line and an ITO pattern and a gate line formed to be connected to the metal pattern on the data line. An array substrate of a thin film transistor liquid crystal display device comprising a metal box consisting of a connection pattern interconnecting adjacent ITO patterns. The array substrate of claim 1, wherein the metal pattern is connected to ground at an outer edge of the display area. The array substrate of claim 1, wherein the metal pattern is formed together with a gate line. 2. The array substrate of claim 1, wherein the connection pattern is made of ITO. The array substrate of claim 1, wherein the connection pattern is integrally formed with an ITO pattern. The array substrate of claim 5, wherein the ITO pattern and the connection pattern are formed together with a pixel electrode. The array substrate of claim 1, further comprising an insulating layer interposed between the metal pattern and the data line and between the data line and the ITO pattern. 8. The array substrate of claim 7, wherein the ITO pattern is connected to the metal pattern through via holes provided in the insulating layer. 10. The array substrate of claim 8, wherein the via hole has a linear shape parallel to the data line.

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