KR100766668B1 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

An object of the present invention is to realize a low on-resistance switch element at low cost.

A switch for switching currents on and off on the first main surface side of the N ⁺ type SiC substrate 2 and the N ⁻ type drain region 1 and the N ⁺ type SiC substrate 2 which are the first conductive semiconductor substrates. a semiconductor device having a mechanism, N ^- the type drain region (1) the N ^- this type drain region (1) and the band gap is formed in the other P ⁺ type polysilicon, the first major surface and the first major surface A plurality of columnar hetero semiconductor regions 4 extending between the second main surfaces facing each other are formed side by side at intervals.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME}

BRIEF DESCRIPTION OF DRAWINGS Fig. 1 is a sectional view showing the structure of an element portion of a semiconductor device of a first embodiment of the present invention.

Fig. 2 is a sectional view showing the structure of an element portion of the semiconductor device of the second embodiment of the present invention.

3 is a sectional view showing a schematic structure of a heterojunction in the present invention.

<Explanation of symbols for main parts of the drawings>

1: N ^- type SiC drain region

2: N ⁺ type SiC substrate

3: P type well area

4: P ⁺ type polysilicon hetero semiconductor region

5: N ⁺ type source region

6: gate insulating film

7: gate electrode

8: source electrode

9: drain electrode

10: channel area

11: home

12: gate insulating film

13: U gate electrode

14: N ^- type SiC drain region

15: P ⁺ type polysilicon hetero semiconductor region

Proceedings of 2004 Internationl Symposiumon Power Semiconductor Devices & ICs, Kitakyushu

[Document 2] Japanese Unexamined Patent Publication No. 2003-318398

The present invention relates to a semiconductor device and a method of manufacturing the same.

As a conventional technique, for example, there is a so-called SJ (superjunction) type power MOSFET described in Non-Patent Document 1 below.

In this SJ-MOSFET, while using Si as a material, the theoretical performance determined by the material of Si can be overcome. In this SJ-MOSFET, the PNPN. The impurity region of is formed in a sandwich shape. With this structure, the depletion layer is extended in the horizontal direction to enable simultaneous depletion of the entire drift region, which was not possible in the conventional structure, thereby increasing the impurity concentration in the P-type region than in the conventional structure, thereby lowering the ON resistance. It is possible to plan anger.

[Non-Patent Document 1] Proceedings of 2004 Internationl Symposiumon Power Semiconductor Devices & ICs, Kitakyushu, p.459-462

Since the SJ structure requires the P-type and N-type columnar structures, it is necessary to form the P-type columnar structure on the N-type semiconductor substrate having a depth corresponding to the device breakdown voltage.

Therefore, since the element is created by repeating the epitaxial growth of multiple stages and the process of introducing impurities into the patterned area after each epitaxial growth a plurality of times, there is a problem that the cost is high.

An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can realize a switch element having a low on resistance at low cost.

MEANS TO SOLVE THE PROBLEM In order to solve the said subject, this invention is a semiconductor device which has a switch mechanism which switches ON / OFF of an electric current in the 1st main surface side of a 1st conductivity type semiconductor base body, The said semiconductor device has the said A structure in which a band gap is formed from a semiconductor material different from the semiconductor substrate, and a plurality of columnar hetero semiconductor regions extending between the first main surface and the second main surface opposite to the first main surface are formed side by side at a distance. It is.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described in detail using drawing. In addition, in the drawing demonstrated below, the thing with the same function attaches | subjects the same code | symbol, and the repeated description is abbreviate | omitted.

<< first embodiment >>

<Configuration>

A first embodiment of the present invention will be described with reference to FIG. 1 is a cross-sectional view showing the structure of an element portion of a semiconductor device of a first embodiment of the present invention.

Referring to the configuration shown in FIG. 1, a drain region 1 made of N ⁻ type SiC epitaxially grown on an N ⁺ type SiC (silicon carbide) substrate 2 is formed. A power MOSFET is formed on the first main surface side of the N ⁻ type SiC drain region 1. The poly type of SiC may be 4H, 6H, or 3C. Instead of SiC, GaN and diamond, which are excellent wide band gap materials for power device applications, may be used.

Here, the power MOSFET as the switch mechanism may be a switch mechanism in another switch device. For example, a switch mechanism using a heterojunction described in JFET, MESFET, bipolar transistor, and Japanese Patent Laid-Open No. 2003-318398 may be used. In the case of the power MOSFET, for example, the P type well region 3 and the N ⁺ type source region 5 are formed by double diffusion using the edge of the gate electrode 7 formed through the gate insulating film 6. do. A channel region 10 is formed on the surface of the P type well region 3 in contact with the N ⁺ type source region 5 and directly under the gate electrode 7. By controlling the potential applied to the gate electrode 7, the current between the drain electrode 9 and the source electrode 8 is switched on and off. In other words, the switch mechanism in the case of the power MOSFET refers to the gate electrode 7, the gate insulating film 6, and the channel region 10. In addition, in the case of the JFET, a relatively deep P-type well region is formed at a low concentration so as to sandwich the relatively thin N-type source region, for example. This P-type well region becomes a gate region, and a gate electrode is formed thereon, and the region sandwiched by the deep P-type well region becomes a channel region. A switch mechanism for controlling the injection amount of the majority carriers from the N-type source region by switching the height of the potential barrier across the channel region by the gate voltage and the drain voltage. That is, the switch mechanism in the case of a JFET means a gate electrode and a channel region. In the switch mechanism using the heterojunction, the gate electrode is provided in close proximity to the heterojunction interface via the gate insulating film, and the width of the energy barrier due to the heterojunction is controlled by controlling the potential applied to the gate electrode, thereby allowing the tunnel current. By turning on, the current is switched on and off. In the case of GaN, a channel structure using a two-dimensional electron gas cloud may be used.

In the description of the power MOSFET, the N ⁺ type source region 5 is formed in the P type well region 3. The gate electrode 7 is formed on the gate insulating film 6 formed on the first main surface side so as to span the plurality of discretely arranged P-type well regions 3 (two in FIG. 1). A source electrode 8 made of, for example, a metal is formed so as to be connected to the N ⁺ source region 5. Fig. 1 shows a form in which two basic unit cells face each other, but in reality a large number of cells are connected in parallel. The concentration and thickness of the drain region 1 are set according to the necessary breakdown voltage. Thickness is about 10 micrometers as an example in order to acquire the internal pressure of 1000V class. The N ⁺ type SiC substrate 2 is resistance-connected with the drain electrode 9 on the rear surface.

The characteristic structure in this embodiment is that the hetero semiconductor region 4 which consists of P ⁺ type polysilicon (polycrystalline silicon) in the drain region 1 is formed in columnar shape. The hetero semiconductor region 4 which consists of this P ⁺ type polysilicon is connected with the source electrode 8 which consists of metals, for example. The hetero semiconductor region 4 is made up of a source electrode 8, an N ⁺ source region 5, a P type well region 3 and coincidence.

<Manufacturing method>

Next, although the manufacturing method of such a semiconductor device is detailed, since the detailed manufacturing method of a power MOSFET part is common, description is abbreviate | omitted. Only the manufacturing method of the structure which is the essence of this invention is demonstrated. The N ⁻ type drain region 1 is formed on the N ⁺ type SiC substrate 2 by epitaxial growth. The groove 11 is formed by trench etching from the surface side of the drain region 1. A P ⁺ -type polysilicon layer is deposited to fill the grooves 11. Home a P ⁺ type polysilicon layer is deposited on the surface of the drain region 1, after depositing a P ⁺ type polysilicon layer 11 are removed by etch-back. The introduction of the P ⁺ -type impurity into the polysilicon layer may be simultaneous with the deposition of the polysilicon layer or may be introduced after the deposition. Thus, the manufacturing method of the semiconductor device of this embodiment forms the some groove 11 of columnar shape from the 1st main surface side of the said semiconductor base, and forms the hetero semiconductor region 4 in the said groove 11. And a step of forming the hetero semiconductor region 4 by filling a semiconductor material (herein, P ⁺ type polysilicon). By taking such a structure, a manufacturing process becomes easy and there exists an effect which can suppress a raise of manufacturing cost. In addition, the impurity implantation performed for each epitaxial growth is unnecessary, so that variations in device characteristics can be suppressed, and the yield can be improved, thereby reducing manufacturing costs.

<Action>

Next, the operation of the semiconductor device of the present embodiment will be described. The main current flowing through the element is turned on and off by the action of the portion of the switch mechanism composed of the power MOSFET. In the operation of the original longitudinal power MOSFET, when the device is turned on, the main current is directly below the N ⁺ type SiC substrate 2, the N ⁻ type drain region 1, and the gate insulating film 6 from the drain electrode 9. It flows to the source electrode 8 through the channel region 10 and N ⁺ source region 5 formed in the inside. In addition, when the device is turned off, the heterojunction formed between the source semiconductor 8 and the hetero semiconductor region 4 composed of the P ⁺ type polysilicon and the N ⁻ type drain region 1 is reverse biased. This heterojunction functions as a high breakdown voltage diode. From the experimental results obtained by the applicant's hard work, it can be seen that the P ⁺ type is preferable in order to obtain diode characteristics with a small leakage current at high breakdown voltage.

As described above, the semiconductor device of the present embodiment includes the N ⁺ type SiC substrate 2 and the N ^- type drain region 1, which are semiconductor substrates of the first conductivity type, and the semiconductor substrate (here, the N ^- type drain region 1). A semiconductor device formed on the first main surface side of a semiconductor device having a switch mechanism for switching current on and off, wherein the semiconductor substrate (here N ^- type drain region 1) is selected from the semiconductor substrate (here N ^- type drain region). (1)] and a column-shaped hetero semiconductor region 4 formed of a semiconductor material (herein, P ⁺ type polysilicon) having a different band gap and extending between a first main surface and a second main surface facing the first main surface. A plurality of are formed side by side at intervals.

By taking the structure of this embodiment, the depletion layer can be extended to the drain region 1 in the horizontal direction when the element is turned off. As a result, the entire region of the drain region 1 is depleted, and the peak of the electric field strength near the interface between the P-type well region 3 and the drain region 1 is alleviated to have a uniform electric field distribution in the longitudinal direction. It becomes possible. Since the breakdown voltage can be increased as the peak of the electric field intensity is relaxed, it is possible to cover the decrease in the on-resistance by increasing the concentration of the drain region 1 by that amount. Therefore, both high breakdown voltage and low on-resistance exceeding the material limit (theoretical performance limit) of wide band gap semiconductors, such as SiC, are attained. In addition, in the above-mentioned prior art, the P-shaped columnar structure and the N-shaped columnar structure each extend the depletion layer in the transverse direction in the state where the reverse bias is applied to the element, so that it is necessary to secure the transverse dimension. There was a problem that the overall transverse dimension of the device was large. In the device of the present embodiment, since the depletion layer does not widen in the hetero semiconductor region 4 made of P ⁺ type polysilicon, and the P-type columnar structure can be formed as a narrow region, it is compared with the conventional SJ apparatus. Therefore, it becomes possible to reduce the lateral dimension of the element and to form it. As described above, the P-type columnar structure disposed between the N-type columnar structures (N-type drift regions) in the above-described conventional SJ apparatus needs to introduce impurities for each stage of epitaxial growth. Considering the accuracy of alignment with patterning, the width in the horizontal direction had to be increased. In contrast, in the present embodiment, as shown in Fig. 3 showing the schematic configuration, the hetero semiconductor region 15 made of P ⁺ polysilicon corresponding to the P-type columnar structure is formed as a narrow region at once by trench etching. It is possible. Although the horizontal width of the N-type columnar structure (drain region in FIG. 1) 14 is equivalent to that of the conventional one, it is possible to form the P-type columnar structure very small (narrow), thereby improving the overall cell density. You can. As a result, it is possible to lower the on resistance normalized to the area of the device as a whole. In this way, the area for maintaining the breakdown voltage of the device can be made small, and the on-resistance on which the area is normalized can be made sufficiently small. Further, there is an effect that good breakdown voltage characteristics with less reverse leakage characteristics can be obtained. By the above effects, the semiconductor device of the present embodiment can greatly contribute to the miniaturization and cost reduction of power electronic systems such as motor drive inverters.

In addition, the semiconductor substrate is made of any one of silicon carbide, GaN or diamond (here silicon carbide), the hetero semiconductor region 4 is at least one of monocrystalline silicon (Si, silicon), polycrystalline silicon, or amorphous silicon (here polycrystalline) Silicon). This makes it possible to easily form a high breakdown voltage semiconductor device using a general semiconductor material.

Further, a source electrode 8 formed on the first main surface side of the semiconductor substrate and a drain electrode formed on the second main surface or the first main surface side of the semiconductor substrate (here, the vertical main surface side, and thus resistance-connected) (9), the switch mechanism switches current on and off between the drain electrode (9) and the source electrode (8), while the hetero semiconductor region (4) is electrically connected to the source electrode (8). have. As a result, a power MOSFET which is a low on-resistance switch element can be realized at low cost.

In addition, the hetero semiconductor region 4 has a high concentration of the second conductive type (here, P type) with respect to the semiconductor substrate. As a result, a low on-resistance switch element can be realized at low cost.

<< second embodiment >>

A second embodiment of the present invention will be described with reference to FIG. Fig. 2 is a sectional view showing the structure of an element portion of the semiconductor device of the second embodiment of the present invention.

In this embodiment, the switch mechanism is applied to a U gate (groove gate) type power MOSFET. In Fig. 2, 12 is a gate insulating film, and 13 is a U gate electrode.

Although the first embodiment has been described as having a cross-sectional structure in which two basic cells face each other, in the present embodiment, a wide range of cross-sectional structure is shown so that the hetero semiconductor regions 4 made of a plurality of columnar P ⁺ type polysilicon are arranged. It is. Other configurations, basic operations, operations, effects, and the like are the same as in the first embodiment. That is, similarly to the first embodiment, a structure that can obtain a SJ (RESURF effect) that exceeds the theoretical performance limit of SiC can be easily formed, and a low on-resistance switch having good reverse recovery characteristics can be realized by having a hetero interface.

In addition, embodiment described above is described in order to make understanding of this invention easy, and is not described in order to limit this invention. Therefore, each element disclosed in the above embodiment is intended to include all design changes and equivalents belonging to the technical scope of the present invention. For example, in the first and second embodiments, power M0SFETs have been described as an example of a switch mechanism, but are described, for example, in JFET, MESFET, bipolar transistor, or Japanese Patent Laid-Open No. 2003-318398. Other switch mechanisms in a switch device etc. using a heterojunction may be sufficient. In addition, in the said 1st, 2nd embodiment, although the hetero semiconductor region 4 penetrates to the bottom part of the N ^- type SiC drain region 1, the hetero semiconductor region 4 is N ^- type SiC drain region. Even if it does not reach the bottom of (1), it may reach | attain to the middle of the N ⁺ type SiC board | substrate 2.

According to the present invention, it is possible to provide a semiconductor device capable of realizing a low on-resistance switch element at low cost and a manufacturing method thereof.

Claims (8)

A semiconductor substrate of a first conductivity type, A semiconductor device formed on the first main surface side of the semiconductor substrate and having a switch mechanism for switching current on and off. The semiconductor substrate is formed of a semiconductor material having a band gap different from that of the semiconductor substrate, and the columnar hetero semiconductor regions extending between the first main surface and the second main surface opposite to the first main surface are spaced side by side at intervals. A plurality of semiconductor devices are formed. The method of claim 1, wherein the semiconductor substrate is made of any one of silicon carbide, GaN or diamond, And wherein said hetero semiconductor region is formed of at least one of monocrystalline silicon, polycrystalline silicon, or amorphous silicon. The source electrode of claim 1 or 2, wherein the source electrode is formed on the first main surface side of the semiconductor substrate; It has a drain electrode formed in the 2nd main surface or the 1st main surface side of the said semiconductor base, and resistance-connected, And the switch mechanism switches on and off current between the drain electrode and the source electrode, and the hetero semiconductor region is electrically connected to the source electrode. The semiconductor device according to claim 2, wherein the hetero semiconductor region is of a second conductivity type having a high concentration with respect to the semiconductor substrate. It is a manufacturing method which manufactures the semiconductor device of Claim 1 or 2, The process of forming a some columnar groove from the 1st main surface side of the said semiconductor base material, And a step of forming said hetero semiconductor region by filling said semiconductor material in said grooves. 4. The semiconductor device according to claim 3, wherein said hetero semiconductor region is of a high concentration second conductivity type with respect to said semiconductor substrate. It is a manufacturing method which manufactures the semiconductor device of Claim 3, The process of forming a some columnar groove from the 1st main surface side of the said semiconductor base material, And a step of forming said hetero semiconductor region by filling said semiconductor material in said grooves. The manufacturing method of manufacturing the semiconductor device of Claim 4 or 6, The process of forming a some columnar groove from the 1st main surface side of the said semiconductor base material, And a step of forming said hetero semiconductor region by filling said semiconductor material in said grooves.

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