KR100762093B1 - Vertical light emitting device and package manufacturing method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical light emitting device and a method for manufacturing the package thereof, and more particularly, to a vertical light emitting device and a method for manufacturing the package, which are manufactured by bonding a light emitting device to a submount at the wafer level. This invention comprises the steps of forming a metal buffer layer on a substrate; Growing a plurality of semiconductor layers over the metal buffer layer; Forming a first electrode on the semiconductor layers; Separating the substrate on which the semiconductor layer is grown into unit devices; Bonding the separated unit elements to a submount; Separating the substrate by etching the metal buffer layer; And forming a second electrode on the semiconductor layer from which the substrate is separated.

Submount, light emitting element, GaN, metal buffer layer, substrate.

Description

Vertical light emitting device and its package manufacturing method {Method of manufacturing and packaging LED having vertical structure}

1 to 4 are cross-sectional views showing a first embodiment of the manufacturing method of the vertical light emitting device of the present invention.

1 is a cross-sectional view showing the step of forming a semiconductor layer of the method of manufacturing a vertical light emitting device of the present invention.

2 is a cross-sectional view illustrating a step of forming a first electrode of a method of manufacturing a vertical light emitting device of the present invention.

3 is a cross-sectional view showing a laser scribing step of the method of manufacturing a vertical light emitting device of the present invention.

4 is a cross-sectional view showing a chip of the first embodiment of the method of manufacturing the vertical light emitting device of the present invention.

5 to 8 are cross-sectional views showing a second embodiment of the manufacturing method of the vertical light emitting device of the present invention.

5 is a cross-sectional view showing a mesa etching step of the manufacturing method of the vertical light emitting device of the present invention.

6 is a cross-sectional view illustrating a step of forming a passivation layer and a first electrode in the method of manufacturing a vertical light emitting device of the present invention.

7 is a cross-sectional view showing a step of forming a metal plate of the method of manufacturing a vertical light emitting device of the present invention.

8 is a cross-sectional view showing a chip of a second embodiment of the method of manufacturing a vertical light emitting device of the present invention.

9 and 10 are cross-sectional views showing a third embodiment of the manufacturing method of the vertical light emitting device of the present invention.

9 is a cross-sectional view illustrating a trench etching step of the method of manufacturing a vertical light emitting device of the present invention.

Fig. 10 is a sectional view showing a chip of the third embodiment of the method of manufacturing the vertical light emitting device of the present invention.

11 is a cross-sectional view illustrating a step of bonding a chip to a submount in the method of manufacturing a vertical light emitting device of the present invention.

12 is a schematic diagram showing an example of a submount in the method of manufacturing a vertical light emitting device of the present invention.

13 is a cross-sectional view showing a circuit of a submount in the method of manufacturing a vertical light emitting device of the present invention.

14 is a cross-sectional view showing a state where a chip is attached to a submount in the method of manufacturing a vertical light emitting device of the present invention.

Fig. 15 is a sectional view showing the first embodiment of the submount in the method of manufacturing the vertical light emitting device of the present invention.

16 is a cross-sectional view showing a second embodiment of a submount of the method of manufacturing a vertical light emitting device of the present invention.

Fig. 17 is a cross-sectional view showing the third embodiment of the submount in the method of manufacturing the vertical light emitting device of the present invention.

18 is a perspective view showing an example of a light emitting device package manufactured by the method of manufacturing a vertical light emitting device of the present invention.

<Brief description of the main parts of the drawing>

10: substrate 20: metal buffer layer

30 semiconductor layer 40 first electrode

50: passivation layer 60: submount

70: second electrode 71: wire

80 lens 100 chip

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical light emitting device and a method for manufacturing the package thereof, and more particularly, to a vertical light emitting device and a method for manufacturing the package, which are manufactured by bonding a light emitting device to a submount at the wafer level.

Light Emitting Diodes (LEDs) are well-known semiconductor devices that convert current into light.In 1962, red LEDs using GaAsP compound semiconductors were commercialized. It has been used as a light source for display images of electronic devices.

The wavelength of light emitted by such LEDs depends on the semiconductor material used to make the LEDs. This is because the wavelength of the emitted light depends on the band-gap of the semiconductor material, which represents the energy difference between the valence band electrons and the conduction band electrons.

Gallium Nitride (GaN) semiconductors have received a lot of attention. One reason for this is that GaN can be combined with other elements (indium (In), aluminum (Al), etc.) to produce semiconductor layers that emit green, blue and white light.

In this way, the emission wavelength can be adjusted to match the material's characteristics to specific device characteristics. For example, GaN can be used to create white LEDs that can replace incandescent and blue LEDs that are beneficial for optical recording.

In addition, in the case of the conventional green LED, it was initially implemented as GaP, which was inefficient as an indirect transition type material, and thus practical pure green light emission could not be obtained, but high brightness green LED was realized by InGaN thin film growth.

Because of these and other benefits, the GaN series LED market is growing rapidly. Therefore, since commercial introduction in 1994, GaN-based optoelectronic device technology has rapidly developed.

Since the efficiency of GaN light emitting diodes outperformed the efficiency of incandescent lamps and is now comparable to that of fluorescent lamps, the GaN LED market is expected to continue to grow rapidly.

Despite the rapid development of GaN device technology as described above, the manufacturing of GaN device has a large cost disadvantage. This is related to the difficulty of growing GaN epitaxial layers and subsequently cutting the finished GaN-based devices.

GaN-based devices are typically fabricated on sapphire (Al ₂ O ₃ ) substrates. This is because sapphire wafers are commercially available in sizes suitable for mass production of GaN-based devices, support relatively high quality GaN thin film growth, and have a wide range of temperature processing capabilities.

In addition, sapphire is chemically and thermally stable, has a high melting point to enable high temperature manufacturing processes, high binding energy (122.4 Kcal / mole) and high dielectric constant. Chemically, sapphire is crystalline aluminum oxide (Al ₂ O ₃ ).

On the other hand, since the sapphire is an insulator, the shape of the LED element available when using the used sapphire substrate (or other insulator substrate) is, in fact, limited to a lateral or vertical structure.

In this horizontal structure, the metal contacts used to inject current into the LED are all located on the top surface (or on the same side of the substrate). In the vertical structure, on the other hand, one metal contact is on the top face and the other contact is located on the bottom face after the sapphire (insulation) substrate is removed.

In addition, a flip chip bonding method in which the chip is attached upside down to a submount such as a silicon wafer or a ceramic substrate having excellent thermal conductivity after the manufacture of the LED chip is also widely used.

However, the above-described horizontal structure or flip chip method is a problem in heat dissipation efficiency because the thermal conductivity of the sapphire substrate is about 27 W / mK and the heat resistance is very large. The manufacturing process was complicated and required.

In connection with these problems, the vertical structure of the LED for removing the sapphire substrate has attracted much attention.

In order to solve the above problems of the sapphire substrate in the vertical LED, the sapphire substrate is removed by using a laser lift off (LLO) method to manufacture the device.

In applying the laser lift-off method, the front surface of the sapphire substrate cannot be removed at once because of the size and uniformity of the laser beam. .

At this time, a stress caused by laser is applied to the GaN thin film when the laser is incident. To separate the sapphire substrate and the GaN thin film, a laser beam having a high energy density must be used. Decomposes into nitrogen (N ₂ ).

Since the decomposed nitrogen gas has a great expansion force, the decomposed nitrogen gas has a considerable impact not only on the GaN thin film but also on the supporting layer and each metal layer for device fabrication, which primarily degrades the adhesion and further impairs the electrical properties.

After the LLO process, the GaN thin film may generate ripples that appear to have curvature at the edge portion. In addition, during the LLO process, it is possible to observe a lot of the poor adhesion of these thin films.

In addition, this method causes a problem that the back surface of the GaN layer constituting the LED is damaged at overlapping beams, and cracks may be propagated to other parts of the GaN layer, which may occur at some poor quality areas. Done.

In order to prevent the shape as described above, a semiconductor wafer such as Si, GaAs or the like may be bonded or a method of separating a sapphire substrate after forming a metal support part by plating using a metal such as Cu, Au or Ni may be used. However, this method increases the overall process.

As described above, a process that takes a long time is required to fabricate a device using a GaN thin film constituting the LED layer, and also has many difficulties in this process. In particular, the use of a laser tends to cause damage to the thin film, and there are many process problems such as lowering productivity.

The present invention is to solve the problems described above, to prevent the damage of the thin film generated in the laser lift-off process, to reduce the process step and the process time, the vertical light emission that can be various arrangements and forms of the device An object and a package manufacturing method thereof are provided.

In order to achieve the object of the present invention as described above, the present invention comprises the steps of forming a metal buffer layer on a substrate; Growing a plurality of semiconductor layers over the metal buffer layer; Forming a first electrode on the semiconductor layers; Separating the substrate on which the semiconductor layer is grown into unit devices; Bonding the separated unit elements to a submount; Separating the substrate by etching the metal buffer layer; And forming a second electrode on the semiconductor layer from which the substrate is separated.

The method may further include applying a yellow phosphor to an outer portion of the unit device to form a white light emitting device.

After the step, performing wire bonding between the submount and the second electrode; Forming a filler in the submount; The method may further include bonding a lens to the submount.

The growing of the plurality of semiconductor layers may include forming an n-type semiconductor layer on the substrate; Forming an active layer on the n-type semiconductor layer; The method may include forming a p-type semiconductor layer on the active layer.

The substrate of the submount is made of any one of Si, AlN ceramic, AlO _x , Al ₂ O ₃ , BeO, PCB substrate, the submount is a planar submount, 3D submount, 3D THI (Through Hole Interconnection) Any of the submounts can be used.

Bonding the separated unit element to the submount may be performed by bonding the unit element to the submount using an adhesive, and then thermally pressure bonding or mounting the unit element to the submount, followed by ultrasonic vibration. It is made by bonding by the frictional heat generated by the.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, a method of manufacturing individual semiconductor light emitting device chips will be described.

As shown in FIG. 1, after the metal buffer layer 20 is formed on the sapphire substrate 10, the plurality of semiconductor layers 30 are formed by using a thin film growth method such as hydride vapor phase epitaxy (HVPE). . HVPE method has the advantage that the growth rate is very fast, about 50 ~ 100㎛ per hour, high-purity thin film growth with low impurity concentration during thin film growth.

The growth of the plurality of semiconductor layers 30 is performed by first forming an n-type GaN semiconductor layer on the substrate 10, then forming an active layer, and then forming a p-type GaN semiconductor layer on the active layer.

Subsequently, as shown in FIG. 2, the first electrode 40 is formed on the semiconductor layer 30. The first electrode 40 has a reflective electrode 42 in addition to the ohmic electrode 41. The light emission efficiency may be improved by reflecting light emitted from the active layer of the semiconductor layer 30.

Indium tin oxide (ITO) may be used as the ohmic electrode 41, and a diffusion barrier layer 43 may be further formed on the reflective electrode 42.

The diffusion barrier layer 43 is also referred to as an under bump metalization (UBM) layer. In the case of plating on the reflective electrode 42 or attaching a metal support layer, solder is mainly used, and this solder is melted to form the solder component. It is introduced into the semiconductor layer 30 serves to prevent affecting the light emission characteristics.

Subsequently, a plate (not shown) may be formed of metal such as Cu, Ni, or Au to bond the chip to the submount described later on the diffusion barrier layer 43.

Then, the process of separating the chip made as described above into a unit element is performed. First, as shown in FIG. 3, after the substrate 10 is thinned, scribing is performed using a laser in the unit element division region, and then a mechanical method is applied to the scribed portion. As shown in FIG. 4, the individual chips 100 are separated.

Meanwhile, after the semiconductor layers 30 are grown, individual chips may be manufactured by mesa etching, as shown in FIG. 5.

In this case, the mesa etching is usually performed by etching the semiconductor layer 30 grown on the substrate 10 until the n-type semiconductor layer is exposed in the region that separates the unit elements.

Thereafter, as shown in FIG. 6, the ohmic electrode 41 may be manufactured, and the passivation layer 50 may be formed to protect the surface etched with the ohmic electrode 41. Subsequently, as shown in FIG. 7, the reflective electrode 42 and the diffusion barrier layer 43 may be formed, and the metal plate 44 may be formed using metals such as Cu, Ni, and Au.

Subsequently, the process of thinning the substrate 10, performing laser scribing, and separating the chip is the same as the above process, and thus, the separated chip 100 has a structure as shown in FIG. 8.

In addition, as shown in FIG. 9, a chip may be manufactured by performing trench etching that is etched until the substrate 10 is exposed, as shown in FIG. 9. In the present invention, etching may be performed until the metal buffer layer 20 is exposed.

Subsequent manufacturing methods are the same as those described above, and in this case, the chip 100 has a structure as shown in FIG. 10.

The individual chips 100 manufactured as described above are bonded to the submount 60 produced separately, as shown in FIG. In this case, bonding is performed in a manner that the first electrode 40 is attached to the substrate 61 of the submount 60.

The substrate 61 of the submount 60 may be Si, AlN ceramics, AlO _x , Al ₂ O ₃ , BeO, PCB substrates, all in the case of using a Si substrate by forming a zener diode on the substrate, ESD (electrostatic discharge) characteristics can be improved.

ESD characteristic means that when a static electricity is generated, a momentarily high voltage is applied, and when such a voltage is applied to the device, the characteristics of the device are lost by the electrostatic breakdown phenomenon. This type of ESD often occurs during assembly and handling by humans or equipment. By optimizing a structure that eliminates current condensation inside the device, it is necessary to improve ESD characteristics (enhancing the electrostatic resistance of the device to higher voltages). It is important to improve the characteristics of the device.

Specifically, such static electricity may occur in a process of manufacturing a semiconductor, or may occur in a process of mounting the manufactured semiconductor on a PCB.

Since static electricity does not always occur and is not always a certain amount (voltage, current) even when it occurs, it is necessary to make static electricity with the same voltage and current waveforms for quantitative tests. There are standards such as 61000-4-2, EIAJ, MIL STD.-883D, E (3015), and KN61000-4-2 (Korean version of IEC61000-4-2) is a representative standard.

As a method of bonding the chip 100 to the submount 60, the following method may be used.

First, the unit device chip 100 may be mounted on the submount 60 using an adhesive, and then bonding may be performed by thermally applying pressure.

In addition, after the unit device chip 100 is aligned and mounted (contacted) to the submount 60, bonding may be performed by frictional heat generated by ultrasonic vibration.

In this case, the metal plate 44 of the chip 100 may be formed of Au, the Au ball may be positioned at a desired part on the opposite side of the chip, and bonded to the chip part by U / S bonding. Silver bonding properties are particularly excellent in thermal properties.

FIG. 12 illustrates an example of a 3D through hole interconnection (THI) submount incorporating a zener diode to improve such ESD characteristics.

As shown, this submount 60 is provided with a substrate 61 in contact with the chip, which is in contact with a top side metal substrate 62 in contact with the first electrode 40 of the chip, and subsequently. The back side metal substrate 63 is in contact with the second electrode of the chip, and the reflecting plate 65 reflects light emitted from the chip.

Zener diodes 64 are connected to the two substrates 62 and 63 in opposite polarities to form a circuit as shown in FIG. 13 when the chip 100 is attached.

That is, when the zener diode 64 is connected to the substrates 62 and 63 connected to the chip 100 in opposite polarity in parallel with the chip, and the chip 100 is subjected to an excessive voltage, the zener diode 64 may be Beyond the breakdown voltage, the current flows through the zener diode 64.

A reflective plate 65 may be separately provided on the substrate 61 side of the submount 60 to reflect light generated from the chip 100.

In FIG. 14, the chip 100 is attached to the submount 60 as described above. The submounts 60 are connected to each other to form a plane, and the chip 100 is attached to the submounts 60, and after the manufacturing of the light emitting device is completed, the submounts 60 are used separately.

As described above, after bonding the chip 100 to the submount 60, the substrate 10 is separated by etching the metal buffer layer 20 of the chip 100.

As shown in FIG. 14, since the individual chips 100 are separated and etched in a state in which they are attached to the submount 60, etching is performed in the state before the entire chips 100 are separated. The time required is significantly reduced, and the quality is excellent.

In this manner, after the substrate 10 is separated, as shown in FIGS. 15 to 17, the second electrode 70 is formed on the surface from which the substrate 10 is separated, and the substrate of the submount 60 ( 61 and wire 71 bonding.

In this case, the second electrode 70 may be an n-type electrode.

The submount 60 may be a planar submount as shown in FIG. 15, a 3D submount as shown in FIG. 16, or a 3D through hole interconnection (THI) submount as shown in FIG. 17.

In order to increase the light emitting efficiency of the chip 100, a structure having various shapes may be formed on a surface from which light is emitted.

The pattern can be formed in various ways, one of which uses a patterned sapphire substrate (PSS). This method does not use a flat substrate for the first thin film growth, but a device with a patterned structure on a sapphire substrate.

As described above, when the device is manufactured and the sapphire substrate 10 is separated later, the concave-convex shape that can naturally emit light well at the interface can be formed.

In addition, fine patterns may be fabricated on the light emitting surface by using PBC (photonic crystal), nanoparticle (nano particles) adhesion, nano etching (NIL).

Such fine patterns can be formed using MOCVD.

On the other hand, as described above, after the device is manufactured, a white light emitting device can be produced by applying a yellow phosphor to the outside of the chip 100.

That is, the GaN-based light emitting device emits blue light, which is partially absorbed and emitted by the yellow phosphor, thereby emitting white light.

The application of the yellow phosphor may be a variety of methods, such as dispensing, screen printing, molding of the epoxy mixed with the yellow phosphor.

Subsequently, a filler is formed in the submount 60, and as shown in FIG. 18, the lens 80 is bonded to the upper side of the chip 100 of the submount 60, and the submount 60 is an individual element. By separating, packaging of a light emitting element is achieved.

The above embodiment is an example for explaining the technical idea of the present invention in detail, and the present invention is not limited to the above embodiment, various modifications are possible, and various embodiments of the technical idea are all protected by the present invention. It belongs to the scope.

The present invention as described above, in the manufacture of a vertical light emitting device, by separating the substrate by a chemical etching method, it is possible to prevent damage to the thin film generated in the laser lift-off process, and to shorten the process step and the process time In addition, it is possible to improve process convenience and mass production, to enable various arrangements and shapes of devices, and to improve ESD characteristics of devices.

Claims (32)

Forming a metal buffer layer on the substrate; Growing a plurality of semiconductor layers over the metal buffer layer; Forming a first electrode on the semiconductor layers; Separating the substrate on which the semiconductor layer is grown into unit devices; Bonding the first electrode side of the separated unit element to a submount; Separating the substrate by etching the metal buffer layer; And forming a second electrode on the semiconductor layer from which the substrate is separated. The method of claim 1, wherein the growing of the plurality of semiconductor layers comprises: Forming an n-type semiconductor layer on the substrate; Forming an active layer on the n-type semiconductor layer; And forming a p-type semiconductor layer over the active layer. The method of claim 1, wherein the forming of the first electrode comprises: Forming an ohmic electrode; And forming a reflective electrode on the ohmic electrode. The method of claim 3, further comprising forming a diffusion barrier layer on the reflective electrode. The method of claim 3, further comprising forming a metal plate on the reflective electrode. The method of claim 1, wherein the separating of the substrate into a unit device comprises: Thinning the substrate; Irradiating a laser on the substrate side and scribing; And separating the scribed portion. The method of claim 1, wherein after growing the plurality of semiconductor layers on the metal buffer layer, And etching a region in which the semiconductor device grown on the substrate to separate the unit devices until a portion of the grown semiconductor layer is exposed. The method of claim 1, wherein after growing the plurality of semiconductor layers on the metal buffer layer, And etching the region separating the semiconductor device grown on the substrate until the substrate is exposed. The method of claim 7 or 8, wherein a passivation layer is formed on the etched surface. 10. The method of claim 9, wherein the passivation layer is formed to the side of the first electrode. delete The method of claim 1, wherein the submount, Method of manufacturing a vertical light emitting device, characterized in that made of any one of Si, AlN ceramics, AlO _x , Al ₂ O ₃ , BeO, PCB substrate. The method of claim 12, wherein a Zener diode is formed on the Si submount substrate. The method of claim 1, wherein the submount uses any one of a planar submount, a 3D submount, and a 3D through hole interconnection (THI) submount. The method of claim 1, wherein bonding the separated unit elements to a submount includes: A method of manufacturing a vertical light-emitting device, characterized in that the unit device is mounted on a submount using an adhesive, and then bonded under thermal pressure. The method of claim 1, wherein bonding the separated unit elements to a submount includes: And mounting the unit device on a submount, and bonding the unit device by frictional heat generated by ultrasonic vibrations. The method of claim 1, wherein a specific pattern is formed on a surface on which light emitted by the plurality of semiconductor layers is emitted. The method of claim 17, wherein the formation of the specific pattern, And forming the plurality of semiconductor layers on the substrate on which the specific pattern is formed. 18. The method of claim 17, wherein the specific pattern is formed on the surface from which the light is emitted by any one of photonic crystal formation, nanoparticle adhesion, and nano etching. The method of claim 1, further comprising applying a yellow phosphor to an outer portion of the unit device. In the method for packaging a vertical light emitting device manufactured by the method of claim 1, Performing wire bonding between the submount and the second electrode; Forming a filler in the submount; The method of manufacturing a package of a vertical light-emitting device further comprising the step of bonding a lens to the submount. A submount having at least one pair of electrodes formed on the light emitting device chip mounting portion; A plurality of semiconductor layers coupled to the submount, a metal plate electrically connected to one side of the electrode, a first electrode disposed on the metal plate, and a light extraction pattern formed on the first electrode; And a light emitting device chip on the semiconductor layer and including a second electrode electrically connected to the other side of the electrode; And a Zener diode formed in the submount and connected to the electrode. The method of claim 22, wherein the first electrode, The vertical light emitting device package, characterized in that the ohmic electrode located on the semiconductor layer. The method of claim 23, wherein the first electrode, A reflection electrode positioned on the ohmic electrode; And a diffusion barrier layer disposed on the reflective electrode. 23. The vertical light emitting device package of claim 22, wherein the metal plate is formed of any one of Cu, Ni, and Au or an alloy thereof. 23. The vertical light emitting device package of claim 22, wherein the support layer covers the semiconductor layer and the first electrode. 23. The vertical light emitting device package of claim 22, wherein a passivation layer is formed on at least one side of the semiconductor layer and the first electrode. The method of claim 22, wherein the submount, A vertical light emitting device package comprising any one of Si, AlN ceramic, AlO _x , Al ₂ O ₃ , BeO, and PCB substrate. 23. The vertical light emitting device package of claim 22, wherein the submount uses any one of a planar submount, a 3D submount, and a 3D through hole interconnection (THI) submount. The method of claim 22, A filler formed on the submount; Vertical light emitting device package further comprises a lens coupled to the filler. The vertical light emitting device package of claim 22, wherein the light extraction pattern is a photonic crystal or a plurality of nanoparticles. 23. The vertical light emitting device package of claim 22, further comprising a phosphor layer outside the light emitting device chip.

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