KR100761082B1 - Thin film transistor and its manufacturing method - Google Patents

Abstract

According to the present invention, when the amorphous silicon layer is crystallized into a polycrystalline silicon layer by SGS crystallization, an upper capping layer and a lower capping layer are formed on the upper and lower portions of the amorphous silicon layer, respectively, and the upper or lower capping layer of the upper capping layer is formed. The present invention relates to a thin film transistor and a method for manufacturing the same, which minimize the concentration of the metal catalyst remaining in the polycrystalline silicon layer by forming a metal catalyst layer at the bottom and then diffusing the metal catalyst contributing to the crystallization by the crystallization to the lower capping layer or the upper capping layer.

SGS crystallization method, metal catalyst

Description

Thin film transistor and its manufacturing method {Thin film transistor and method for fabricating the same}

1A to 1E are cross-sectional views illustrating a method of manufacturing a thin film transistor including a polycrystalline silicon layer crystallized by a crystallization method according to an embodiment of the present invention.

2A to 2E are cross-sectional views illustrating a method of manufacturing a thin film transistor including a polycrystalline silicon layer crystallized by a crystallization method according to another embodiment of the present invention.

 <Description of the symbols for the main parts of the drawings>

120: lower capping layer 130: amorphous silicon layer

135 polycrystalline silicon layer 140 upper capping layer

150: metal catalyst layer

The present invention relates to a thin film transistor and a method for manufacturing the same, and more particularly, when the amorphous silicon layer is crystallized into a polycrystalline silicon layer by the SGS crystallization method, a thin film transistor having a minimum amount of metal catalyst in the polycrystalline silicon layer and a method of manufacturing the same. It is about.

In general, the polycrystalline silicon layer is widely used as a semiconductor layer for thin film transistors because of its advantages in that it can be applied to high field effect mobility, high speed operation circuits, and CMOS circuits. Thin film transistors using such polycrystalline silicon layers are mainly used in active elements of active matrix liquid crystal display (AMLCD) and switching elements and driving elements of organic electroluminescent element (OLED).

In this case, the polycrystalline silicon layer used for the thin film transistor may be fabricated using a direct deposition method, a technique using high temperature heat treatment, or a laser heat treatment method. Although the laser heat treatment method is capable of low temperature processing and can implement high field effect mobility, a lot of alternative technologies have been studied because expensive laser equipment is required.

Currently, the method of crystallizing amorphous silicon using a metal has been studied a lot because it has the advantage that can be crystallized in a short time at a lower temperature than the solid phase crystallization (Solid Phase Crystallization). Crystallization using metal is divided into Metal Induced Crystallization (MIC) and Metal Induced Lateral Crystallization (MILC). However, the method using the metal catalyst has a problem in that the device characteristics of the thin film transistor are deteriorated due to contamination by the metal catalyst.

In order to solve the contamination problem of the metal catalyst as described above, a method of manufacturing a polycrystalline silicon layer by a crystallization method using a cover layer (published patent 2003-0060403) has been developed. The method includes depositing an amorphous silicon layer and a capping layer on a substrate, forming a metal catalyst layer thereon, and then diffusing the substrate with the amorphous silicon layer through the capping layer by heat treatment using a heat treatment or a laser. After forming a seed, it is a method of obtaining a polycrystalline silicon layer using this. The method has an advantage of preventing metal contamination more than necessary because the metal catalyst is diffused through the cover layer, but there is still a problem that a large amount of the metal catalyst layer is present inside the polycrystalline silicon layer.

Accordingly, the present invention is to solve the above-mentioned disadvantages and problems of the prior art, to form an upper capping layer and a lower capping layer on the upper and lower portions of the amorphous silicon layer, respectively, the upper or lower cap of the upper capping layer After forming the metal catalyst layer on the lower portion of the ping layer, and the crystallization of the metal catalyst contributed to the crystallization diffused into the lower capping layer or the upper capping layer to provide a thin film transistor and a method for manufacturing the same to minimize the concentration of the metal catalyst remaining in the polycrystalline silicon layer. There is an object of the present invention.

The object of the present invention is a substrate; One or more capping layers on the substrate and having a metal catalyst; A semiconductor layer formed on the capping layer; And a gate insulating film, a gate electrode, an interlayer insulating film, and a source / drain electrode formed on the semiconductor layer.

In addition, the above object of the present invention comprises the steps of preparing a substrate; Forming a lower capping layer on the substrate; Forming an amorphous silicon layer on the lower capping layer; Forming an upper capping layer on the amorphous silicon layer; Forming a metal catalyst layer on the upper capping layer; Heat treating the substrate to crystallize the amorphous silicon layer into a polycrystalline silicon layer; Removing the metal catalyst layer and the upper capping layer; And patterning the polycrystalline silicon layer to form a semiconductor layer.

In addition, the above object of the present invention comprises the steps of preparing a substrate; Forming a metal catalyst layer on the substrate; Forming a lower capping layer on the metal catalyst layer; Forming an amorphous silicon layer on the lower capping layer; Forming an upper capping layer on the amorphous silicon layer; Heat treating the substrate to crystallize the amorphous silicon layer into a polycrystalline silicon layer; Removing the upper capping layer; And patterning the polycrystalline silicon layer to form a semiconductor layer.

Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention. In the drawings, the length, thickness, etc. of layers and regions may be exaggerated for convenience. Like numbers refer to like elements throughout.

<Example 1>

1A to 1E are cross-sectional views illustrating a method of manufacturing a thin film transistor including a polycrystalline silicon layer crystallized by a crystallization method according to an embodiment of the present invention.

Referring to FIG. 1A, a buffer layer 110 is formed of a silicon oxide film or a silicon nitride film by physical vapor deposition or chemical vapor deposition on a transparent insulating substrate 100 such as glass or plastic. Form.

At this time, the buffer layer 110 serves to prevent the diffusion of moisture or impurities generated in the lower substrate, or to control the rate of heat transfer during crystallization, so that the amorphous silicon layer can be crystallized well.

Subsequently, a lower capping layer 120 is formed on the substrate by physical vapor deposition or chemical vapor deposition.

In this case, the lower capping layer 120 is preferably formed of a silicon nitride film, and the silicon nitride film preferably has a refractive index of 1.9 or less, which means that the lower capping layer 120 has a refractive index of 1.9 or less. This is because diffusion of the metal catalyst is easy. In addition, the lower capping layer 120 is formed to a thickness of 100 to 5000Å.

Subsequently, an amorphous silicon layer 130 is formed on the lower capping layer 120.

Subsequently, an upper capping layer 140 is formed on the amorphous silicon layer 130 by using physical vapor deposition or chemical vapor deposition.

In this case, the upper capping layer 140 is formed of a silicon nitride film having a refractive index of 1.9 or less, similarly to the lower capping layer 120. In addition, the upper capping layer 140 is formed to a thickness of 100 to 5000Å.

In this case, although the lower capping layer 120 and the upper capping layer 140 are shown as being formed in a single layer, respectively, if necessary, may be formed of two or more layers, respectively.

Subsequently, a metal catalyst layer 150 is formed on the upper capping layer 140.

At this time, the metal catalyst layer 150 is formed to include any one or more of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Cr, Ru, Rh, Cd and Pt, Preferably, the metal catalyst layer 150 including Ni is preferably formed. This is because the diffusion rate is high in the upper capping layer 140, the amorphous silicon layer 130, and the lower capping layer 120, and the crystallization characteristics are excellent when the amorphous silicon layer 130 is crystallized.

In addition, the metal catalyst layer 150 is preferably formed in a very small amount at a concentration of about 1 × 10 ¹³ atoms / cm ² or less, in order to minimize the amount of metal catalyst to be deposited to minimize the residual amount of the metal catalyst to be.

Referring to FIG. 1B, the substrate is heat-treated with a heating device such as a furnace, rapid thermal annealing (RTA), or laser.

The metal catalyst of the metal catalyst layer 150 is diffused by the heat treatment process. At this time, the heat treatment process is carried out for several seconds or several hours at a temperature of 750 ℃ or less.

In this case, the predetermined metal catalyst of the metal catalyst layer 150 has a short diffusion distance and diffuses to the upper capping layer 140 to become the first metal catalyst 151, and the predetermined metal catalyst of the metal catalyst layer 150 is an amorphous silicon layer. It diffuses to 130 to become the second metal catalyst 152. At this time, predetermined metal catalysts of the second metal catalyst 152 form a seed 153 which is a nucleus that crystallizes the amorphous silicon layer 130 into a polycrystalline silicon layer. In this case, the seed 153 is formed while the second metal catalyst 152 diffused to the amorphous silicon layer 130 breaks through a certain critical point, and generally various second metal catalysts diffused to the amorphous silicon layer 130. 152 is a seed 153 when more than a certain number is collected.

In addition, the predetermined metal catalyst of the metal catalyst layer 150 may be diffused to the lower capping layer 154 to become the third metal catalyst 154. In this case, preferably, the diffusion of the metal catalyst of the metal catalyst layer 150 may be performed only up to the amorphous silicon layer 130. This is because it is not necessary to increase the processing time (heat treatment time) unnecessarily to increase the probability of damaging the substrate.

At this time, the concentration of the metal catalyst in each layer is higher in the order of the lower capping layer 120, the amorphous silicon layer 130 and the upper capping layer 140. This refers to a concentration at any one time, and is a state at which a seed 153 is formed in the amorphous silicon layer 130 and immediately before crystallization is completed when the amorphous silicon layer 130 starts to crystallize. .

Referring to FIG. 1C, if the heat treatment process described with reference to FIG. 1B is continued, a metal catalyst is formed by diffusion into the amorphous silicon layer 130 from the metal catalyst layer 150 as shown in FIG. 1C. Using the seed 153 as a nucleus, the amorphous silicon layer 130 is crystallized into the polycrystalline silicon layer 135.

In this case, the metal catalyst layer 150 and the upper capping layer 140 is shown to be crystallized in a state that is not removed, if necessary, only the metal catalyst layer 150, or the metal catalyst layer 150 and the upper capping layer. After removing all of the 140, a heat treatment process may be performed to perform a crystallization process. (At this time, the heat treatment for diffusing the metal catalyst described with reference to FIG. 1B is a first heat treatment process and the crystallization described with reference to FIG. 1C. Heat treatment may be divided into a second heat treatment process.)

In this case, some of the second metal catalysts 152 in the polycrystalline silicon layer are diffused into the lower capping layer 120 by the heat treatment for crystallization or additional heat treatment after the crystallization is completed, thereby present in the lower gapping layer 120. The fourth metal catalyst 155 may be.

At this time, the concentration of the metal catalyst in each layer is similar to the concentration of the lower capping layer 120 and the polycrystalline silicon layer 135, the concentration of the upper capping layer 140 is the lower capping layer 120 and the polycrystalline silicon layer Higher than the concentration of 135. This is due to the fourth metal catalyst 155 diffused from the polycrystalline silicon layer 135 to the lower capping layer 120. That is, the fourth metal catalyst 155 continuously diffuses into the lower capping layer 120, and the concentration of the polycrystalline silicon layer 135 and the lower capping layer 120 is about to be similar.

If the lower capping layer 120 does not exist or the other layer does not diffuse the metal catalyst, the polycrystalline silicon layer 135 diffuses from the upper capping layer 140 so that the second metal catalyst 152 is formed. The concentration will continue to increase.

Although not shown in FIG. 1C, after the seed 153 is formed, the metal catalyst layer 150 and the upper capping layer 140 are removed, and the heat treatment for crystallization is continued. The concentration of the second metal catalyst 152 of 135 will be further lowered. This is because the second metal catalyst 152 diffuses into the lower capping layer 120 and only changes to the fourth metal catalyst 155, and there is no second metal catalyst 152 supplied from the upper capping layer 140. Because.

In this case, as described above, the metal catalyst of the metal catalyst layer diffuses through the capping layer to the amorphous silicon layer by laminating with an amorphous silicon layer / capping layer / metal catalyst layer and heat treatment, and then forms a seed. Crystallization of the amorphous silicon layer from the polycrystalline silicon layer is referred to as a super grain silicon (SGS) crystallization method.

Referring to FIG. 1D, after the crystallization of the polycrystalline silicon layer 135 is completed, the metal catalyst layer 150 and the upper capping layer 140 are removed.

At this time, as shown in the figure, the second metal catalyst 152 and the seed 153 remain in the polycrystalline silicon layer 135, and the third metal catalyst 154 and the fourth gold in the lower capping layer 120. The fast catalyst 155 remains.

Accordingly, the metal catalyst remaining in the polycrystalline silicon layer 135 is at least lower than the lower capping layer 120 compared to the concentration of the residual metal catalyst of the polycrystalline silicon layer which has undergone the same crystallization process without the lower capping layer 120 being formed. The concentration will be reduced by the fourth metal catalyst 155 remaining in the c).

If the heat treatment process in FIG. 1B is appropriately adjusted, the metal catalyst diffuses only to the amorphous silicon layer 130 so that the third metal catalyst is not formed to form the first metal catalyst 151 and the second metal catalyst. If only the 152 and the seed 153 are formed, and the metal catalyst layer 150 and the upper capping layer 140 are removed, the amorphous silicon layer 130 is crystallized with the polycrystalline silicon layer 135. Among the second metal catalysts 152 in the layer 130, the concentration of the fourth metal catalyst 155 diffused to the lower capping layer 120 is reduced to obtain a polycrystalline silicon layer in which a very small amount of metal catalyst remains. will be.

Referring to FIG. 1E, the polycrystalline silicon layer 135 is patterned to form a semiconductor layer 200, and a gate insulating film (eg, one of a silicon oxide film, a silicon nitride film, and a multilayer thereof) is formed on the semiconductor layer 200. 210).

Subsequently, a gate electrode 220 is formed on the gate insulating film 210, an interlayer insulating film 230 is formed on the gate electrode 220, and a predetermined region of the interlayer insulating film 230 is etched to form the semiconductor. After forming a contact hole exposing a predetermined region of the layer 200, a source / drain electrode 240 contacting the semiconductor layer 200 is formed through the contact hole to complete the thin film transistor.

Therefore, in the present exemplary embodiment, a thin film transistor having excellent electrical characteristics may be provided because the concentration of the metal catalyst remaining in the semiconductor layer is smaller than that of the conventional art.

<Example 2>

2A to 2E are cross-sectional views illustrating a method of manufacturing a thin film transistor including a polycrystalline silicon layer crystallized by a crystallization method according to another embodiment of the present invention.

Referring to FIG. 2A, a buffer layer 110 is formed of a silicon oxide film or a silicon nitride film by physical vapor deposition or chemical vapor deposition on a transparent insulating substrate 100 such as glass or plastic.

At this time, the buffer layer 110 serves to prevent the diffusion of moisture or impurities generated in the lower substrate, or to control the rate of heat transfer during crystallization, so that the amorphous silicon layer can be crystallized well.

Subsequently, a metal catalyst layer 150 is formed on the buffer layer 110.

At this time, the metal catalyst layer 150 is formed to include any one or more of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Cr, Ru, Rh, Cd and Pt, Preferably, the metal catalyst layer 150 including Ni is preferably formed. This is because the diffusion rate is fast in the upper capping layer, the amorphous silicon layer and the lower capping layer to be formed later, and when the amorphous silicon layer is crystallized, the crystallization characteristics are excellent.

In addition, the metal catalyst layer 150 may be formed in a very small amount at a concentration of about 1 × 10 ¹³ atoms / cm ² or less. to be.

Subsequently, the lower capping layer 120 is formed on the metal catalyst layer 150 by physical vapor deposition or chemical vapor deposition.

In this case, the lower capping layer 120 is preferably formed of a silicon nitride film, and the silicon nitride film preferably has a refractive index of 1.9 or less, which is when the lower capping layer 120 is a silicon nitride film having a refractive index of 1.9 or less. This is because it is easy to spread. In addition, the lower capping layer 120 is formed to a thickness of 100 to 5000Å.

Subsequently, an amorphous silicon layer 130 is formed on the lower capping layer 120.

Subsequently, the upper capping layer 140 is formed on the amorphous silicon layer 130 by using physical vapor deposition or chemical vapor deposition.

In this case, the upper capping layer 140 is formed of a silicon nitride film having a refractive index of 1.9 or less, similarly to the lower capping layer 120. In addition, the upper capping layer 140 is formed to a thickness of 100 to 5000Å.

In this case, although the lower capping layer 120 and the upper capping layer 140 are shown as being formed in a single layer, respectively, if necessary, may be formed of two or more layers, respectively.

Referring to Figure 2b, the substrate is heat-treated with a heating device such as a furnace, RTA or laser.

The metal catalyst of the metal catalyst layer 150 is diffused by the heat treatment process. At this time, the heat treatment process is carried out for several seconds or several hours at a temperature of 750 ℃ or less.

At this time, the predetermined metal catalyst of the metal catalyst layer 150 has a short diffusion distance and diffuses to the lower capping layer 120 to become the sixth metal catalyst 251, and the predetermined metal catalyst of the metal catalyst layer 150 is an amorphous silicon layer. It diffuses to 130 to become the seventh metal catalyst 252. At this time, predetermined metal catalysts of the seventh metal catalyst 252 form a seed 253 which is a nucleus that crystallizes the amorphous silicon layer 130 into a polycrystalline silicon layer. In this case, the seed 253 is formed while the seventh metal catalyst 252 diffused to the amorphous silicon layer 130 breaks through a certain critical point. In general, the seventh metal catalyst diffused to the amorphous silicon layer 130 is provided. 252 is a seed 253 when a certain number or more are collected.

In addition, the predetermined metal catalyst of the metal catalyst layer 150 may be diffused to the lower capping layer 154 to become an eighth metal catalyst 254. In this case, preferably, the diffusion of the metal catalyst of the metal catalyst layer 150 may be performed only up to the amorphous silicon layer 130. This is because it is not necessary to increase the processing time (heat treatment time) unnecessarily to increase the probability of damaging the substrate.

In this case, the concentration of the metal catalyst in each layer is high in the order of the upper capping layer 140, the amorphous silicon layer 130 and the upper capping layer 120. (This is the lamination order in the reverse order to the first embodiment) The instantaneous concentration refers to a state in which the seed 253 is formed in the amorphous silicon layer 130 and the crystallization is completed at the time when the amorphous silicon layer 130 starts to crystallize.

Referring to FIG. 2C, if the heat treatment process described with reference to FIG. 2B is continuously performed, as shown in FIG. 2C, the metal catalyst is formed by diffusion into the amorphous silicon layer 130 from the metal catalyst layer 150. The amorphous silicon layer 130 is crystallized into the polycrystalline silicon layer 135 using the seed 253 as a nucleus.

In this embodiment, unlike the <Example 1>, the upper capping layer 140 or the metal catalyst layer 150 should not be removed. (At this time, a heat treatment for diffusing the metal catalyst described with reference to FIG. 2B is performed. It is a first heat treatment process, and the crystallization heat treatment described with reference to FIG. 2C may be divided into a second heat treatment process.)

At this time, some of the seventh metal catalysts 252 in the polycrystalline silicon layer are diffused into the upper capping layer 140 by the additional heat treatment during or after the heat treatment for crystallization is completed, the upper gapping layer 140. It may be the eighth metal catalyst 255 present in the.

At this time, the concentration of the metal catalyst in each layer is similar to the concentration of the upper capping layer 140 and the polycrystalline silicon layer 135, the concentration of the lower capping layer 120 is the upper capping layer 140 and the polycrystalline silicon layer Higher than the concentration of 135. This is due to the eighth metal catalyst 255 diffusing from the polycrystalline silicon layer 135 to the upper capping layer 140. That is, the eighth metal catalyst 255 continuously diffuses into the upper capping layer 140, and thus the concentration of the polycrystalline silicon layer 135 and the upper capping layer 140 is about to be similar.

If the upper capping layer 140 does not exist or the other layer does not diffuse the metal catalyst, the polycrystalline silicon layer 135 diffuses from the lower capping layer 120 to form a seventh metal catalyst 252. The concentration will continue to increase.

Referring to FIG. 2D, after the crystallization of the polycrystalline silicon layer 135 is completed, the upper capping layer 140 is removed.

In this case, as shown in FIG. 7, the seventh metal catalyst 152 and the seed 153 remain in the polycrystalline silicon layer 135, and the fourth metal catalyst 251 remains in the lower capping layer 120. .

Therefore, the metal catalyst remaining in the polycrystalline silicon layer 135 is at least the upper capping layer 140 compared to the concentration of the residual metal catalyst of the polycrystalline silicon layer which has undergone the same crystallization process without the upper capping layer 140 being formed. The concentration will be reduced by the ninth metal catalyst 255 which is diffused into ().

Referring to FIG. 2E, the polycrystalline silicon layer 135 is patterned to form the semiconductor layer 200, and a gate insulating film (eg, one of a silicon oxide film, a silicon nitride film, and a multilayer thereof) is formed on the semiconductor layer 200. 210).

Subsequently, a gate electrode 220 is formed on the gate insulating film 210, an interlayer insulating film 230 is formed on the gate electrode 220, and a predetermined region of the interlayer insulating film 230 is etched to form the semiconductor. After forming a contact hole exposing a predetermined region of the layer 200, a source / drain electrode 240 contacting the semiconductor layer 200 is formed through the contact hole to complete a thin film transistor.

Therefore, in the present exemplary embodiment, a thin film transistor having excellent electrical characteristics may be provided because the concentration of the metal catalyst remaining in the semiconductor layer is smaller than that of the conventional art.

The present invention has been shown and described with reference to the preferred embodiments as described above, but is not limited to the above embodiments and those skilled in the art without departing from the spirit of the present invention. Various changes and modifications will be possible.

Therefore, the thin film transistor of the present invention and its manufacturing method have an effect of providing a thin film transistor having excellent electrical characteristics since the concentration of the metal catalyst remaining in the semiconductor layer is small.

Claims (12)

Board; A buffer layer on the substrate; One or more capping layers disposed on the buffer layer and having a metal catalyst; A semiconductor layer formed on the capping layer; And A thin film transistor comprising: a gate insulating film, a gate electrode, an interlayer insulating film, and a source / drain electrode formed on the semiconductor layer. delete delete The method of claim 1, The semiconductor layer is a thin film transistor, characterized in that the polycrystalline silicon layer crystallized by the SGS crystallization method. Board; A metal catalyst layer on the substrate; One or more capping layers positioned on the metal catalyst layer and having a metal catalyst; A semiconductor layer formed on the capping layer; And A thin film transistor comprising: a gate insulating film, a gate electrode, an interlayer insulating film, and a source / drain electrode formed on the semiconductor layer. The method of claim 1, The capping layer includes a silicon nitride film and has a refractive index of 1.9 or less. Preparing a substrate; Forming a lower capping layer on the substrate; Forming an amorphous silicon layer on the lower capping layer; Forming an upper capping layer on the amorphous silicon layer; Forming a metal catalyst layer on the upper capping layer; Heat treating the substrate to crystallize the amorphous silicon layer into a polycrystalline silicon layer; Removing the metal catalyst layer and the upper capping layer; And Patterning the polycrystalline silicon layer to form a semiconductor layer Thin film transistor manufacturing method comprising a. Preparing a substrate; Forming a metal catalyst layer on the substrate; Forming a lower capping layer on the metal catalyst layer; Forming an amorphous silicon layer on the lower capping layer; Forming an upper capping layer on the amorphous silicon layer; Heat treating the substrate to crystallize the amorphous silicon layer into a polycrystalline silicon layer; Removing the upper capping layer; And Patterning the polycrystalline silicon layer to form a semiconductor layer Thin film transistor manufacturing method comprising a. The method according to claim 7 or 8, After forming the semiconductor layer, Forming a gate insulating film on the substrate; Forming a gate electrode on the gate insulating film; Forming an interlayer insulating film on the gate electrode; And And forming a source / drain electrode in contact with the predetermined region of the semiconductor layer. The method according to claim 7 or 8, The metal catalyst layer is Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Cr, Ru, Rh, Cd and Pt manufacturing a thin film transistor, characterized in that it comprises any one Way. The method according to claim 7 or 8, The metal catalyst layer is a thin film transistor manufacturing method, characterized in that the concentration of the metal catalyst is 10 ¹³ atoms / cm ² or less. The method according to claim 7 or 8, The upper capping layer or the lower capping layer includes a silicon nitride film, and the refractive index is 1.9 or less thin film transistor manufacturing method characterized in that.

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