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KR100756772B1 - Method of manufacturing a transistor - Google Patents

Method of manufacturing a transistor Download PDF

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KR100756772B1
KR100756772B1 KR1020010080581A KR20010080581A KR100756772B1 KR 100756772 B1 KR100756772 B1 KR 100756772B1 KR 1020010080581 A KR1020010080581 A KR 1020010080581A KR 20010080581 A KR20010080581 A KR 20010080581A KR 100756772 B1 KR100756772 B1 KR 100756772B1
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tungsten
silicon layer
gate electrode
forming
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KR20030050182A (en
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이석규
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/671—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor having lateral variation in doping or structure

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 트랜지스터의 제조 방법에 관한 것으로, 특히 다결정 실리콘층/텅스텐(W)층의 금속 게이트 전극 형성 공정 시 상기 텅스텐층을 패터닝(Patterning)하고 확산 방지막을 형성하기 위해 암모니아(NH3) 가스를 사용한 어닐(Anneal) 공정을 진행한 후 상기 다결정 실리콘층을 패터닝하여 게이트 전극을 형성하므로, 상기 텅스텐층 측벽에도 확산 방지막을 형성하기 때문에 종래 기술에서 텅스텐층 측벽을 노출시킨 상태에서 후속 공정인 선택 산화 공정을 진행하여 발생된 텅스텐의 아웃 가싱(Out gassing) 현상을 방지하여 소자의 특성, 수율 및 신뢰성을 향상시키는 특징이 있다.More particularly, the present invention relates to a method of manufacturing a transistor, and more particularly, to a method of patterning a tungsten layer and forming an NH 3 gas in a process of forming a diffusion barrier film in a process of forming a metal gate electrode of a polycrystalline silicon layer / tungsten (W) Since the polysilicon layer is patterned to form a gate electrode, a diffusion barrier layer is formed on the sidewalls of the tungsten layer. Therefore, in the prior art, the tungsten layer sidewalls are exposed, The out gassing phenomenon of the tungsten generated by the process is prevented, thereby improving the characteristics, yield and reliability of the device.

Description

트랜지스터의 제조 방법{Method for manufacturing a transistor}[0001] The present invention relates to a method for manufacturing a transistor,

도 1a 내지 도 1c는 종래 기술에 따른 트랜지스터의 제조 방법을 도시한 단면도.1A to 1C are cross-sectional views illustrating a method of manufacturing a transistor according to the related art.

도 2a 내지 도 2d는 본 발명의 실시 예에 따른 트랜지스터의 제조 방법을 도시한 단면도.FIGS. 2A to 2D are cross-sectional views illustrating a method of manufacturing a transistor according to an embodiment of the present invention; FIGS.

< 도면의 주요부분에 대한 부호의 설명 >Description of the Related Art

11, 31 : 반도체 기판 13, 33 : 제 1 산화막11, 31: semiconductor substrate 13, 33: first oxide film

15, 35 : 다결정 실리콘층 17, 37 : 텅스텐층15, 35: polycrystalline silicon layer 17, 37: tungsten layer

19, 41 : 텅스텐나이트라이드막 21, 39 : 질화막19, 41: tungsten nitride film 21, 39: nitride film

23, 43 : 제 2 산화막23, 43: a second oxide film

본 발명은 트랜지스터의 제조 방법에 관한 것으로, 특히 다결정 실리콘층/텅스텐(W)층의 금속 게이트 전극 형성 공정 시 상기 텅스텐층 측벽에 확산 방지막을 형성하여 소자의 특성, 수율 및 신뢰성을 향상시키는 트랜지스터의 제조 방법에 관한 것이다. The present invention relates to a method of manufacturing a transistor, and more particularly, to a method of manufacturing a transistor, in which a diffusion barrier film is formed on a sidewall of a tungsten layer in a process of forming a metal gate electrode of a polycrystalline silicon layer / tungsten (W) layer to improve the characteristics, yield and reliability And a manufacturing method thereof.                         

최근 미세 소자 제조 시 낮은 게이트 저항이 요구되므로 게이트 전극 형성 물질로 텅스텐과 같은 저항이 낮은 금속을 사용하고 있다.In recent years, low gate resistance is required in manufacturing fine devices, and therefore, a metal having a low resistance such as tungsten is used as a gate electrode forming material.

이때, 게이트 산화막 상에 직접 텅스텐층을 형성하는 구조는 상기 게이트 산화막의 특성을 열화시키기 때문에 상기 게이트 산화막과 텅스텐층 사이에 다결정 실리콘층을 형성한 후, 서로간의 반응을 막기 위해 상기 다결정 실리콘층과 텅스텐층 사이에 텅스텐나이트라이드막(WNx)을 형성한 구조의 게이트 전극을 사용하고 있다.At this time, since the structure of forming the tungsten layer directly on the gate oxide film deteriorates the characteristics of the gate oxide film, the polysilicon layer is formed between the gate oxide film and the tungsten layer, A gate electrode having a structure in which a tungsten nitride film WNx is formed between tungsten layers is used.

도 1a 내지 도 1c는 종래 기술에 따른 트랜지스터의 제조 방법을 도시한 단면도이다.1A to 1C are cross-sectional views illustrating a method of manufacturing a transistor according to the related art.

도 1a를 참조하면, 반도체 기판(11)상에 제 1 산화막(13), 다결정 실리콘층(15) 및 텅스텐층(17)을 순차적으로 형성한다.1A, a first oxide film 13, a polycrystalline silicon layer 15, and a tungsten layer 17 are sequentially formed on a semiconductor substrate 11.

그리고, 암모니아(NH3) 가스를 사용한 어닐(Anneal) 공정을 전면에 실시하여 상기 다결정 실리콘층(15)과 텅스텐층(17) 사이에 확산 방지막인 텅스텐나이트라이드막(19)을 형성한다.An annealing process using ammonia (NH 3 ) gas is performed on the entire surface to form a tungsten nitride film 19, which is a diffusion barrier film, between the polycrystalline silicon layer 15 and the tungsten layer 17.

도 1b를 참조하면, 상기 텅스텐층(17) 상에 하드 마스크(Hard mask)층인 질화막(21)을 형성한다.Referring to FIG. 1B, a nitride film 21, which is a hard mask layer, is formed on the tungsten layer 17.

도 1c를 참조하면, 상기 질화막(21) 상에 감광막을 형성하고, 상기 감광막을 게이트 전극이 형성될 부위에만 남도록 선택적으로 노광 및 현상하여 감광막 패턴을 형성한다. Referring to FIG. 1C, a photoresist layer is formed on the nitride layer 21, and the photoresist layer is selectively exposed and developed so that the photoresist layer remains only on a portion where a gate electrode is to be formed, thereby forming a photoresist pattern.                         

그리고, 상기 감광막 패턴을 마스크로 상기 질화막(21)을 식각하고, 상기 감광막 패턴을 제거한다.Then, the nitride film 21 is etched using the photoresist pattern as a mask, and the photoresist pattern is removed.

이어, 상기 질화막(21)을 마스크로 상기 텅스텐층(17), 텅스텐나이트라이드막(19) 및 다결정 실리콘층(15)을 식각하여 게이트 전극을 형성한다.Then, the tungsten layer 17, the tungsten nitride film 19 and the polycrystalline silicon layer 15 are etched using the nitride film 21 as a mask to form a gate electrode.

그리고, 금속은 산화되지 않고 실리콘 박막만을 산화시키는 선택 산화 공정을 전면에 실시하여 상기 노출된 반도체 기판(11)과 다결정 실리콘층(15) 표면상에 제 2 산화막(23)을 형성한다.A selective oxidation process for oxidizing only the silicon thin film without oxidizing the metal is performed on the entire surface to form the second oxide film 23 on the surface of the exposed semiconductor substrate 11 and the polycrystalline silicon layer 15. [

그러나, 종래의 다결정 실리콘층/텅스텐층의 금속 게이트 전극 형성 공정 시 암모니아 가스를 사용한 어닐 공정을 진행한 후 상기 텅스텐층과 다결정 실리콘층을 패터닝(Patterning)하여 게이트 전극을 형성하므로, 상기 텅스텐층 측벽이 노출되기 때문에 후속 공정인 선택 산화 공정 시 텅스텐이 텅스텐옥사이드(WO3) 형태의 증기로 빠져나오는 아웃 가싱(Out gassing) 현상이 발생되므로 상기 반도체 기판이 오염되어 누설 전류가 증가되고 또한 상기 텅스텐층 측벽이 비이상적으로 산화되어 게이트 전극 패턴이 거칠어지므로 소자의 특성, 수율 및 신뢰성이 저하되는 문제점이 있었다.However, in the process of forming the metal gate electrode of the conventional polycrystalline silicon layer / tungsten layer, after the annealing process using the ammonia gas is performed, the gate electrode is formed by patterning the tungsten layer and the polycrystalline silicon layer, An out gassing phenomenon occurs in which the tungsten is released into the vapor of the tungsten oxide (WO 3 ) type during the selective oxidation process, which is a subsequent process, so that the semiconductor substrate is contaminated to increase the leakage current and the tungsten layer The side walls are unexpectedly oxidized, and the gate electrode pattern becomes rough, so that the characteristics, yield and reliability of the device are deteriorated.

본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 다결정 실리콘층/텅스텐층의 금속 게이트 전극 형성 공정에 있어서 상기 텅스텐층을 패터닝하고 확산 방지막을 형성하기 위해 암모니아 가스를 사용한 어닐 공정을 진행한 후 상기 다결정 실리콘층을 패터닝하여 게이트 전극을 형성하므로, 상기 텅스텐층 측벽에도 확산 방지막을 형성하기 때문에 후속 공정인 선택 산화 공정 시 상기 텅스텐층 측벽에서 발생되는 텅스텐의 아웃 가싱 현상을 방지하는 트랜지스터의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been devised in order to solve the above-mentioned problems, and it is an object of the present invention to provide a method for patterning a tungsten layer in a process of forming a metal gate electrode of a polycrystalline silicon layer / tungsten layer and an annealing process using ammonia gas for forming a diffusion barrier layer, Since the polysilicon layer is patterned to form a gate electrode, a diffusion preventing film is formed on the sidewall of the tungsten layer. Therefore, a method of manufacturing a transistor that prevents outgassing of tungsten generated in a sidewall of the tungsten layer during a selective oxidation process The purpose is to provide.

이상의 목적을 달성하기 위한 본 발명은 반도체 기판 상에 절연막, 실리콘층, 금속층 및 하드 마스크층을 순차적으로 형성하는 단계, 게이트 전극용 마스크를 사용한 사진식각 공정으로 상기 하드 마스크층과 금속층을 식각하는 단계, 열처리 공정으로 상기 실리콘층과 금속층 사이 및 상기 금속층 측벽에 확산 방지막을 형성하는 단계 및 상기 하드 마스크층을 마스크로 상기 실리콘층과 절연막을 식각하여 게이트 전극을 형성하는 단계를 포함하는 트랜지스터의 제조 방법을 제공하는 것과,According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: sequentially forming an insulating layer, a silicon layer, a metal layer, and a hard mask layer on a semiconductor substrate; etching the hard mask layer and the metal layer by a photolithography process using a mask for a gate electrode Forming a diffusion barrier film between the silicon layer and the metal layer and a sidewall of the metal layer by a heat treatment process and etching the silicon layer and the insulating layer using the hard mask layer as a mask to form a gate electrode , &Lt; / RTI &gt;

상기 실리콘층을 300 ∼ 2000Å 두께의 다결정 실리콘층 또는 비정질 실리콘층으로 형성하는 것과,The silicon layer is formed of a polycrystalline silicon layer or an amorphous silicon layer with a thickness of 300 to 2000 Å,

상기 금속층을 텅스텐과 같은 고내열성과 저저항을 동시에 갖는 금속층으로 형성하는 것과,The metal layer is formed of a metal layer having high heat resistance and low resistance such as tungsten,

상기 텅스텐층을 스퍼터링법 또는 화학기상 증착법으로 형성하는 것과,Forming the tungsten layer by a sputtering method or a chemical vapor deposition method,

상기 하드 마스크층을 질화막과 같은 후속 층간 절연막에 대해 건식 식각 선택비가 좋으며 절연성이 우수한 성질을 갖는 절연막으로 형성하는 것과,Wherein the hard mask layer is formed of an insulating film having a good dry etching selectivity with respect to a subsequent interlayer insulating film such as a nitride film,

상기 질화막을 저압화학기상 증착법 또는 플라즈마화학기상 증착법으로 형성 하는 것과,Forming the nitride film by a low pressure chemical vapor deposition method or a plasma chemical vapor deposition method,

상기 열처리 공정은 500 ∼ 800℃의 온도로 암모니아 가스를 사용한 어닐 공정을 다결정 실리콘층과 식각된 텅스텐층을 포함한 전면에 실시하는 것을 특징으로 한다.The annealing process is performed at an annealing process using ammonia gas at a temperature of 500 to 800 ° C on the entire surface including the polycrystalline silicon layer and the etched tungsten layer.

본 발명의 원리는 다결정 실리콘층/텅스텐층의 금속 게이트 전극 형성 공정 시 상기 텅스텐층을 패터닝하고 암모니아 가스를 사용한 어닐 공정을 진행하여 상기 텅스텐층 측벽에도 확산 방지막을 형성하므로, 종래 기술에서 텅스텐층 측벽을 노출시킨 상태에서 후속 공정인 선택 산화 공정을 진행하여 발생된 텅스텐의 아웃 가싱 현상을 방지하여 소자의 특성, 수율 및 신뢰성을 향상시키는 발명이다.The principle of the present invention is that the tungsten layer is patterned in the process of forming the metal gate electrode of the polycrystalline silicon layer / tungsten layer and the annealing process using ammonia gas is performed to form a diffusion barrier film on the side wall of the tungsten layer. The selective oxidation process is performed in a subsequent process to prevent the outgassing phenomenon of tungsten, thereby improving the characteristics, yield and reliability of the device.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d는 본 발명의 실시 예에 따른 트랜지스터의 제조 방법을 도시한 단면도이다.2A to 2D are cross-sectional views illustrating a method of manufacturing a transistor according to an embodiment of the present invention.

도 2a를 참조하면, 반도체 기판(31)상에 제 1 산화막(33), 다결정 실리콘층(35), 텅스텐층(37) 및 하드 마스크층인 질화막(39)을 순차적으로 형성한다. 이때, 상기 다결정 실리콘층(35)을 300 ∼ 2000Å의 두께로 형성하고, 상기 다결정 실리콘층(35) 대신에 비정질 실리콘층으로 형성할 수 있다. 그리고 상기 텅스텐층(37)을 스퍼터링(Sputtering)법 또는 화학기상 증착법으로 형성하고, 상기 텅스텐층(37) 대신에 고내열성과 저저항을 동시에 갖는 다른 금속층으로도 형성할 수 있다. 이어 질화막(39)을 저압화학기상 증착법 또는 플라즈마(Plasma)화학기상 증착법으로 형성하고, 상기 질화막(39) 대신에 후속 층간 절연막에 대해 건식 식각 선택비가 좋으며 절연성이 우수한 성질을 갖는 다른 절연막으로도 형성할 수 있다.2A, a first oxide film 33, a polycrystalline silicon layer 35, a tungsten layer 37, and a nitride film 39 as a hard mask layer are sequentially formed on a semiconductor substrate 31. At this time, the polycrystalline silicon layer 35 may be formed to a thickness of 300 to 2000 Å, and the amorphous silicon layer may be formed instead of the polycrystalline silicon layer 35. The tungsten layer 37 may be formed by a sputtering method or a chemical vapor deposition method. Instead of the tungsten layer 37, another metal layer having high heat resistance and low resistance may be formed. Subsequently, a nitride film 39 is formed by a low-pressure chemical vapor deposition method or a plasma chemical vapor deposition method. Instead of the nitride film 39, another insulating film having a good dry etching selectivity to the subsequent interlayer insulating film, can do.

도 2b를 참조하면, 상기 질화막(39) 상에 감광막을 형성하고, 상기 감광막을 게이트 전극이 형성될 부위에만 남도록 선택적으로 노광 및 현상하여 감광막 패턴을 형성한다.Referring to FIG. 2B, a photoresist layer is formed on the nitride layer 39, and the photoresist layer is selectively exposed and developed so that the photoresist layer remains only on a portion where a gate electrode is to be formed, thereby forming a photoresist pattern.

그리고, 상기 감광막 패턴을 마스크로 상기 질화막(39)을 식각하고, 상기 감광막 패턴을 제거한다.Then, the nitride film 39 is etched using the photoresist pattern as a mask, and the photoresist pattern is removed.

이어, 상기 질화막(39)을 마스크로 상기 텅스텐층(37)을 식각한다.Then, the tungsten layer 37 is etched using the nitride film 39 as a mask.

도 2c를 참조하면, 500 ∼ 800℃의 온도로 암모니아 가스를 사용한 어닐 공정을 전면에 실시하여 상기 다결정 실리콘층(35)과 텅스텐층(37) 사이 그리고 상기 텅스텐층(37) 측벽에 확산 방지막인 텅스텐나이트라이드막(WNx)(41)을 형성한다.Referring to FIG. 2C, an annealing process using ammonia gas at a temperature of 500 to 800 ° C is performed on the entire surface to form a diffusion barrier layer (not shown) on the sidewalls of the tungsten layer 37 and between the polycrystalline silicon layer 35 and the tungsten layer 37. Tungsten nitride film (WNx) 41 is formed.

도 2d를 참조하면, 상기 질화막(39)을 마스크로 상기 다결정 실리콘층(35)을 식각하여 상기 다결정 실리콘층(35)/텅스텐층(37)의 적층구조의 게이트 전극을 형성한다.Referring to FIG. 2D, the polysilicon layer 35 is etched using the nitride film 39 as a mask to form a gate electrode having a stacked structure of the polycrystalline silicon layer 35 and the tungsten layer 37.

그리고, 800 ∼ 1000℃의 온도에서 수소(H2) + 수분(H2O) 분위기 중 수분의 분압을 전체 압력의 5 ∼ 20%로 사용한 선택 산화 공정을 전면에 실시하여 상기 노출된 반도체 기판(31)과 다결정 실리콘층(35) 표면상에 제 2 산화막(43)을 선택적으로 형성한다.Then, a selective oxidation process using a partial pressure of water in an atmosphere of hydrogen (H 2 ) + water (H 2 O) at 5 to 20% of the total pressure at a temperature of 800 to 1000 ° C. is performed on the entire surface, 31 and the polycrystalline silicon layer 35, as shown in FIG.

본 발명의 트랜지스터의 제조 방법은 다결정 실리콘층/텅스텐층의 금속 게이 트 전극 형성 공정 시 상기 텅스텐층을 패터닝하고 확산 방지막을 형성하기 위해 암모니아 가스를 사용한 어닐 공정을 진행한 후 상기 다결정 실리콘층을 패터닝하여 게이트 전극을 형성하므로, 상기 텅스텐층 측벽에도 확산 방지막을 형성하기 때문에 종래 기술에서 텅스텐층 측벽을 노출시킨 상태에서 후속 공정인 선택 산화 공정을 진행하여 발생된 텅스텐의 아웃 가싱 현상을 억제하여 반도체 기판의 오염 및 게이트 전극 패턴의 거칠어짐 현상을 방지하므로 소자의 특성, 수율 및 신뢰성을 향상시키는 효과가 있다.In the method of manufacturing a transistor of the present invention, the tungsten layer is patterned in a process of forming a metal gate electrode of a polycrystalline silicon layer / tungsten layer, an annealing process using ammonia gas is performed to form a diffusion barrier layer, Since the diffusion barrier film is formed on the sidewalls of the tungsten layer, the selective oxidation process is performed in a state where the sidewalls of the tungsten layer are exposed in the prior art, thereby suppressing the outgassing phenomenon of tungsten, Contamination of the gate electrode pattern and roughness of the gate electrode pattern are prevented, thereby improving the characteristics, yield and reliability of the device.

Claims (7)

반도체 기판 상에 절연막, 실리콘층, 금속층 및 하드 마스크층을 순차적으로 형성하는 단계;Sequentially forming an insulating film, a silicon layer, a metal layer, and a hard mask layer on a semiconductor substrate; 게이트 전극용 마스크를 사용한 사진식각 공정으로 상기 하드 마스크층과 금속층을 식각하는 단계;Etching the hard mask layer and the metal layer by a photolithography process using a mask for a gate electrode; 열처리 공정으로 상기 실리콘층과 금속층 사이 및 상기 금속층 측벽에 확산 방지막을 형성하는 단계;Forming a diffusion barrier layer between the silicon layer and the metal layer and the sidewall of the metal layer by a heat treatment process; 상기 하드 마스크층을 마스크로 상기 실리콘층과 절연막을 식각하여 게이트 전극을 형성하는 단계를 포함하는 트랜지스터의 제조 방법.And etching the silicon layer and the insulating layer using the hard mask layer as a mask to form a gate electrode. 제 1 항에 있어서,The method according to claim 1, 상기 실리콘층을 300 ∼ 2000Å 두께의 다결정 실리콘층 또는 비정질 실리콘층으로 형성함을 특징으로 하는 트랜지스터의 제조 방법.Wherein the silicon layer is formed of a polycrystalline silicon layer or amorphous silicon layer having a thickness of 300 to 2000 angstroms. 제 1 항에 있어서,The method according to claim 1, 상기 금속층을 텅스텐과 같은 고내열성과 저저항을 동시에 갖는 금속층으로 형성함을 특징으로 하는 트랜지스터의 제조 방법.Wherein the metal layer is formed of a metal layer having high heat resistance and low resistance simultaneously such as tungsten. 제 3 항에 있어서,The method of claim 3, 상기 텅스텐층을 스퍼터링법 또는 화학기상 증착법으로 형성함을 특징으로 하는 트랜지스터의 제조 방법.Wherein the tungsten layer is formed by a sputtering method or a chemical vapor deposition method. 제 1 항에 있어서,The method according to claim 1, 상기 하드 마스크층을 질화막과 같은 후속 층간 절연막에 대해 건식 식각 선택비가 좋으며 절연성이 우수한 성질을 갖는 절연막으로 형성함을 특징으로 하는 트랜지스터의 제조 방법.Wherein the hard mask layer is formed of an insulating film having good dry etching selectivity with respect to a subsequent interlayer insulating film such as a nitride film and having excellent insulating properties. 제 5 항에 있어서,6. The method of claim 5, 상기 질화막을 저압화학기상 증착법 또는 플라즈마화학기상 증착법으로 형성함을 특징으로 하는 트랜지스터의 제조 방법.Wherein the nitride film is formed by a low pressure chemical vapor deposition method or a plasma chemical vapor deposition method. 제 1 항에 있어서,The method according to claim 1, 상기 열처리 공정은 500 ∼ 800℃의 온도로 암모니아 가스를 사용한 어닐 공정을 다결정 실리콘층과 식각된 텅스텐층을 포함한 전면에 실시함을 특징으로 하는 트랜지스터의 제조 방법.Wherein the annealing process is performed at an entire surface including an amorphous silicon layer and an etched tungsten layer using an ammonia gas at a temperature of 500 to 800 ° C.
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