KR100752168B1 - Photodiode Measurement Patterns of Vertical CMOS Image Sensors - Google Patents

Abstract

The present invention relates to a photodiode measuring pattern of a vertical CMOS image sensor capable of measuring the leakage current of an efficient photodiode in a vertical CMOS image sensor, and the photodiode of the vertical CMOS image sensor of the present invention. The measurement pattern is a photodiode measurement pattern of a vertical image sensor in which first, second, and third photodiodes are vertically disposed above a substrate, wherein the first to third photodiode measurements are formed corresponding to different portions. And a ground terminal formed at a predetermined portion on the substrate to be spaced apart from the first to third metal pad terminals and the first to third metal pad terminals.

Vertical CMOS image sensor, leakage current, measurement pattern, photodiode

Description

Test pattern for Photo-diode in Vertical-type CMOS image sensor

1 is a plan view illustrating a leakage current measurement pattern of a photodiode of a general CMOS image sensor

2 is a cross-sectional view showing unit pixels of a general CMOS image sensor

3 is a plan view showing a leakage current measurement pattern of the photodiode of the vertical CMOS image sensor of the present invention

4 is a cross-sectional view illustrating a unit pixel of a vertical CMOS image sensor.

* Description of the symbols for the main parts of the drawings *

100: substrate 102: red photodiode

104: first plug 105: green photodiode

105a: first connection portion 108; 2nd plug

109: blue-blue photodiode 109a: second connection portion

110: third connection portion 111 interlayer insulating film

112: contact material 113: ground metal pad

114: red metal pad 115: blue metal pad

116: green metal pad 117: device isolation film

118: first epi layer 119: second epi layer

The present invention relates to an image sensor, and more particularly, to a vertical CMOS image sensor, a photodiode measuring pattern of a vertical CMOS image sensor capable of measuring a leakage current of an efficient photodiode, and a measuring method thereof.

In general, CMOS image sensors are semiconductor devices that convert an optical image into an electrical signal. Among them, a charge coupled device (CCD) includes an individual metal-oxide silicon (MOS) capacitor. A device in which charge carriers are stored and transported in a capacitor while being in close proximity to one another.

CMOS image sensors, on the other hand, use CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits to create as many photodiodes as the number of pixels and transistors connected to them to open and close channels. The transistors sequentially detect red, green, and blue optical signals using the transistors and output the same by a switching method.

Such CMOS image sensor has many advantages such as low power consumption, low process cost and high level of integration. In particular, with recent technological advances, CMOS image sensors have been spotlighted as an alternative to charge-coupled devices (CCDs) in many applications.

Such CMOS image sensors are classified into 3T type, 4T type, and 5T type according to the number of transistors. The 3T type consists of one photodiode and three transistors, and the 4T type consists of one photodiode and four transistors.

The unit pixel of a general 3T CMOS image sensor is composed of one photodiode (PD) and three nMOS transistors (T1, T2, T3). The cathode of the photodiode PD is connected to the drain of the first nMOS transistor T1 and the gate of the second nMOS transistor T2.

The sources of the first and second nMOS transistors T1 and T2 are all connected to a power supply line supplied with a reference voltage VR, and the gate of the first nMOS transistor T1 has a reset signal RST. It is connected to the reset line supplied.

Further, the source of the third nMOS transistor T3 is connected to the drain of the second nMOS transistor, the drain of the third nMOS transistor T3 is connected to a read circuit (not shown in the drawing) via a signal line, The gate of the third nMOS transistor T3 is connected to a column select line to which a selection signal SLCT is supplied.

Accordingly, the first nMOS transistor T1 is referred to as a reset transistor Rx, the second nMOS transistor T2 is referred to as a drive transistor Dx, and the third nMOS transistor T3 is referred to as a selection transistor Sx.

Such CMOS image sensor has a measurement pattern for measuring the leakage current of the photodiode.

Hereinafter, a leakage current measurement pattern of a conventional CMOS image sensor and a photodiode thereof will be described with reference to the accompanying drawings.

1 is a plan view illustrating a leakage current measurement pattern of a photodiode of a general CMOS image sensor, and FIG. 2 is a cross-sectional view illustrating unit pixels of a general CMOS image sensor.

As shown in FIG. 2, in a general CMOS image sensor, a first epitaxial layer 3 is stacked on a substrate 1, and a second epitaxial layer 6 is formed on the first epitaxial layer 3. A shallow trench isolation (STI) film 9 is formed in a predetermined region in the second epitaxial layer 6 to define an active region in which the STI film 9 is not formed. An n + type impurity is implanted in a predetermined region to define the photodiode region 9, and another p + type impurity is implanted in the other predetermined region to define the source / drain region 10. A poly-metal dielectric (PMD) layer 11 is formed on the second epitaxial layer 6, the first and second openings of the photodiode region 9 and the source / drain region 10. Two contact holes 12 are formed, and are connected to the photodiode layer 15 and the ground terminal 13 on the upper side, respectively.

As shown in FIG. 1, the photodiode has a well shape formed by being doped with n + type. In this case, the dark current measurement pattern of the CMOS image sensor is a leakage area for one photodiode. It is made large at about 2 × 10 ⁴ μm ² or more. This is the same diode leakage current measurement pattern used in General CMOS Technology. In this case, in the case of a general CMOS image sensor, transistors for driving and the like are formed horizontally, including a photo diode, and the unit pixel uses color filters of red (R), green (G), and blue (B). Will detect the light of the corresponding color.

In this case, in a general CMOS image sensor, one unit pixel must include all of the red (R), green (G), and blue (B) color filters formed in a planar shape, so that the size of the unit is large. Thus, in the case of such a general CMOS image sensor, the pixel integration degree is lowered.

As such, a vertical image sensor has been proposed to improve the problem of lowering the density of a general image sensor.

However, the conventional image sensor as described above has the following problems.

In this case, in a general CMOS image sensor, one unit pixel includes the red (R), green (G), and blue (B) color filters, respectively, and the image is formed on a semiconductor substrate by increasing its area. The integration of the sensor is lowered.

To improve this, a vertical image sensor has been developed. The vertical image sensor has a red / green / blue photodiode for detecting red (R), green (G), and blue (B) signals per unit pixel. It has a vertical structure. Therefore, it is difficult to apply the existing diode measurement pattern as it is. In addition, even though each diode is manufactured and measured separately, the vertical isolation leakage between the red, green, and blue diodes (Vertical isolation leakage) is not taken into consideration, there is a disadvantage that a plurality of patterns are required.

The present invention has been made to solve the above problems, in the vertical CMOS image sensor, a photodiode measuring pattern of the vertical CMOS image sensor capable of measuring the leakage current of the efficient photodiode and a measuring method thereof The purpose is to provide.

The photodiode measurement pattern of the vertical CMOS image sensor of the present invention for achieving the above object is the photodiode measurement of the vertical image sensor in which the first, second, and third photodiodes are vertically arranged above the substrate. In the pattern, the first to third metal pad terminals for measuring the first to third photodiodes and the first to third metal pad terminals formed to correspond to different portions, and the ground terminals formed at predetermined portions on the substrate. Its features are made to include.

The first photodiode is located on a substrate, the second photodiode is located on a first epilayer formed on the substrate, and the third photodiode is a second epilayer formed on the first epilayer. Located in the phase.

The first photodiode is connected to the first metal pad terminal at another portion that does not overlap with the first photodiode through a plug material in the first and second epilayers.

The plug material is connected to a first connection portion formed together when forming the second photodiode on the surface of the first epitaxial layer, respectively, and to a second connection portion formed together when forming the third photodiode on the surface of the second epilayer. do.

The second photodiode is connected to the second metal pad terminal at another portion of the second epitaxial layer that does not overlap with the first photodiode through a plug material.

The plug materials are each formed in connection with a third connection portion formed together when the third photodiode is formed on the surface of the second epitaxial layer.

Hereinafter, a photo diode measuring pattern and a measuring method thereof of the vertical CMOS image sensor according to the present invention will be described in detail with reference to the accompanying drawings.

The present invention relates to a test pattern for evaluating leakage currents of red, green, and blue photodiodes constituting pixels of a vertical CMOS image sensor. Pixel design is the most important part of CMOS image sensor technology with high resolution such as 2M and 3M, and the quality of photodiode constituting the pixel is an important item that determines the performance of the entire image sensor system.

In general CMOS image sensor, there is one photodiode per pixel, which uses a color filter to detect red / green / blue light. In this case, the diode measurement pattern used in the conventional general CMOS standard technology can be sufficiently evaluated.

The vertical CMOS image sensor, however, has three (red / green / blue) photodiodes per pixel, which uses a special method of detecting both red, green and blue. It is inappropriate to apply the above general diode pattern to evaluate this. The present invention supplements the advantages and newly constructs a test pattern to be suitable for the leakage current evaluation of pixels.

3 is a plan view illustrating a leakage current measurement pattern of a photodiode of a vertical CMOS image sensor of the present invention, and FIG. 4 is a cross-sectional view illustrating unit pixels of a vertical CMOS image sensor.

As shown in FIG. 3, the leakage current measurement pattern of the photodiode of the vertical CMOS sensor of the present invention uses a large number of pixel array structures similar to the actual image sensor circuit. That is, three photodiodes consisting of the number of rows and columns are arranged vertically. Each photodiode is connected to the common terminal (metal pad) of red (1), green (2), and blue (3) through the metal wiring, and the GND terminal is composed of (4).

Table 1 shows the leakage current measurement method for each photodiode. The area of each photodiode is in the silicon epilayer in red and green, thus doubling the product of the number of pixel arrays and the size of one photodiode. In the case of blue, since there are buried type and surface type depending on the position of the photodiode, the double type for the buried type and the double type for the surface type may be calculated. Considering the measurable resolution of the measuring equipment, make the total area larger than about 2x104um2.

Measurement target Measure photodiode Pad terminal definition area Vf COM Leakage current Red (R) (One) (4) 2 * number of arrays * unit size Green (G) (2) (4) 2 * number of arrays * unit size Blue (B) (3) (4) n * number of arrays * unit size, n = 2 (when buried, n = 1 (surface)

As illustrated in FIG. 4, in the CMOS image sensor to which the photodiode measurement pattern of the CMOS image sensor of the present invention is applied, red, green, and blue photodiodes 102, 105, and 109 are vertically formed.

In the case of the red photodiode 102, an initial silicon epitaxial layer (starting wafer) 100, the green photodiode 105 is a first epi layer 113, the blue photodiode 109 Are respectively formed on the 2nd Epi layer 118. Each photodiode 102, 105, 109 is commonly fabricated in the form of n + ion implantation wells, particularly in the case of red, green photodiodes 102, 105 for the first plug 104 and A second plug 108 is added to connect the photodiode 102 and 105 to the metal pads 114 and 116 of the corresponding color. In addition, p + ion implantation is formed in the ground (GND) region to form a source / drain region 110, and is connected to a common (COM) terminal 113 during measurement.

Here, the red photodiode 102 includes a first plug 104, a first connection portion 105a formed by being connected to the first plug 104 together with the green photodiode 105, and a second plug. 108 and a second connection portion 109a connected to the second plug 108 and formed in the contact hole 112 formed in the interlayer insulating layer to be formed together when the blue photodiode 109 is formed. It is connected to the red metal pattern 114.

The green photodiode 105 is connected to the second plug 108, the second plug 108, and the second connection part 109a and the interlayer insulating layer formed together when the blue photodiode 109 is formed. It is connected to the green metal pad 116 through the contact material 112 filled in the contact hole formed in the (111).

In addition, the blue photodiode 109 is connected to the blue metal pad 116 through a contact material 112 filled in a contact hole formed in the interlayer insulating layer 111.

In this case, each of the metal pads 114, 115, 116, and 113 is driven by applying a voltage to a corresponding photodiode or ground portion.

In addition, a voltage is externally applied to each of the metal pads 114, 115, 116, and 113 to measure leakage current flowing through the corresponding photodiode.

Here, reference numeral 117, which is not described, denotes an isolation layer, and regions except for the isolation layer are defined as active regions by impurity implantation.

The photodiode measurement pattern of the vertical CMOS image sensor of the present invention includes a metal pad terminal for applying a voltage to each of the photodiodes formed vertically, wherein the metal pad terminals are located in an overlapped area. It is not located. That is, the lower the photodiode is formed in a larger area, and by forming a metal pad terminal in a position different from the metal pad terminal connected to the photodiode located in the upper layer through the plug and contact material on the upper side, There will be no difficulty.

Such a test pattern enables isolation between photodiodes, whereby the leakage current between the photodiodes can be measured to evaluate the relative thicknesses of the first epitaxial layer 113 and the second epitaxial layer 118 relative to each other. .

Such a test pattern can also evaluate the capacitance of photodiodes and the like. This evaluation of capacitance can be useful in understanding the physical behavior of pixels and in designing simulations.

Hereinafter, a measuring method using a photodiode measuring pattern of the vertical image sensor of the present invention will be described with reference to Table 2.

Measurement target Measure photodiode Pad terminal definition Vf COM Vertical isolation between photodiodes Red and green One 2 Evaluation of the first epilayer Green and blue 2 3 Evaluation of the second epilayer Capacitance of Photodiode Red One 4 Area = 2 * array number * unit size green 2 4 Area = 2 * array number * unit size blue 3 4 Area = n * number of arrays * unit size, n = 2 for investment type, n = 1 for surface type

The photodiode measurement pattern of the vertical CMOS image sensor of the present invention as described above and a measuring method thereof have the following effects.

First, due to the vertical structure, it is possible to evaluate isolation characteristics that may be weak when measuring leakage current of each photodiode. In other words, the leakage current between the photodiodes can be measured to electrically evaluate the thickness of the first and second epilayers.

Second, the capacitance of the photodiode can be measured. By evaluating this, it can be useful for understanding the material behavior of pixels and for simulation and design.

Claims (7)

A substrate, a first epitaxial layer and a second epitaxial layer sequentially formed on the substrate, and first to third photodiodes respectively formed on the substrate, the first and second epitaxial layers, and overlapping each other; In the photodiode measurement pattern of the vertical image sensor, An interlayer insulating layer formed on the entire surface of the second epitaxial layer; A first metal pad terminal electrically connected to the first photodiode on the interlayer insulating layer which does not overlap the first photodiode; A second metal pad terminal spaced apart from the first metal pad terminal and electrically connected to the second photo diode on the interlayer insulating layer corresponding to the second photo diode; A third metal pad terminal spaced apart from the first and second metal pad terminals and electrically connected to the third photo diode on the interlayer insulating layer to correspond to the third photo diode; And And a ground terminal spaced apart from the first to third metal pad terminals and formed on a predetermined portion of the upper portion of the interlayer insulating layer. delete The method of claim 1, The first photodiode is connected to the first and second plug materials formed in the first epitaxial layer and the second epitaxial layer, respectively, up and down with the first and second plug materials, and on the surface of the first epitaxial layer. A first connection portion formed together when forming the second photodiode so as to overlap the first metal pad terminal; and the first metal pad terminal connected to the second plug material to form the third photodiode on the surface of the second epitaxial layer. The first metal pad terminal is connected to another portion of the interlayer insulating layer that is formed to overlap with the first metal diode and a contact material connecting the first metal pad terminal and the second connection portion in the interlayer insulating layer. Photodiode measurement pattern of a vertical CMOS image sensor. delete The method of claim 1, Wherein the second photodiode is connected to the second metal pad terminal at another portion of the second epitaxial layer that does not overlap with the first photodiode through a third plug material. Photodiode measurement pattern. The method of claim 5, And the third plug material is connected to a third connection part formed together when the third photodiode is formed on the surface of the second epitaxial layer, respectively. The method of claim 1, The photodiode measurement pattern of the vertical CMOS image sensor, wherein the first to third photodiodes are red, green, and blue photodiodes, respectively.

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