KR100745373B1 - Probe card manufacturing method - Google Patents

Abstract

A method for manufacturing a probe card is provided to enhance the heat characteristic by additionally forming a conductive plug between a space transformer and a probe beam. A substrate(100) is etched to form a through-hole, and then a conductive plug is formed to bury the through-hole. A lower interconnection which is connected to the conductive plug is formed on a first surface of the substrate. A conductive bump is formed on the lower interconnection of the conductive plug, and then an adhesive layer(310) is formed on a surface of the conductive bump. An end portion of a probe beam(410) is adhered to the conductive bump via the adhesive layer.

Description

Probe card manufacturing method {METHOD FOR MANUFACTURE PROBE CARD}

1A to 1V are cross-sectional views illustrating a method of manufacturing a probe card according to a first embodiment of the present invention.

2A to 2W are cross-sectional views illustrating a method of manufacturing a probe card according to a second embodiment of the present invention.

3A to 3I are cross-sectional views illustrating a method of manufacturing a probe card according to a third embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a probe card, and in particular, by adding a substrate having a conductive plug for embedding a through-hole between a space transformer and a probe beam, repair is possible and the pitch of the probe card is reduced. A method of manufacturing a probe card that can be reduced.

One or more dies are formed on top of the wafer, and a wafer-level test must be performed to verify that each die is normally manufactured. Typically, wafer level testing is performed using a probe card with a plurality of probe tips formed thereon. The probe tip is press-connected to a plurality of pads formed on the wafer, and a test signal is received from a tester and transmitted to the plurality of pads.

As the size of the semiconductor device is reduced, the pitch of the pad is also reduced, and the spacing between the probe tips for pressurizing the pad and performing the test is also drastically reduced. In addition, the number of probe tips is rapidly increasing because a large number of dies must be tested in one test.

Various processes have been proposed to reduce the pitch of the probe team.

In the method of forming a probe tip on a space transformer, which is a silicon substrate, it is easy to reduce the pitch (pitch <80 µm), but it is difficult to perform a process such as insulation or plating, which is a rising factor such as manufacturing cost. In addition, in the case of using a ceramic, it is easy to reduce the pitch (pitch <80 mu m), but there is a problem that the ceramic substrate is weak in heat.

In order to solve the above-mentioned problem, the present invention enables the repair by reducing the pitch of the probe card by adding a substrate having a conductive plug for embedding a through-hole between the space transformer and the probe beam. It is an object of the present invention to provide a method for manufacturing a probe card.

Probe card manufacturing method according to the invention comprises the steps of (a) forming a through-hole by etching the substrate; (b) forming a conductive plug to fill the through-hole; (c) forming a lower metal wiring connected to the conductive plug on the first surface of the substrate; (d) forming a conductive bump on the lower metal wiring on the conductive plug; (e) forming an adhesive layer on the conductive bump surface; And (f) bonding an end portion of the probe beam to the conductive bump through the adhesive layer.

Here, it is preferable that the said board | substrate is a glass substrate.

In addition, the step (a) may comprise the steps of (a-1) forming a photoresist pattern exposing the through-hole predetermined region; And (a-2) etching the substrate by performing a sand blasting process using the photoresist pattern as an etching mask, wherein the step (b) comprises (b-1) the through-hole surface and Forming a seed layer on the second surface of the substrate; (b-2) forming a photoresist pattern for applying the seed layer on the second surface of the substrate; (b-3) performing a plating process to form a metal layer at least filling the through-holes; And (b-4) forming the conductive plug by performing a planarization etching process until the substrate is exposed.

The seed layer is preferably formed of a Ti / Cu layer, and the metal layer is preferably formed of a Cu layer.

In the step (d), (d-1) forming the lower TEOS film pattern having the first opening exposing the lower metal wiring surface on the upper portion of the conductive plug. (D-2) The lower TEOS film pattern and the first Forming a seed layer on a lower metal wiring surface on the conductive plug exposed through an opening; (d-3) forming a first mask layer pattern including a second opening exposing the first opening; (d-4) forming a first conductive bump filling the first opening and the second opening; (d-5) forming a second mask layer pattern including a third opening exposing the first conductive bumps; (d-6) forming a second conductive bump filling the third opening to form the conductive bump having a stack structure of the first and second conductive bumps; And (d-7) removing the second mask layer pattern, the first mask layer pattern, and the seed layer.

Here, step (d-4) may include forming a Ni—Co layer on the first surface by performing a plating process; And forming the first conductive bumps by performing a polishing process until the first mask layer pattern is exposed, wherein the step (d-5) is performed on the entire surface by performing a plating process. Forming a Ni—Co layer; And performing the polishing process until the second mask layer is exposed to form the second conductive bumps.

Probe card manufacturing method according to the invention may further comprise the step of forming a trench for the flow of the probe beam on the first surface of the substrate, in this case (d) step (d-1) Forming a lower TEOS film pattern having a first opening that exposes a lower metal interconnect surface over the conductive plug; (d-1) forming a seed layer on the lower metal wiring surface of the upper portion of the conductive plug exposed through the lower TEOS layer pattern and the first opening; (d-1) forming a mask layer pattern including a second opening that exposes the first opening; (d-1) forming the conductive bumps filling the first openings and the second openings; (d-1) removing the mask layer pattern and the seed layer.

Probe card manufacturing method according to another embodiment of the present invention comprises the steps of (a) etching the first substrate to form a trench; (b) etching the substrate to form a through-hole; (c) bonding a second substrate on which a probe beam is formed to the first substrate, wherein the through-hole is aligned with an end of the probe beam; (d) forming a conductive plug to fill the through-hole; And (e) removing the second substrate.

Here, the step (a) may include (a-1) forming one of a polysilicon layer, a metal layer, and a silicon layer on the first and second surfaces of the first substrate; And (a-2) etching the first surface of the first substrate to form the trench, wherein step (b) includes (b-1) an upper portion of the second surface of the first substrate. Forming a photoresist pattern exposing the through-hole predetermined region in the substrate; (b-2) preferably etching the first substrate using the photoresist pattern as an etch mask to form the through-holes.

In addition, the etching process of the step (b-2) is preferably a sand blasting process or a laser drilling process.

The method of manufacturing a probe card according to another embodiment of the present invention may further include forming a seed layer on the surface of the second substrate on which the probe beam is formed before performing step (c).

In addition, the bonding process of the step (c) is preferably a positive bonding process.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1A to 1V are cross-sectional views illustrating a method of manufacturing a probe card according to a first embodiment of the present invention.

Referring to FIG. 1A, a substrate 100 is prepared. The substrate 100 is preferably a glass substrate having a thickness of about 525 μm.

Referring to FIG. 1B, a photoresist pattern 110 is formed on the second surface of the substrate 100 to expose the through-hole predetermined region.

Referring to FIG. 1C, the through-hole 120 is formed by performing an etching process on the photoresist pattern 110 using an etching mask. Here, the etching process is preferably a sand blasting process. The through-holes 120 preferably have an upper diameter of about 300 μm and a lower diameter of about 80 μm.

Referring to FIG. 1D, the seed layer 130 is formed on the entire surface including the surface of the through-hole 120 and the second surface of the substrate 100 after removing the photoresist pattern 110. The seed layer 130 is preferably formed of a Ti / Cu layer. More preferably, the seed layer 130 is formed in a stacked structure of a Ti layer of about 0.01 μm and a Cu layer of about 1 μm.

Referring to FIG. 1E, a photoresist pattern 140 is formed on the seed layer 130 to expose the through-holes 120. The photosensitive film pattern 140 is preferably formed to a thickness of about 120㎛.

Referring to FIG. 1F, the metal layer 150 at least filling the through-hole 120 is formed. The metal layer 150 is preferably formed of Cu using a plating process.

Referring to FIG. 1G, the planar etching process is performed until the substrate 100 is exposed to form the conductive plug 160. The planarization etching process is preferably a chemical mechanical polishing (CMP) process.

Referring to FIG. 1H, an upper metal line 170 connected to the conductive plug 160 is formed on the second surface of the substrate 100. The upper metal wiring 170 is preferably formed by forming a pattern of about 0.5 μm Au film (not shown).

Referring to FIG. 1I, the upper TEOS layer 180, which is a protective layer for coating the upper metal wiring 170 and the second surface of the substrate 100, is formed. The upper TEOS film 180 is preferably formed to a thickness of about 500 GPa.

Referring to FIG. 1J, an Au film 190 is formed on the first surface of the substrate 100. The Au film 190 is preferably formed to a thickness of about 0.5 mu m.

Referring to FIG. 1K, the Au film 190 is patterned to form a lower metal wire 190a connected to the conductive plug 160. Next, a lower TEOS film 200, which is a protective film for coating the lower metal wire 190a and the first surface of the substrate 100, is formed.

Referring to FIG. 1L, the lower TEOS layer pattern 200a may include a first opening 210 that selectively etches the lower TEOS layer 200 to expose a surface of the lower metal interconnection 190a on the conductive plug 160. To form.

Referring to FIG. 1M, the seed layer 220 is formed on the entire surface including the lower TEOS layer pattern 200a and the lower metal interconnection 190a exposed through the first opening 210. The seed layer 220 is preferably formed of a Ti / Cu layer. More preferably, the seed layer 220 is formed in a stacked structure of a Ti layer of about 0.01 μm and a Cu layer of about 0.2 μm.

Next, a first mask layer pattern 230 including a second opening 240 exposing the first opening 210 is formed over the entire surface.

Referring to FIG. 1N, a first conductive bump 250 filling the first opening 210 and the second opening 240 is formed. When the first conductive bump 250 performs a plating process to form a Ni—Co layer (not shown) of about 100 μm on the first surface of the substrate 100 and the first mask layer pattern 230 is exposed. It is preferable to form by performing a polishing process such as a CMP process.

Referring to FIG. 1O, a second mask layer pattern 260 including a third opening 270 exposing the first conductive bumps 250 is formed.

Referring to FIG. 1P, a second conductive bump 280 filling the third opening 270 is formed. When the second conductive bump 280 performs a plating process to form a Ni—Co layer (not shown) of about 100 μm on the first surface of the substrate 100 and the second mask layer pattern 260 is exposed. It is preferable to form by performing a polishing process such as a CMP process.

Referring to FIG. 1Q, a stack structure of the first conductive bumps 250 and the second conductive bumps 280 by removing the second mask layer pattern 260, the first mask layer pattern 230, and the seed layer 220 is described. A conductive bump 290 is formed.

Referring to FIG. 1R, the lower TEOS layer pattern 200a and the upper TEOS layer 180 are removed.

Referring to FIG. 1S, an adhesive layer material 300 is formed on the surface of the conductive bump 290. The adhesive layer material 300 is preferably formed of an AuSn layer of about 20 μm using a screen printing process.

Referring to FIG. 1T, the adhesive layer material 300 in portions other than the upper surface of the conductive bump 290 may be removed to form the adhesive layer 310.

Referring to FIG. 1U, the bump 420 at the end of the probe beam 410 formed on the substrate 400 may be bonded to the conductive bump 290 through the adhesive layer 310.

Referring to FIG. 1V, the substrate 400 is removed to form a probe card.

2A to 2W are cross-sectional views illustrating a method of manufacturing a probe card according to a second exemplary embodiment of the present invention.

Referring to FIG. 2A, a substrate 100 is prepared. The substrate 100 is preferably a glass substrate having a thickness of about 525 μm.

Referring to FIG. 2B, a photoresist pattern 103 is formed on the first surface of the substrate 100 to define a trench for the flow of the probe beam.

Referring to FIG. 2C, the trench 100 is formed by etching the substrate 100 using the photoresist pattern 103 as an etching mask. The trench 105 is preferably formed to a depth of about 100㎛ by performing a sand blasting process.

Referring to FIG. 2D, a photoresist pattern 110 is formed on the second surface of the substrate 100 to expose the through-hole predetermined region.

Referring to FIG. 2E, the through-hole 120 is formed by performing an etching process on the photoresist pattern 110 using an etching mask. Here, the etching process is preferably a sand blasting process. The through-holes 120 preferably have an upper diameter of about 300 μm and a lower diameter of about 80 μm.

Referring to FIG. 2F, after removing the photoresist pattern 110, the seed layer 130 is formed on the entire surface including the through-hole 120 and the second surface of the substrate 100. The seed layer 130 is preferably formed of a Ti / Cu layer. More preferably, the seed layer 130 is formed in a stacked structure of a Ti layer of about 0.01 μm and a Cu layer of about 1 μm.

Referring to FIG. 2G, a photoresist pattern 140 is formed on the seed layer 130 to expose the through-holes 120. The photosensitive film pattern 140 is preferably formed to a thickness of about 120㎛.

Referring to FIG. 2H, the metal layer 150 at least filling the through-hole 120 is formed. The metal layer 150 is preferably formed of Cu using a plating process.

Referring to FIG. 2I, the planar etching process is performed until the substrate 100 is exposed to form the conductive plug 160. The planarization etching process is preferably a chemical mechanical polishing (CMP) process.

Referring to FIG. 2J, an upper metal wiring 170 connected to the conductive plug 160 is formed on the second surface of the substrate 100. The upper metal wiring 170 is preferably formed by forming a pattern of about 0.5 μm Au film (not shown).

Referring to FIG. 2K, an upper TEOS layer 180, which is a protective layer for coating the upper metal wiring 170 and the second surface of the substrate 100, is formed. The upper TEOS film 180 is preferably formed to a thickness of about 500 GPa.

Referring to FIG. 2L, an Au film 190 is formed on the first surface of the substrate 100 including the trench 105. The Au film 190 is preferably formed to a thickness of about 0.5 mu m.

Referring to FIG. 2M, the Au film 190 is patterned to form a lower metal wire 190a connected to the conductive plug 160. Next, a lower TEOS film 200, which is a protective film for coating the lower metal wire 190a and the first surface of the substrate 100, is formed.

Referring to FIG. 2N, the lower TEOS layer pattern 200a may include a first opening 210 that selectively etches the lower TEOS layer 200 to expose a surface of the lower metal interconnection 190a on the conductive plug 160. To form.

Referring to FIG. 2O, the seed layer 220 is formed on the entire surface including the lower TEOS layer pattern 200a and the lower metal interconnection 190a exposed through the first opening 210. The seed layer 220 is preferably formed of a Ti / Cu layer. More preferably, the seed layer 220 is formed in a stacked structure of a Ti layer of about 0.01 μm and a Cu layer of about 0.2 μm.

Referring to FIG. 2P, a mask layer pattern 230 including a second opening 240 exposing the first opening 210 is formed on the entire surface.

Referring to FIG. 2Q, a conductive bump 250 filling the first opening 210 and the second opening 240 is formed. The conductive bump 250 performs a plating process to form a Ni—Co layer (not shown) of about 100 μm on the first surface of the substrate 100, and the CMP process until the mask layer pattern 230 is exposed. It is preferable to form by performing the polishing process.

Referring to FIG. 2R, the mask layer pattern 230 and the seed layer 220 are removed.

Referring to FIG. 2S, the lower TEOS layer pattern 200a and the upper TEOS layer 180 are removed.

Referring to FIG. 2T, an adhesive layer material 260 is formed on the surface of the conductive bump 250. The adhesive layer material 260 is preferably formed of an AuSn layer of about 20 μm using a screen printing process.

Referring to FIG. 2U, the adhesive layer material 260 of the portion other than the upper surface of the conductive bump 250 is removed to form the adhesive layer 270.

Referring to FIG. 2V, the bump 320 at the end of the probe beam 310 formed on the substrate 300 is bonded to the conductive bump 250 through the adhesive layer 270.

Referring to FIG. 2W, the substrate 300 is removed to form a probe card.

3A to 3I are cross-sectional views illustrating a method of manufacturing a probe card according to a third exemplary embodiment of the present invention.

Referring to FIG. 3A, thin films 110a and 110b are formed on the first and second surfaces of the first substrate 100. Preferably, the substrate is a glass substrate, and the thin films 110a and 110b are preferably formed of any one of a polysilicon layer, a metal layer, and a silicon layer.

Referring to FIG. 3B, the first surface of the first substrate 100 is selectively etched to form the trench 120 for the flow of the probe beam.

Referring to FIG. 3C, a photoresist pattern 130 is formed on the second surface of the first substrate 100 to expose the through-hole predetermined region.

Referring to FIG. 3D, the first substrate 100 is etched using the photoresist pattern 130 as an etch mask to form through-holes 140. Here, the etching process is preferably a sand blasting process or a laser drilling process.

Referring to FIG. 3E, the thin films 110a and 110b and the photoresist pattern 130 are removed. The removal process is preferably performed by polishing, for example, grinding, polishing or CMP, until the first substrate 100 is exposed.

Referring to FIG. 3F, the seed layer 220 is formed on the second substrate 200 on which the probe beam 210 is formed.

Referring to FIG. 3G, the through-hole 140 is aligned at the end of the probe beam, and the second substrate 200 on which the probe beam 210 is formed is bonded to the first substrate 100. It is preferable that the bonding process is an anodic bonding process.

Referring to FIG. 3H, the conductive plug 230 filling the through-hole 140 is formed.

Referring to FIG. 3I, the second substrate 200 is removed to form a probe card. The removal process is preferably carried out using a KOH solution or a tetra-methyl ammonium hydroxide (TMAH) solution.

The method of manufacturing a probe card according to the present invention is excellent in thermal characteristics by adding a substrate having a conductive plug for embedding a through-hole between a space transformer and a probe beam, which enables repair and a pitch of the probe card ( Pitch) can be easily reduced.

Claims (32)

(a) etching the substrate to form a through-hole; (b) forming a conductive plug to fill the through-hole; (c) forming a lower metal wiring connected to the conductive plug on the first surface of the substrate; (d) forming a conductive bump on the lower metal wiring on the conductive plug; (e) forming an adhesive layer on the conductive bump surface; And (f) bonding an end portion of the probe beam to the conductive bump via the adhesive layer; Probe card manufacturing method comprising a. The method of claim 1, And the substrate comprises a glass substrate. The method of claim 1, Step (a) is (a-1) forming a photoresist pattern exposing the through-hole predetermined region; And (a-2) etching the substrate by performing a sand blasting process using the photoresist pattern as an etching mask Probe card manufacturing method comprising a. The method of claim 1, Step (b) is (b-1) forming a seed layer on the through-hole surface and the second surface of the substrate; (b-2) forming a photoresist pattern for applying the seed layer on the second surface of the substrate; (b-3) performing a plating process to form a metal layer at least filling the through-holes; And (b-4) forming the conductive plug by performing a planarization etching process until the substrate is exposed Probe card manufacturing method comprising a. The method of claim 4, wherein The seed layer is a probe card manufacturing method characterized in that it comprises a Ti / Cu layer. The method of claim 4, wherein The metal layer comprises a Cu layer, characterized in that the probe card manufacturing method. The method of claim 4, wherein The planar etching process includes a probe card manufacturing method comprising a CMP process. The method of claim 1, And forming an upper metal wiring connected to the conductive plug on the second surface of the substrate. The method of claim 1, And forming a lower TEOS film coating the lower metal wiring and the first surface of the substrate. The method of claim 8, And forming an upper TEOS film coating the upper metal wiring and the second surface of the substrate. The method of claim 1, Step (d) (d-1) forming a lower TEOS film pattern having a first opening that exposes a lower metal wiring surface on the conductive plug; (d-2) forming a seed layer on the lower metal wiring surface of the upper portion of the conductive plug exposed through the lower TEOS layer pattern and the first opening; (d-3) forming a first mask layer pattern including a second opening exposing the first opening; (d-4) forming a first conductive bump filling the first opening and the second opening; (d-5) forming a second mask layer pattern including a third opening exposing the first conductive bumps; (d-6) forming a second conductive bump filling the third opening to form the conductive bump having a stack structure of the first and second conductive bumps; And (d-7) removing the second mask layer pattern, the first mask layer pattern, and the seed layer Probe card manufacturing method comprising a. The method of claim 11, And the first and second conductive bumps comprise a Ni—Co layer. The method of claim 12, The Ni-Co layer is a probe card manufacturing method, characterized in that formed by a plating process. The method of claim 11, Step (d-4) is Performing a plating process to form a Ni—Co layer on the first surface; And And forming the first conductive bumps by performing a polishing process until the first mask layer pattern is exposed. The method of claim 11, Step (d-5) is Performing a plating process to form a Ni—Co layer over the entire surface; And And performing a polishing process until the second mask layer is exposed to form the second conductive bumps. The method of claim 9, Probe card further comprising the step of removing the lower TEOS film. The method of claim 10, Probe card further comprising the step of removing the upper TEOS film. The method of claim 1, The adhesive layer is a probe card manufacturing method, characterized in that formed by the screen printing process. The method of claim 1, The adhesive layer is a probe card manufacturing method characterized in that it comprises an AuSn layer. The method according to any one of claims 1 to 8, 10 and 17 to 19, And forming a trench in the first surface of the substrate for the flow of the probe beam. The method of claim 20, Step (d) (d-1) forming a lower TEOS film pattern having a first opening that exposes a lower metal wiring surface on the conductive plug; (d-1) forming a seed layer on the lower metal wiring surface of the upper portion of the conductive plug exposed through the lower TEOS layer pattern and the first opening; (d-1) forming a mask layer pattern including a second opening exposing the first opening; (d-1) forming the conductive bumps filling the first openings and the second openings; (d-1) removing the mask layer pattern and the seed layer. The method of claim 21, And the conductive bump comprises a Ni / Co layer. The method of claim 22, The Ni / Co layer is a probe card manufacturing method, characterized in that formed by a plating process. The method of claim 21, Step (d-4) is Performing a plating process to form a Ni—Co layer on the first surface; And And performing the polishing process until the mask layer pattern is exposed to form the conductive bumps. (a) etching the first substrate to form a trench; (b) etching the substrate to form a through-hole; (c) bonding a second substrate on which a probe beam is formed to the first substrate, wherein the through-hole is aligned with an end of the probe beam; (d) forming a conductive plug to fill the through-hole; And (e) removing the second substrate Probe card manufacturing method comprising a. The method of claim 25, Step (a) is (a-1) forming any one of a polysilicon layer, a metal layer, and a silicon layer on the first and second surfaces of the first substrate; And (a-2) forming the trench by etching the first surface of the first substrate; Probe card manufacturing method comprising a. The method of claim 25, Step (b) is (b-1) forming a photoresist pattern on the second surface of the first substrate to expose the through-hole predetermined region; (b-2) etching the first substrate using the photoresist pattern as an etch mask to form the through-holes Probe card manufacturing method comprising a. The method of claim 27, The etching process of the step (b-2) comprises a sand blasting process or a laser drilling process. The method of claim 26, Probe card further comprising the step of polishing until the first substrate is exposed. The method of claim 25, And forming a seed layer on a surface of the second substrate on which the probe beam is formed before performing step (c). The method of claim 25, Step (c) is a probe card manufacturing method characterized in that it comprises a positive bonding process. The method of claim 25, The step (e) is a probe card manufacturing method, characterized in that performed using KOH or TMAH.

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