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KR100744798B1 - Method of forming a contact plug of a semiconductor device - Google Patents

Method of forming a contact plug of a semiconductor device Download PDF

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KR100744798B1
KR100744798B1 KR1020010088625A KR20010088625A KR100744798B1 KR 100744798 B1 KR100744798 B1 KR 100744798B1 KR 1020010088625 A KR1020010088625 A KR 1020010088625A KR 20010088625 A KR20010088625 A KR 20010088625A KR 100744798 B1 KR100744798 B1 KR 100744798B1
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forming
barrier layer
contact
contact hole
semiconductor device
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KR20030058230A (en
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정종열
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 온도구배를 이용한 반도체 소자의 컨택 플러그 형성 방법에 관한 것이다. 이를 위해, 반도체 소자의 컨택 플러그 형성 방법에 있어서, 기판위에 컨택홀 형성을 위한 패턴을 형성하고, 상기 컨택홀을 포함하는 전체구조 상부에 접합층을 얇은 두께로 형성한다. 상기 접합층 상부에 베리어층을 형성하되, 상기 컨택홀 부위에 형성된 베리어층의 두께는 상부 두께보다 하부 두께가 더 두껍게 형성한 후 상기 베리어층 위에 컨택 형성을 위한 텅스텐막을 증착하게 된다.The present invention relates to a method of forming a contact plug of a semiconductor device using a temperature gradient. To this end, in a method for forming a contact plug of a semiconductor device, a pattern for forming a contact hole is formed on a substrate, and a bonding layer is formed to a thin thickness on the entire structure including the contact hole. A barrier layer is formed on the bonding layer. The thickness of the barrier layer formed on the contact hole is made thicker than the thickness of the upper layer, and then a tungsten film is deposited on the barrier layer.

이에 따라, 온도구배에 의한 컨택홀의 베리어층을 경사지게 형성시켜 결국 텅스텐 증착공정의 마진이 넓어지며, 그에 따라 금속배선공정의 신뢰성을 높이고, 컨택 또는 비아의 저항값을 낮추는 효과가 있다.As a result, the barrier layer of the contact hole due to the temperature gradient is formed obliquely, thereby widening the margin of the tungsten deposition process, thereby increasing the reliability of the metal wiring process and lowering the resistance value of the contact or via.

플러그, 컨택홀, 화학기상증착, 히터블록, 온도구배Plug, contact hole, chemical vapor deposition, heater block, temperature gradient

Description

반도체 소자의 컨택 플러그 형성 방법{Method of forming contact plug for semiconductor devices}[0001] The present invention relates to a method of forming contact plugs for semiconductor devices,

도 1a 내지 도 1e는 종래의 반도체 소자 컨택 플러그 형성 과정을 보여주는 공정 단면도이다.1A to 1E are process cross-sectional views illustrating a conventional semiconductor element contact plug forming process.

도 2는 컨택 플러그 형성을 위한 장비의 예를 보여주는 도면이다.2 is a view showing an example of equipment for forming a contact plug.

도 3a 및 도 3b는 본 발명에 의한 반도체 소자의 컨택 플러그 형성 방법을 설명하기 위한 공정 단면도이다.3A and 3B are process cross-sectional views illustrating a method of forming a contact plug of a semiconductor device according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS

10, 30 : 기판 12, 32 : 절연층10, 30: substrate 12, 32: insulating layer

14, 34 : 접합층 16, 36 : 베리어층14, 34: bonding layer 16, 36: barrier layer

18, 38 : 텅스텐막 100 : 반응챔버18, 38: tungsten film 100: reaction chamber

200 : 웨이퍼 300 : 히터블록200: wafer 300: heater block

400, 500 : 온도조절장치400, 500: Temperature controller

본 발명은 반도체 소자의 컨택 플러그 형성 방법에 관한 것으로, 보다 상세 하게는, 보이드가 발생되지 않는 컨택 플러그를 형성하는 반도체 소자의 컨택 플러그 형성 방법에 관한 것이다.The present invention relates to a method of forming a contact plug of a semiconductor device, and more particularly, to a method of forming a contact plug of a semiconductor device forming a contact plug in which no void is generated.

반도체 소자의 고집적화에 따라 최근 금속배선공정도 점차 다층화되고 미세패턴화 되어가고 있다. 그 결과 금속 배선물질로 알루미늄만을 사용하던 과거의 방법에서 현재는 일반적으로 텅스텐 플러그와 알루미늄 배선을 동시에 사용하는 금속배선 공정이 채택되어 사용되고 있다. 그러나, 패턴이 미세해질수록 종횡비(Aspect Ratio)도 커져서 텅스텐으로 컨택홀을 완전히 채우기는 점점 더 어려워지고 있다.[0003] Along with the high integration of semiconductor devices, the metal wiring process has gradually become multi-layered and fine patterned. As a result, in the past method of using only aluminum as a metal wiring material, a metal wiring process using a tungsten plug and an aluminum wiring at the same time is generally adopted. However, as the pattern becomes finer, the aspect ratio also becomes larger, making it more and more difficult to completely fill the contact hole with tungsten.

그 결과 텅스텐 증착이 불량하게 되면 컨택 플러그에 보이드(Void)가 발생하기도 하며, 텅스텐 증착이 양호하게 되더라도 플러그 중앙에는 키홀(Key Hole)이라고 불리는 작은 보이드가 존재하게 된다. 이러한 현상의 발생원인 중 하나는 텅스텐 증착전 베리어막으로 사용되는 티타늄 나이트라이드(TiN)가 홀 입구에서 오버행(Overhang) 되기 때문이다.As a result, when the tungsten deposition is poor, a void is generated in the contact plug. Even if the tungsten deposition is good, a small void called a key hole exists in the center of the plug. One of the causes of this phenomenon is that titanium nitride (TiN) used as a barrier film before tungsten deposition overhangs at the hole entrance.

이와 같은 종래의 반도체 소자의 컨택 플러그 형성시 보이드가 발생되는 예를 도 1a 내지 도 1e를 참조하여 설명한다.An example in which voids are generated in the formation of the contact plug of such a conventional semiconductor device will be described with reference to FIGS. 1A to 1E.

먼저, 도 1a를 참조하면, 기판 등의 하부막(10) 위에 절연막(12)을 형성한 후 컨택 또는 비아(Via) 형성을 위한 패터닝이 이루어진다. 그 후 도 1b와 같이, 패터닝 후 잔류하는 불순물을 제거하기 위해 고주파 클리닝이 실시된다.First, referring to FIG. 1A, an insulating film 12 is formed on a lower film 10 such as a substrate, and patterning is performed for forming a contact or a via. Then, as shown in FIG. 1B, high-frequency cleaning is performed to remove impurities remaining after patterning.

도 1c는 클리닝 후에 접합층(14)으로 티타늄이 전면에 걸쳐서 얇게 형성된 상태를 보인다. 그리고, 도 1d와 같이, 금속유기 화학기상증착에 의해 티타늄 나이트라이드막(16)이 컨택홀에서의 입구부분과 바닥 부분의 폭(W)이 일정하게 형성된 다.1C shows a state in which titanium is formed thinly over the entire surface of the bonding layer 14 after cleaning. Then, as shown in FIG. 1D, the titanium nitride film 16 is formed to have a constant width W at the entrance portion and the bottom portion of the contact hole by metal organic chemical vapor deposition.

프로파일이 수직적으로 형성되어 있는 상기 티타늄 나이트라이드막(16) 위에 컨택형성을 위한 텅스텐막(18)이 증착되는데, 도 1e를 참조하면, 이때 컨택홀에 보이드(20)가 형성된다.A tungsten film 18 for contact formation is deposited on the titanium nitride film 16 having a vertically formed profile. Referring to FIG. 1E, a void 20 is formed in the contact hole.

이와 같이 종래의 컨택 플러그 형성시 텅스텐 증착불량에 의한 보이드가 발생되어서 그에 따른 불량을 낳게 되고, 원하는 특성을 만족시키지 못하는 소자를 생산하게 되는 문제점이 있다.As described above, voids are formed due to defective tungsten deposition in the formation of the conventional contact plugs, resulting in defects resulting in the production of devices that do not satisfy desired characteristics.

이와 같은 문제점을 해결하기 위한 본 발명의 목적은, 컨택 형성하기 전 베리어층을 컨포멀(Conformal)하게 형성하여 양호한 컨택을 얻기 위한 반도체 소자의 컨택 플러그 형성 방법을 제공하는 것이다.SUMMARY OF THE INVENTION An object of the present invention is to provide a contact plug forming method for forming a barrier layer conformally before forming a contact to obtain a good contact.

본 발명의 다른 목적은, 온도구배에 의한 증착속도의 차이를 이용하여 경사진 컨택홀을 형성하기 위한 반도체 소자의 컨택 플러그 형성 방법을 제공하는 것이다.Another object of the present invention is to provide a method of forming a contact plug of a semiconductor device for forming a slanted contact hole using a difference in deposition rate by a temperature gradient.

상기 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 컨택 플러그 형성 방법은, 반도체 소자의 컨택 플러그 형성 방법에 있어서, 기판위에 컨택홀 형성을 위한 패턴을 형성하는 단계와, 상기 컨택홀을 포함하는 전체구조 상부에 접합층을 얇은 두께로 형성하는 단계와, 상기 접합층 상부에 베리어층을 형성하되, 상기 컨택홀 부위에 형성된 베리어층의 두께는 상부 두께보다 하부 두께를 더 두껍게 형성 시키는 단계, 그리고, 상기 베리어층 위에 컨택 형성을 위한 텅스텐막을 증착하는 단계를 포함하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method for forming a contact plug of a semiconductor device, the method comprising the steps of: forming a pattern for forming a contact hole on a substrate; Forming a barrier layer on the bonding layer, wherein a thickness of the barrier layer formed on the contact hole portion is thicker than a thickness of the lower portion of the barrier layer, And depositing a tungsten film for forming a contact on the barrier layer.

상기 베리어층은 티나늄 나이트라이드(TiN)층이 될 수 있으며, 상기 기판의 온도와 기판 상부의 온도가 다르게 되도록 하여 증착속도의 차이에 의해 증착두께가 조절되도록 하는 것이 바람직하다.The barrier layer may be a titanium nitride (TiN) layer. The thickness of the deposition layer may be adjusted by varying the deposition rate so that the temperature of the substrate is different from the temperature of the substrate.

그리고, 상기 베리어층은 금속유기화학기상증착(MOCVD)에 의해 형성될 수 있다.The barrier layer may be formed by metal organic chemical vapor deposition (MOCVD).

이하, 본 발명의 실시예에 대한 설명은 첨부된 도면을 참조하여 더욱 상세하게 설명한다. 아래에 기재된 본 발명의 실시예는 본 발명의 기술적 사상을 예시적으로 설명하기 위한 것에 불과한 것으로, 본 발명의 권리범위가 여기에 한정되는 것으로 이해되어서는 안될 것이다. 아래의 실시예로부터 다양한 변형, 변경 및 수정이 가능함은 이 분야의 통상의 지식을 가진 자에게 있어서 명백한 것이다.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. The embodiments of the present invention described below are only for illustrative purposes of the technical idea of the present invention and should not be construed as limiting the scope of the present invention. It will be apparent to those skilled in the art that various modifications, changes, and modifications can be made to the embodiments described below.

모든 물질은 가열할 경우 물질 내부에 온도구배(Temperature Gradient)가 발생된다. 즉, 금속유기화학기상증착과 같은 열이 발생되는 화학기상증착 방식에서 온도에 따라 증착속도가 다르다는 특성을 본 발명의 실시예에 적용한다.When all materials are heated, a temperature gradient is created inside the material. That is, the characteristic that the deposition rate varies depending on the temperature in a chemical vapor deposition method in which heat is generated, such as metal organic chemical vapor deposition, is applied to the embodiment of the present invention.

다시 말하면, 웨이퍼의 후면(Backside)과 챔버내의 온도를 다르게 조절함으로써 컨택홀 바닥면에서의 증착속도를 홀 입구보다 더 빠르게 하고, 그 결과 홀 바닥에서부터 증착이 완료되게 함으로써 컨택홀의 프로파일이 수직적으로 형성되던 것을 경사(Slope)가 있는 홀 프로파일을 얻는다. 이로써, 후속공정인 텅스텐 증착시 보이드가 발생되지 않는다. In other words, by varying the temperature of the backside of the wafer and the temperature in the chamber, the deposition rate at the bottom of the contact hole is made faster than the hole entrance, resulting in the deposition being completed from the bottom of the hole, A hole profile with a slope is obtained. As a result, voids are not generated in the subsequent process of tungsten deposition.                     

구체적으로, 도 2를 참조하면, 본 발명의 실시예를 구현하기 위한 증착설비의 예가 도시되어 있다. 반응챔버(100) 내에 웨이퍼(200)가 놓여 있으며, 상기 웨이퍼(200)의 하부에 설치되어 있는 히터블록(300)이 웨이퍼(200)의 온도를 적정수준으로 형성한다. 또한, 반응챔버(100)의 일측에는 아르곤(Ar) 등 비활성가스가 공급되면서 온도를 일정하게 형성하는 온도조절장치(400)가 설치되어 있다. 그리고, 상기 히터블록(300)에도 상기 비활성가스가 공급되어서 온도를 조절하는 온도조절장치(500)가 설치되어 있다. 반응챔버(100)의 상측으로부터 공정수행을 위한 반응가스가 공급되며, 측면 또는 저면에는 진공펌프(도시하지 않음)에 의해 반응챔버(100) 내부의 가스를 배출시키게 된다.Specifically, referring to FIG. 2, there is shown an example of a deposition facility for implementing an embodiment of the present invention. The wafer 200 is placed in the reaction chamber 100 and the heater block 300 provided below the wafer 200 forms the temperature of the wafer 200 at an appropriate level. In addition, a temperature control device 400 is provided at one side of the reaction chamber 100 to form an inert gas such as argon (Ar) at a constant temperature. The heater block 300 is also provided with a temperature controller 500 for controlling the temperature by supplying the inert gas. A reaction gas for performing the process is supplied from the upper side of the reaction chamber 100, and a gas inside the reaction chamber 100 is discharged to the side or bottom by a vacuum pump (not shown).

상기 히터블록(300) 뿐만 아니라 가스나 램프에 의해 온도를 조절하여 온도구배를 형성시킬 수도 있음은 당연한 것이다.It is a matter of course that the temperature gradient can be formed by adjusting the temperature by the gas or the lamp as well as the heater block 300.

이와 같이 구성되어 있는 본 실시예는 반응챔버(100) 내에 있는 웨이퍼의 저면 온도와 반응챔버(100) 내의 온도에 차이를 두어서 웨이퍼(200) 자체의 수직적인 온도분포가 다르게 되도록 하는 온도구배를 형성하는 것이다.In the present embodiment having such a structure, a temperature gradient is formed such that the vertical temperature distribution of the wafer 200 itself is different by making a difference between the bottom surface temperature of the wafer in the reaction chamber 100 and the temperature in the reaction chamber 100 Lt; / RTI >

본 실시예는 종래와 같이 반도체 기판(30)에 절연막(32) 형성과 클리닝 실시 및 접합층(34) 형성 과정은 동일하게 실시된다.In this embodiment, the insulating film 32 is formed on the semiconductor substrate 30, the cleaning is performed, and the bonding layer 34 is formed in the same manner as in the related art.

그리고, 베리어층(36)으로 형성되는 티타늄 나이트라이드막 형성시 상기한 설비의 예와 같이, 웨이퍼에 온도구배가 적용된 막질의 경사진 프로파일을 얻게 된다. 즉, 도 3a를 참조하면, 금속유기 화학기상증착에 의해 형성된 티타늄 나이트라이드막을 볼 수 있다. Then, when forming the titanium nitride film formed of the barrier layer 36, as in the above-mentioned example of the equipment, a film inclined profile with a temperature gradient applied to the wafer is obtained. That is, referring to FIG. 3A, a titanium nitride film formed by metal organic chemical vapor deposition can be seen.                     

컨택홀에 형성된 티타늄 나이트라이드막의 홀의 입구 부분과 바닥 부분의 폭이 서로 다름을 알 수 있다. 이와 같은 차이는 온도구배에 의해 증착되는 속도가 입구와 바닥이 서로 다르기 때문이다. 즉, 웨이퍼(200)의 후면의 온도가 반응챔버(100) 내의 온도보다 더 높게 형성되어 바닥면에서 증착이 먼저 이루어지게 되고, 입구 부분은 더 느리게 형성되는 것이다. 이때 반응챔버(100) 내의 온도가 차이를 보이지 않게 되어 온도구배가 생기지 않게 되면 다시 반응챔버(100)의 온도를 낮추고 히터블록(300)을 통해 웨이퍼(200)를 가열시킨다. 그러면, 상기와 같이 온도구배가 다시 형성되므로 증착을 계속 진행한다. 이와 같은 과정을 반복하게 되면 바닥 부분의 폭(W2)이 입구 부분의 폭(W1)보다 더 작은 베리어층(36)을 형성하게 되는 것이다.It can be seen that the widths of the bottom and inlet portions of the hole of the titanium nitride film formed in the contact hole are different from each other. This difference is due to the fact that the deposition rate by the temperature gradient is different between the inlet and the bottom. That is, the temperature of the rear surface of the wafer 200 is formed to be higher than the temperature in the reaction chamber 100, so that the deposition is first performed on the bottom surface, and the inlet portion is formed more slowly. At this time, if the temperature in the reaction chamber 100 does not show a difference and the temperature gradient is not generated, the temperature of the reaction chamber 100 is lowered again and the wafer 200 is heated through the heater block 300. Then, since the temperature gradient is formed again as described above, the deposition continues. Repeating this process forms the barrier layer 36 having a bottom width W2 smaller than the width W1 of the inlet portion.

이와 같이 형성된 베리어층(36) 위에 텅스텐막(38)을 증착하게 되면, 도 3b와 같이 보이드 등의 불량이 발생되지 않은 컨택 플러그를 형성시킬 수 있는 것이다.When the tungsten film 38 is deposited on the barrier layer 36 thus formed, contact plugs such as voids, which do not cause defects, can be formed as shown in FIG. 3B.

전술한 본 발명의 실시예에 의하면, 티타늄 나이트라이드막 증착 후 컨택홀의 프로파일을 경사진 모양으로 형성시킬 수 있으며, 그에 따라 후속 텅스텐 증착공정의 마진이 넓어지게 하는 이점이 있다. 이는 텅스텐 플러그 형성시 보이드가 없는 플러그를 형성시킬 수 있으며, 금속배선 공정의 신뢰성을 높이는 것은 물론 컨택 또는 비아의 저항치를 낮추게 된다.According to the embodiment of the present invention described above, the profile of the contact hole can be formed in an oblique shape after the deposition of the titanium nitride film, thereby widening the margin of the subsequent tungsten deposition process. This can form void-free plugs in the formation of tungsten plugs, increasing the reliability of metallization processes and lowering the resistance of contacts or vias.

그리고, 계속되는 후속공정인 컨택형성 후 카파(Cu) 접합 공정의 마진이 넓어짐으로써 미세패턴에도 적용하여 큰 효과를 얻을 수 있다.Further, since the margin of the copper (Cu) bonding process after the formation of the contact, which is a succeeding process, is widened, the present invention can be applied to a fine pattern.

따라서, 본 발명에 의하면, 온도구배에 의한 컨택홀의 베리어층을 경사지게 형성시켜 결국 텅스텐 증착공정의 마진이 넓어지는 효과가 있다. 그에 따라 금속배선공정의 신뢰성을 높이며, 컨택 또는 비아의 저항값을 낮추는 효과가 있다.Therefore, according to the present invention, the barrier layer of the contact hole formed by the temperature gradient is inclined so that the margin of the tungsten deposition process is widened. Thereby enhancing the reliability of the metal wiring process and lowering the resistance value of the contact or via.

그리고, 텅스텐 플러그 형성시 보이드가 없는 플러그를 형성시키는 효과가 있다.There is also an effect of forming a void-free plug when forming a tungsten plug.

Claims (4)

삭제delete 삭제delete 반도체 소자의 컨택 플러그 형성 방법에 있어서,A method of forming a contact plug of a semiconductor device, 기판위에 컨택홀 형성을 위한 패턴을 형성하는 단계와;Forming a pattern for forming a contact hole on a substrate; 상기 컨택홀을 포함하는 전체구조 상부에 접합층을 얇은 두께로 형성하는 단계와;Forming a bonding layer on the entire structure including the contact hole to a thin thickness; 상기 접합층 상부에 상기 기판의 온도와 기판 상부의 온도를 다르게 형성하여 증착속도의 차이에 의해 증착두께를 조절하여 베리어층을 형성하되, 상기 컨택홀 부위에 형성된 베리어층의 두께는 상부 두께보다 하부 두께를 더 두껍게 형성시키는 단계; 그리고, Wherein the thickness of the barrier layer formed on the contact hole portion is less than the thickness of the upper portion of the barrier layer, and the thickness of the barrier layer is less than the thickness of the upper portion of the barrier layer. Forming a thicker layer; And, 상기 베리어층 위에 컨택 형성을 위한 텅스텐막을 증착하는 단계;Depositing a tungsten film for forming a contact on the barrier layer; 를 포함하는 것을 특징으로 하는 반도체 소자의 컨택 플러그 형성 방법.≪ / RTI > wherein the step of forming the contact plug comprises: 삭제delete
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JPH02185025A (en) * 1989-01-12 1990-07-19 Agency Of Ind Science & Technol Manufacture of semiconductor device
KR19980017453A (en) * 1996-08-30 1998-06-05 김광호 Formation method of metal wiring layer
JPH10229120A (en) * 1997-02-13 1998-08-25 Sanyo Electric Co Ltd Manufacture of semiconductor device
KR20010109474A (en) * 2000-05-31 2001-12-10 윤종용 Metal wiring method of semiconductor device
JP6036411B2 (en) * 2012-03-08 2016-11-30 Ｊｆｅスチール株式会社 Coal reforming method and coke manufacturing method

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JPH02185025A (en) * 1989-01-12 1990-07-19 Agency Of Ind Science & Technol Manufacture of semiconductor device
KR19980017453A (en) * 1996-08-30 1998-06-05 김광호 Formation method of metal wiring layer
JPH10229120A (en) * 1997-02-13 1998-08-25 Sanyo Electric Co Ltd Manufacture of semiconductor device
KR20010109474A (en) * 2000-05-31 2001-12-10 윤종용 Metal wiring method of semiconductor device
JP6036411B2 (en) * 2012-03-08 2016-11-30 Ｊｆｅスチール株式会社 Coal reforming method and coke manufacturing method

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