KR100742383B1 - Thin Film Transistor and Manufacturing Method Thereof - Google Patents

Abstract

A thin film transistor is provided to reduce driving defects by properly increasing the threshold voltage of a driving thin film transistor in a circuit part. A semiconductor layer(120) in which a polycrystalline silicon layer(121) and an amorphous silicon layer(122) are sequentially stacked is formed on a substrate(100). The amorphous silicon layer can be position on a source/drain region of the polycrystalline silicon layer. A gate insulation layer(130) is positioned on the semiconductor layer. A gate electrode(140) is positioned on the gate insulation layer. An interlayer dielectric(150) is positioned on the gate electrode. A source/drain electrode(161,162) is positioned on the interlayer dielectric. The polycrystalline silicon layer and the amorphous silicon layer can have the same pattern length.

Description

Thin Film Transistor And Method Of Manufacturing Of The Same

1 to 4 are cross-sectional views of a thin film transistor according to a first embodiment of the present invention.

5 to 8 are cross-sectional views of a thin film transistor according to a second embodiment of the present invention.

<Description of Symbols for Major Symbols in Drawings>

100 substrate 110 buffer layer

120 semiconductor layer 121 polycrystalline silicon film

122: amorphous silicon film 130: gate insulating film

140: gate electrode 150: interlayer insulating film

161,162: source / drain electrodes

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a method for manufacturing the same, and more particularly, to a thin film transistor capable of preventing contamination of a polycrystalline silicon film and deterioration of device characteristics.

Recently, a flat panel type such as a liquid crystal display device, an organic electroluminescence device, or a plasma display panel that solves the shortcomings of conventional display devices such as cathode ray tubes. Flat panel display devices are attracting attention.

Since the liquid crystal display is not a light emitting device but a light receiving device, there is a limit in brightness, contrast, viewing angle, and large area, and although the PDP is a light emitting device, it is heavier in weight and consumes more power than other flat panel displays. In addition, there is a problem that the manufacturing method is complicated.

On the other hand, since the organic light emitting display device is a self-luminous element, it is excellent in viewing angle, contrast, etc., and because it does not need a backlight, it is possible to be lightweight and thin, and is advantageous in terms of power consumption. In addition, since it is possible to drive a DC low voltage, fast response speed, and all solid, it is resistant to external shock, wide use temperature range, and has a simple and inexpensive manufacturing method.

In this case, in order to drive or control the organic light emitting display device, a thin film transistor is used as a switching and driving element.

The thin film transistor may include a semiconductor layer including a source region, a channel region, and a drain region, a gate insulating layer positioned on the semiconductor layer, a gate electrode positioned to correspond to the channel region of the semiconductor layer, and the source / And source / drain electrodes respectively in contact with the drain region.

In this case, an ion implantation process is performed to form a source / drain region in a semiconductor layer made of polycrystalline silicon. In an amorphous material, a projection range of ions is always uniformly distributed along a Gaussian distribution, but atoms are regularly arranged. Direct ion implantation into silicon forms tails in a Gaussian distribution curve. This is due to the channeling effect because when the vertically incident ions pass through the channel, the energy loss is very small and the long distance can be moved. As a result, the distribution of ions in the semiconductor layer is irregular, which lowers device characteristics.

Also, in the case of the driving thin film transistor of the circuit part, it is preferable to use a semiconductor layer made of a polycrystalline silicon film to lower the threshold voltage. However, when the threshold voltage becomes very low, it becomes difficult to control on / off, resulting in poor driving of the device. There is a problem.

In addition, in order to form the semiconductor layer, a photoresist is formed and patterned on the polycrystalline silicon film using a photolithography method, which causes a problem that the polycrystalline silicon film contacted by the organic photoresist is contaminated and thus deteriorates the characteristics of the device. This happens.

Accordingly, an object of the present invention is to provide a thin film transistor and a method of manufacturing the same, which solve the above-mentioned disadvantages and problems of the prior art, and which can prevent contamination of a polycrystalline silicon film and deterioration of device characteristics. .

The object of the present invention is a substrate; A semiconductor layer on the substrate, the semiconductor layer in which a polycrystalline silicon film and an amorphous silicon film are sequentially stacked; A gate insulating layer on the semiconductor layer; A gate electrode on the gate insulating layer; An interlayer insulating layer on the gate electrode; And a source / drain electrode positioned on the interlayer insulating film.

In addition, the object of the present invention is to provide a substrate, to form a polycrystalline silicon film on the substrate, to form an amorphous silicon film on the polycrystalline silicon film, and simultaneously etching the polycrystalline silicon film and the amorphous silicon film to form a semiconductor layer And forming a gate insulating film on the semiconductor layer, forming a gate electrode on the gate insulating film, forming an interlayer insulating film on the gate electrode, and forming a source / drain electrode on the interlayer insulating film. It is achieved by the method of manufacturing a thin film transistor.

Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention. In the drawings, the length, thickness, etc. of layers and regions may be exaggerated for convenience. Like numbers refer to like elements throughout.

1 to 4 are cross-sectional views of a thin film transistor according to a first embodiment of the present invention.

Referring to FIG. 1, in the thin film transistor according to the first embodiment of the present invention, the buffer layer 110 is positioned on a substrate 100 made of an insulating glass, a plastic, or a conductive substrate. The buffer layer 110 may be a silicon nitride film, a silicon oxide film, or multiple layers thereof. In addition, the buffer layer 110 may serve to prevent impurities from penetrating upward from the substrate, and may control the rate of crystallization when the amorphous silicon film is crystallized.

The semiconductor layer 120 is positioned on the buffer layer 110. The semiconductor layer 120 has a structure in which a polycrystalline silicon film 121 and an amorphous silicon film 122 are sequentially stacked on the semiconductor layer 120, and the polycrystalline silicon film 121 includes a source / drain region and a channel region. Doing.

In this case, the polycrystalline silicon film 121 and the amorphous silicon film 122 preferably have the same pattern length. This is because the amorphous silicon film 122 is positioned on the polycrystalline silicon film 121, and thus, the polycrystalline silicon film 121 of the semiconductor layer 120 is formed by a reaction effect during an ion implantation process for forming a source / drain region later. The oxygen atoms penetrating into the C) can be prevented from being mostly trapped in the amorphous silicon film 122 and penetrating into the polycrystalline silicon film 121.

In addition, in the case of a circuit driving thin film transistor, the amorphous silicon film 122 is positioned on the channel region of the polycrystalline silicon film 121, thereby providing a higher threshold voltage than the low threshold voltage of the semiconductor layer of the conventional polycrystalline silicon film. Therefore, there is an advantage that it is easy to control the on / off of the thin film transistor. In this case, the amorphous silicon film 122 preferably has a range of 100 to 300 kHz. This is because when the amorphous silicon film 122 is thinner than 100 kV, it is difficult to prevent the recoil effect and the threshold voltage is not generated enough to easily control on / off. This is because energy is needed and the threshold voltage is too high, driving voltage rises.

A gate insulating film 130 formed of a silicon oxide film, a silicon nitride film, or multiple layers thereof is positioned on the semiconductor layer 120, and is positioned at a position corresponding to a partial region of the semiconductor layer 120 on the gate insulating film 130. The gate electrode 140 is located.

In addition, an interlayer insulating layer 150 made of a silicon oxide film, a silicon nitride film, or multiple layers thereof is positioned on the gate electrode 140.

Source / drain electrodes 161 and 162 are disposed on the interlayer insulating layer 150 to contact the source / drain regions of the semiconductor layer 120 through contact holes penetrating through the gate insulating layer 130 and the interlayer insulating layer 150.

Hereinafter, the manufacturing method of the thin film transistor according to the first embodiment of the present invention configured as described above is as follows.

Referring to FIG. 2, a substrate 100 made of insulating glass, plastic, or a conductive substrate is provided. Subsequently, a buffer layer 110 is formed on the substrate 100. The buffer layer 110 may be a silicon oxide film, a silicon nitride film, or multiple layers thereof.

Subsequently, an amorphous silicon film is formed on the substrate 100 on which the buffer layer 110 is formed by using physical vapor deposition or chemical vapor deposition. At this time, since the amorphous silicon film contains a large amount of gases such as hydrogen and thus adversely affects subsequent processes such as a crystallization process, a degassing process such as a dehydrogenation process of removing gases such as hydrogen is performed.

Subsequently, the amorphous silicon film is RTA (Rapid Thermal Annealing), SPC (Solid Phase Crystallization), ELA (Excimer Laser Crystallization), MIC (Metal Induced Crystallization), MILC (Metal Induced Lateral Crystallization) or SLS (Sequential). The polycrystalline silicon film 121 is crystallized by using any one or more of various crystallization methods such as a lateral solidification method.

Subsequently, the amorphous silicon film 122 is formed on the substrate 100 on which the polycrystalline silicon film 121 is formed by using physical vapor deposition or chemical vapor deposition.

3 and 4, the polycrystalline silicon film 121 and the amorphous silicon film 122 are simultaneously etched to form the semiconductor layer 120. In more detail, a photoresist is formed on the amorphous silicon film 122, and the polycrystalline silicon film 121 and the amorphous silicon film 122 are simultaneously etched to form the polycrystalline silicon film 121 and the amorphous silicon film 122. ) Forms a semiconductor layer 120 having the same pattern length.

Subsequently, a photoresist is applied on the amorphous silicon film 122 of the semiconductor layer 120, and an ion implantation process is performed to form source / drain and channel regions of the polycrystalline silicon film 121. Remove the resist. In this case, by performing the ion implantation process directly on the amorphous silicon film 122, there is an advantage that the reaction effect of the oxygen atom can be reliably eliminated and the energy of the ion implanter can be reduced.

Unlike the above, the photoresist is formed to correspond to the channel region of the polycrystalline silicon layer 121 by performing the ion implantation process and considering the electrical contact between the source / drain region and the source / drain electrode. As a result, the amorphous silicon film 122 positioned on the source / drain region may be removed.

As described above, by conventionally patterning the polycrystalline silicon film by the photolithography method, it is possible to prevent the problem that the polycrystalline silicon film is contaminated and to prevent the deterioration of device characteristics.

In addition, in the case of a circuit driving thin film transistor, the amorphous silicon film 122 is positioned on the channel region of the polycrystalline silicon film 121, thereby providing a higher threshold voltage than the low threshold voltage of the semiconductor layer of the conventional polycrystalline silicon film. Therefore, there is an advantage that it is easy to control the on / off of the thin film transistor. In this case, the amorphous silicon film 122 preferably has a range of 100 to 300 kHz. This is because when the amorphous silicon film 122 is thinner than 100 kV, it is difficult to prevent oxygen atoms from penetrating into the polycrystalline silicon film by the reaction effect in the ion implantation process, and the threshold voltage can be easily controlled on / off. This does not occur, and if it is thicker than 300 kW, a large amount of energy is required for ion implantation and the threshold voltage is too high, which causes a problem that the driving voltage is increased.

Subsequently, a gate insulating layer 130 is formed on the semiconductor layer 120. The gate insulating layer 130 may be a silicon oxide layer, a silicon nitride layer, or a multilayer thereof.

Subsequently, the gate electrode 140 is formed on the gate insulating layer 130 at a position corresponding to the partial region of the semiconductor layer 120.

Subsequently, an interlayer insulating layer 150 may be formed on the gate electrode 140, which may be a silicon nitride layer, a silicon oxide layer, or a multilayer thereof.

Subsequently, the interlayer insulating layer 150, the gate insulating layer 130, and the amorphous silicon layer 122 are etched to form contact holes, and a source / drain material is deposited and patterned on the entire surface of the substrate 100 to form the contact holes. The thin film transistor according to the first exemplary embodiment of the present invention is manufactured by forming source / drain electrodes 161 and 162 contacting the source / drain regions of the semiconductor layer 120.

As described above, by forming a semiconductor layer composed of a double layer of a polycrystalline silicon film and an amorphous silicon film, it is possible to prevent contamination by a photosensitive agent during patterning of the polycrystalline silicon film, and to charge the polycrystalline silicon film due to the reaction effect of oxygen atoms in the ion implantation process. The mobility can be prevented from being reduced, and the driving failure can be reduced by appropriately increasing the threshold voltage of the driving thin film transistor of the circuit unit.

5 through 8 are cross-sectional views of a thin film transistor according to a second exemplary embodiment of the present invention.

Referring to FIG. 5, in the thin film transistor according to the second exemplary embodiment of the present invention, a buffer layer 210 is positioned on a substrate 200 made of an insulating glass, a plastic, or a conductive substrate. The buffer layer 210 may be a silicon nitride film, a silicon oxide film, or multiple layers thereof. In addition, the buffer layer 210 may serve to prevent impurities from penetrating upward from the substrate, and may control the rate of crystallization when the amorphous silicon film is crystallized.

The semiconductor layer 220 is positioned on the buffer layer 210. The semiconductor layer 220 has a structure in which a polycrystalline silicon film 221 and an amorphous silicon film 222 are sequentially stacked on the semiconductor layer 220, and the polycrystalline silicon film 221 includes a source / drain region and a channel region. Doing.

In this case, the amorphous silicon film 222 may be located on the source / drain region of the polycrystalline silicon film 221. This is because the amorphous silicon film 222 is positioned on the source / drain region of the polycrystalline silicon film 221, so that the semiconductor layer 220 may be formed by a reaction effect during an ion implantation process to form the source / drain region later. Oxygen atoms that have penetrated into the polycrystalline silicon film 221 can be prevented from being mostly trapped in the amorphous silicon film 222 and penetrated into the polycrystalline silicon film 221.

In this case, the amorphous silicon film 222 preferably has a range of 100 to 300 kHz. This is because when the amorphous silicon film 222 is thinner than 100 mW, it is difficult to prevent the recoil effect, and when thicker than 300 mW, a large amount of energy is required for ion implantation.

A gate insulating film 230 made of a silicon oxide film, a silicon nitride film, or multiple layers thereof is positioned on the semiconductor layer 220, and is positioned at a position corresponding to a partial region of the semiconductor layer 220 on the gate insulating film 230. The gate electrode 240 is located.

In addition, an interlayer insulating layer 250 formed of a silicon oxide film, a silicon nitride film, or multiple layers thereof is positioned on the gate electrode 240.

Source / drain electrodes 261 and 262 are disposed on the interlayer insulating layer 250 to contact the source / drain regions of the semiconductor layer 220 through contact holes penetrating through the gate insulating layer 230 and the interlayer insulating layer 250. .

Hereinafter, the manufacturing method of the thin film transistor according to the second embodiment of the present invention configured as described above is as follows.

6 to 8, a substrate 200 made of insulating glass, plastic, or a conductive substrate is provided. Subsequently, a buffer layer 210 is formed on the substrate 200. The buffer layer 210 may be a silicon oxide film, a silicon nitride film, or a multilayer thereof.

Subsequently, an amorphous silicon film is formed on the substrate 200 on which the buffer layer 210 is formed by using physical vapor deposition or chemical vapor deposition. At this time, since the amorphous silicon film contains a large amount of gases such as hydrogen and thus adversely affects subsequent processes such as a crystallization process, a degassing process such as a dehydrogenation process of removing gases such as hydrogen is performed.

Subsequently, the amorphous silicon film is RTA (Rapid Thermal Annealing), SPC (Solid Phase Crystallization), ELA (Excimer Laser Crystallization), MIC (Metal Induced Crystallization), MILC (Metal Induced Lateral Crystallization) or SLS (Sequential). The polycrystalline silicon film 221 is crystallized by using any one or more of various crystallization methods such as a lateral solidification method.

Subsequently, an amorphous silicon film 222 is formed on the substrate 200 on which the polycrystalline silicon film 221 is formed by using physical vapor deposition or chemical vapor deposition.

Subsequently, the polycrystalline silicon film 221 and the amorphous silicon film 222 are simultaneously etched using a halftone mask to form the semiconductor layer 220. In more detail, a photoresist is formed on the amorphous silicon film 222, and the polycrystalline silicon film 221 and the amorphous silicon film 222 are simultaneously etched with the same pattern length by using a halftone mask, and the polycrystalline The amorphous silicon film 222 is left on the region where the source / drain regions of the silicon film 221 are formed, and the amorphous silicon film 222 of the region where the channel region is formed is removed. Thereby, by conventionally patterning the polycrystalline silicon film by the photolithography method, it is possible to prevent the problem of contaminating the polycrystalline silicon film and to prevent the deterioration of device characteristics.

In this case, the amorphous silicon film 222 preferably has a range of 100 to 300 kHz. When the amorphous silicon film 222 is thinner than 100 mW, it is difficult to prevent oxygen atoms from penetrating into the polycrystalline silicon film by the reaction effect in the ion implantation process, and when the amorphous silicon film 222 is thicker than 300 mW, a lot of energy is required for ion implantation. Because it is necessary.

Subsequently, a gate insulating layer 230 is formed on the semiconductor layer 220. The gate insulating layer 230 may be a silicon oxide layer, a silicon nitride layer, or a multilayer thereof.

Subsequently, the gate electrode 240 is formed on the gate insulating layer 230 at a position corresponding to the partial region of the semiconductor layer 220. Next, an ion implantation process is performed using the gate electrode 240 as a mask to form a source / drain region in the semiconductor layer 220.

Alternatively, before forming the gate insulating film 230, a photoresist is formed at a position where the channel region of the polycrystalline silicon film 221 is formed, and an ion implantation process for forming a source / drain region is performed. In addition, both the amorphous silicon film 222 and the photoresist disposed on the source / drain area of the polycrystalline silicon film 221 may be removed in consideration of the electrical contact between the source / drain area and the source / drain electrode. .

Here, oxygen atoms that have penetrated into the polycrystalline silicon film 221 of the semiconductor layer 220 due to the reaction effect in the ion implantation process are mostly trapped in the amorphous silicon film 222 and penetrate into the polycrystalline silicon film 221. There is an advantage that can be prevented to be prevented to reduce the mobility of the carrier.

Subsequently, an interlayer insulating layer 250 may be formed on the gate electrode 240, which may be a silicon nitride layer, a silicon oxide layer, or a multilayer thereof.

Subsequently, the interlayer insulating layer 250, the gate insulating layer 230, and the amorphous silicon layer 222 are etched to form contact holes, and a source / drain material is deposited and patterned on the entire surface of the substrate 200 to form the contact holes. The thin film transistor according to the second embodiment of the present invention is manufactured by forming source / drain electrodes 261 and 262 in contact with the source / drain regions of the semiconductor layer 220.

As described above, by forming a semiconductor layer composed of a double layer of a polycrystalline silicon film and an amorphous silicon film, it is possible to prevent contamination by a photosensitive agent during patterning of the polycrystalline silicon film, and to charge the polycrystalline silicon film due to the reaction effect of oxygen atoms in the ion implantation process. There is an advantage that can prevent the degradation of mobility.

The present invention has been shown and described with reference to the preferred embodiments as described above, but is not limited to the above embodiments and those skilled in the art without departing from the spirit of the present invention. Various changes and modifications will be possible.

Therefore, the thin film transistor of the present invention and the method of manufacturing the same can prevent the contamination by the photosensitive agent during the patterning of the polycrystalline silicon film, and can prevent the degradation of the charge mobility of the polycrystalline silicon film due to the reaction effect of oxygen atoms during the ion implantation process. In addition, the threshold voltage of the driving thin film transistor of the circuit unit may be appropriately increased to reduce driving failure.

Claims (7)

Board; A semiconductor layer on the substrate, the semiconductor layer in which a polycrystalline silicon film and an amorphous silicon film are sequentially stacked; A gate insulating layer on the semiconductor layer; A gate electrode on the gate insulating layer; An interlayer insulating layer on the gate electrode; And And a source / drain electrode positioned on the interlayer insulating film. The method of claim 1, And the polycrystalline silicon film and the amorphous silicon film have the same pattern length. The method of claim 1, And the amorphous silicon film is positioned on the source / drain region of the polycrystalline silicon film. The method of claim 1, The amorphous silicon film is a thin film transistor, characterized in that the thickness of 100 to 300Å. Providing a substrate, Forming a polycrystalline silicon film on the substrate, Forming an amorphous silicon film on the polycrystalline silicon film, Simultaneously etching the polycrystalline silicon film and the amorphous silicon film to form a semiconductor layer, Forming a gate insulating film on the semiconductor layer, Forming a gate electrode on the gate insulating film, An interlayer insulating film is formed on the gate electrode, A source / drain electrode is formed on the interlayer insulating film. The method of claim 5, The semiconductor layer is a method of manufacturing a thin film transistor using a halftone mask to leave an amorphous silicon film on the source / drain region of the polycrystalline silicon film and to remove the amorphous silicon film on the channel region. The method of claim 6, And the polycrystalline silicon film and the amorphous silicon film are formed to have the same pattern length.

Images