KR100741896B1 - Liquid Crystal Display Panel Manufacturing Method - Google Patents

Abstract

The present invention provides a method for manufacturing a liquid crystal display panel, comprising the steps of: forming a gate wiring, a gate electrode, and a gate pad on a substrate in the manufacture of a liquid crystal display panel divided into an active region and a pad region; Forming a gate insulating film on an entire surface of the substrate including the gate pad; Forming a semiconductor layer on the gate insulating film; Forming a data wiring and a data pad on the gate insulating film and forming a source / drain electrode on the semiconductor layer to form a thin film transistor; Forming a protective film on the entire surface including the source / drain electrodes; Exposing the drain electrode, the gate pad, and the data pad; Plating a conductive material on the exposed gate pads to form a plating film; Forming a transparent conductive film connected to the gate pad and the data pad, and forming a plating film on an Al or Al-based single gate pad to reduce the contact resistance of the conductive film connected to the driving circuit of the LCD panel. Can be used.

Gate pad, metal plating

Description

Liquid crystal display panel manufacturing method {Fabrication Method for Liquid Crystal Display Panel}

1A is a cross-sectional view of a liquid crystal display (LCD) gate pad portion according to the prior art.

1B is a cross-sectional view of an LCD data pad portion according to the prior art.

2A to 2F illustrate a first embodiment of manufacturing an LCD array unit and a pad unit according to the present invention.

3A to 3F illustrate a second embodiment of manufacturing the LCD array unit and the pad unit according to the present invention.

4A is a cross-sectional view of the LCD gate pad portion according to the first and second embodiments.

4B is a sectional view of the LCD data pad portion according to the first and second embodiments;

* Explanation of symbols for main parts of the drawings

101, 201, 301: substrate 102, 202, 302: gate pad

103, 203, 303: gate insulating film 104, 204, 304: protective film

106, 211: data pads 205, 305: semiconductor layer

206, 306: ohmic contact layer 207, 307: source / drain electrodes

208, 308: protective film 209, 309: plating film                 

105, 210, 310: transparent conductive film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to electrode wiring for contact improvement for liquid crystal displays (LCDs), and more particularly to a method for manufacturing a liquid crystal display panel.

In general, an LCD panel may be largely divided into an active region, a pad region, and a grinding region. The active region may include a first substrate having a color filter layer and a common electrode formed thereon, and a plurality of pixels arranged in a matrix. A second substrate having one thin film transistor and one pixel electrode formed therein for each pixel, and a liquid crystal layer formed between the first substrate and the second substrate joined to each other, and the first substrate and the second substrate. Polarizing plates that polarize natural light are attached to both sides of the substrate.

In the second substrate, a gate wiring and a data wiring are cross-formed in a matrix form, and a TFT electrically connected to the pixel electrode is formed in the crossing area. The data pad and the gate respectively extending at the ends of the gate wiring and the data wiring are formed. Each pad electrically interfaces a signal with an external driving circuit.

That is, in order to drive the LCD, the pad is opened and connected to a driving circuit for supplying a driving signal. The data input signal supplied from the driving circuit is separated and transmitted to each pixel according to its own control signal. In this case, the external driving circuit of the LCD and the data wiring or the gate wiring are generally connected in a tap method (TAB: Tape Automated Bonding).

In addition, the grinding region refers to a surface of the finished liquid crystal panel is cut and polished to the desired product size.

Hereinafter, with reference to the accompanying drawings, a pad portion and a method of manufacturing the LCD panel according to the prior art are as follows.

1A is a cross-sectional view of a gate pad portion of an LCD panel according to the prior art, and FIG. 1B is a cross-sectional view of an LCD data pad portion according to the prior art.

As shown in FIG. 1A, the gate pad part forms a gate pad 102 using a metal on the transparent substrate 101, and forms a gate insulating layer 103 on the gate pad 102. At this time, although not shown, the gate pad 102 is formed simultaneously with the gate wiring and the gate electrode of the active region, and the gate insulating film 103 is integrally stacked on the entire surface of the substrate including the gate wiring and the gate electrode.

Next, after the passivation layer 104 is formed on the gate insulation layer 103, the pad is opened by etching the gate insulation layer 103 and the passivation layer 104 to be connected to an external driving circuit.

The transparent conductive film 105 is formed to connect to the gate pad 102 through the open portion, respectively. At this time, the pixel electrodes in the active region are also formed at the same time.

As shown in FIG. 1B, the data pad is integrally formed when the data line and the source / drain electrodes are formed after the semiconductor layer is formed on the gate insulating film formed at the thin film transistor position of the active region. Thus, the data pad 106 is formed over the gate insulating film 103.

Next, after the passivation layer 104 is stacked on the data pad 106, only the passivation layer 104 is etched by a predetermined area so that the data pad 106 is exposed to open the pad.

The transparent conductive film 105 is formed to connect to the data pad 107 through the open portion, respectively.

In this case, the gate / data pads 102/106 form a double pad structure in which other metals (Mo, Cr, Ti, etc.) are deposited on Al or Al-based metals for low resistance wiring, or with Al or Al-based metals. There is a need for an additional process of forming a metal pattern in contact with the pad portion.

The liquid crystal panel formed by the above method is cut into a desired product size through a scribe process and a break process.

However, the liquid crystal display panel manufacturing method according to the related art described above has the following problems.

First, Al or Al-based gate pads are used for low resistance wiring, but contact resistance with conductive films such as ITO is high.

Second, in order to reduce the contact resistance between the pad portion and the conductive film such as ITO, a double pad structure is formed to deposit another metal (Mo, Cr, Ti, etc.) on the Al or Al series, or the pad portion in contact with the Al or Al series metal. There is the hassle of an additional process of forming a metal pattern on.

Accordingly, the present invention has been made to solve the above problems, and provides a liquid crystal display panel manufacturing method for improving the contact resistance problem with a transparent conductive film by performing metal plating on a single pad portion of Al or Al series. There is a purpose.

A liquid crystal display panel manufacturing method according to the present invention for achieving the above object is characterized in that in the manufacturing of a liquid crystal display panel divided into an active region, a pad region, the process of forming a gate wiring, a gate electrode and a gate pad on a substrate ; Forming a gate insulating film on an entire surface of the substrate including the gate pad; Forming a semiconductor layer on the gate insulating film; Forming a data wiring and a data pad on the gate insulating film and forming a source / drain electrode on the semiconductor layer to form a thin film transistor; Forming a protective film on the entire surface including the source / drain electrodes; Exposing the drain electrode, the gate pad, and the data pad; Plating a conductive material on the exposed gate pads to form a plating film; And forming a transparent conductive film connected to the gate pad and the data pad.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

A preferred embodiment of the liquid crystal display panel manufacturing method according to the present invention will be described with reference to the accompanying drawings.

2A to 2F illustrate a first embodiment of manufacturing a liquid crystal display (LCD) array unit and a pad unit according to the present invention.

Although not shown, a plurality of gate lines are arranged in one direction at regular intervals on the substrate 201, and at the same time, the gate electrode 202 is formed on the side of the array as shown in FIG. 2A, and the gate pad is disposed on the side of the gate pad. 203 is formed integrally (only one gate pad is shown for convenience).

The gate wiring, the gate electrode 202 and the gate pad 203 form Al or Al series (AlNd, AlTi, AlTo) as a single gate.

Subsequently, as shown in FIG. 2B, a gate insulating film 204 such as SiN _x is applied to the entire surface including the array portion side and the gate pad portion side. The semiconductor layer 205 and the ohmic contact layer 206 such as n ⁺ a-Si are formed. The gate insulating layer 204, the semiconductor layer 205, and the ohmic contact layer 206 are formed in a low temperature PECVD process of 150 ° C. or less to prevent the gates from being hillocked.

Next, the gate insulating film 204 formed on the gate pad 203 is patterned to expose a predetermined region of the gate pad 203.                     

Subsequently, as shown in FIG. 2C, predetermined regions of the semiconductor layer 205 and the ohmic contact layer 206 formed on the side of the array are selectively etched, a metal film is deposited on the entire surface, and then selectively patterned to form a source / drain electrode. 207 is formed. Although not shown, when the source / drain electrodes 207 are formed, the data pads are integrally formed with a plurality of data lines having a predetermined interval in a direction crossing the respective gate lines.

Subsequently, as shown in FIG. 2D, the passivation layer 208 is formed on the entire surface including the source / drain electrode 207 and then the passivation layer 208 formed on the gate pad part side is removed to remove a predetermined region of the gate pad 203. Expose At this time, although not shown, a contact hole is formed to expose the drain electrode.

In addition, the protective layer 208 formed on the data pad is removed to expose a predetermined area of the data pad.

Subsequently, as illustrated in FIG. 2E, a metal material such as Ni, Ti, Ag, Cu, or the like is plated on the gate pad 203 exposed by the predetermined region to form a plating film 209. In this case, a plated film 209 may be formed on the exposed data pad as necessary.

As shown in FIG. 2F, a transparent conductive film 210 is formed on the gate pad 203 and the data pad so as to be connected to the gate pad 203 and the data pad on which the plating film 209 is formed. At the same time, the transparent conductive film 210 is formed of the pixel electrode on the array side. The transparent conductive film 210 is formed of an oxide and includes ITO, IZO, and the like.

3A to 3F illustrate a second embodiment of manufacturing the LCD array unit and the pad unit according to the present invention.

Although not shown, a plurality of gate lines are arranged in one direction at regular intervals on the substrate, and at the same time, the gate electrode 302 is formed on the array portion side and the gate pad 303 on the gate pad portion side, as shown in FIG. 3A. Is formed integrally (only one gate pad is shown for convenience).

The gate wiring, the gate electrode 302 and the gate pad 303 form Al or Al series (AlNd, AlTi, AlTo) as a single gate.

Subsequently, as shown in FIG. 3B, a gate insulating film 304 such as SiN _x is applied to the entire surface including the array side and the gate pad side, and then, on the formed gate insulating layer 304, a-Si or the like The semiconductor layer 305 and the ohmic contact layer 306, such as n ⁺ a-Si, are formed. The gate insulating layer 304, the semiconductor layer 305, and the ohmic contact layer 306 may be formed in a low temperature PECVD process of 150 ° C. or less to prevent the gate from being hillocked.

Subsequently, as illustrated in FIG. 3C, predetermined regions of the semiconductor layer 305 and the ohmic contact layer 306 formed on the side of the array are selectively etched, and a metal film is deposited on the entire surface, and then selectively patterned to form a source / drain electrode. 307 is formed. Although not shown, when the source / drain electrodes 307 are formed, the data pads are integrally formed with a plurality of data lines having a predetermined interval in a direction crossing the respective gate lines and are integrally formed.

Subsequently, as shown in FIG. 3D, the passivation layer 308 is formed on the entire surface including the source / drain electrode 307, and then the gate insulating layer 304 and the passivation layer 308 formed on the gate pad part side are selectively removed. The predetermined region of the gate pad 303 is exposed. At this time, and although not shown, a contact hole is formed to expose the drain electrode.

In addition, the protective layer 308 formed on the data pad is removed to expose a predetermined area of the data pad.

3E, the plating film 309 is formed by plating a metal material such as Ni, Ti, Ag, and Cu on the gate pad 303 exposed by the predetermined region. At this time, the plating film 309 may be formed on the data pad as necessary.

3F, a transparent conductive layer 310 is formed on the gate pad 303 on which the plating layer 309 is formed and on the gate pad 303 and the data pad so as to be connected to the data pad, respectively. At the same time, the transparent conductive film 310 is formed of the pixel electrode on the array side. The transparent conductive film 210 is formed of an oxide and includes ITO, IZO, and the like.

4A is a cross-sectional view of the gate pad portion of the LCD panel according to the first and second embodiments, and FIG. 4B is a cross-sectional view of the data pad portion according to the present invention.

As described above, although the first and second embodiments have a slight difference in process, the plating process is performed in the exposed area by exposing a predetermined area of the gate pad.

As described above, the liquid crystal display panel manufacturing method according to the present invention reduces the contact resistance of the conductive film connected to the driving circuit of the LCD panel such as ITO without further processing by performing metal plating on the Al or Al series single gate pad. Wiring can be used.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (14)

In manufacturing a liquid crystal display panel divided into an active region and a pad region, Forming a gate wiring, a gate electrode, and a gate pad made of aluminum or an aluminum-based compound on the substrate; Forming a gate insulating film on an entire surface of the substrate including the gate pad; Forming a semiconductor layer on the gate insulating film; Forming a data wiring and a data pad on the gate insulating film and forming a source / drain electrode on the semiconductor layer to form a thin film transistor; Forming a protective film on the entire surface including the source / drain electrodes; Exposing the drain electrode, the gate pad, and the data pad; Forming a plated film by plating silver or copper on the exposed gate pads; And forming a transparent conductive film formed of an oxide electrically connected to the gate pad and the data pad. delete The method of claim 1, wherein at least one of the gate insulating film and the semiconductor layer is formed by a low temperature PECVD process of 15 ° C. or more and 150 ° C. or less. delete The method of claim 1, wherein the oxide is one of ITO and IZO. delete The method of claim 1, wherein the plating layer is further formed on the exposed data pads. In manufacturing a liquid crystal display panel divided into an active region and a pad region, Forming a gate wiring, a gate electrode, and a gate pad made of aluminum or an aluminum-based compound on the substrate; Forming a gate insulating film on an entire surface of the substrate including the gate pad; Forming a semiconductor layer on the gate insulating film; Patterning the gate insulating film to expose a gate pad; Forming a thin film transistor by forming a data line and a data pad on the gate insulating layer and a source / drain electrode on the semiconductor layer; Forming a protective film on the entire surface including the source / drain electrodes; Patterning the passivation layer to expose the drain electrode, the gate pad, and the data pad; Forming a plated film by plating silver or copper on the exposed gate pads; And forming a transparent conductive film formed of an oxide electrically connected to the gate pad and the data pad. delete 10. The method of claim 8, wherein at least one of the gate insulating film and the semiconductor layer is a low temperature PECVD process of 15 ° C or more and 150 ° C or less. delete The method of claim 8, wherein the oxide is one of ITO and IZO. delete The method of claim 8, wherein the plating layer is further formed on the exposed data pads.

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