KR100734809B1 - Method for manufacturing zinc sulfide light emitting device and zinc sulfide light emitting device manufactured thereby - Google Patents

Abstract

The present invention provides a step of preparing a porous silicon substrate, and a p-type semiconductor which is an Al _x In _y Ga _{1 -x- y} N (0≤x, y, x + y≤1) compound semiconductor on the porous silicon substrate. Forming a layer, forming a zinc oxide (ZnO) -based active layer on the p-type semiconductor layer, and forming an n-type zinc sulfide semiconductor layer on the zinc oxide-based active layer Provide a method.

According to the present invention, a lattice mismatch can be reduced by growing a GaN semiconductor layer on a porous silicon substrate, and it is difficult to form a p-type compound due to the material properties of zinc sulfide, and the n-type semiconductor layer is formed of zinc sulfide according to the characteristics of the n-type compound. and forming, with similar material properties and zinc sulfide _{Al x in y Ga 1 -x- y} N (0≤x, y, x + y≤1) for a light-emitting device by forming a p-type compound semiconductor layer of semiconductor material By implementing the pn junction structure it is possible to use the material properties of zinc sulfide in the light emitting device.

Description

METHOD FOR FABRICATING A ZnS BASED LIGHT EMITTING DEVICE AND A ZnS BASED LIGHT EMITTING DEVICE FABRICATED BY THE METHOD

1 is a process flowchart illustrating a manufacturing process of a ZnS-based light emitting device according to an embodiment of the present invention.

2 is a process flow chart for explaining the manufacturing process of the porous silicon substrate used in the ZnS-based light emitting device according to an embodiment of the present invention.

3 to 5 are cross-sectional views of the manufacturing process of FIG. 1.

<Description of the symbols for the main parts of the drawings>

100: porous silicon substrate 200: GaN buffer layer

300: undoped GaN semiconductor layer 400: p-type GaN semiconductor layer

500: ZnO-based active layer 600: n-type ZnS semiconductor layer

700: upper electrode 800: lower electrode

The present invention relates to the production of zinc sulfide (ZnO) -based light emitting device, and in particular, by growing a GaN semiconductor layer on a porous silicon substrate to reduce lattice mismatch, it is difficult to form a p-type compound due to the material properties of zinc sulfide (ZnS) n Pn junction structure for light emitting device by forming n-type semiconductor layer with zinc sulfide (ZnS) and forming p-type semiconductor layer with group III-V compound semiconductor material with similar material properties as ZnS The present invention relates to a method for manufacturing a zinc sulfide-based light emitting device and to a zinc sulfide-based light emitting device manufactured thereby enabling to utilize the material properties of zinc sulfide (ZnS) in the light emitting device.

In general, a light emitting device includes a light emitting diode having a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer interposed between these semiconductor layers. Light is generated by the recombination of electrons and holes in the active layer and emitted to the outside.

Light emitting diodes have developed into a group III-V compound semiconductor. Group III-V compound semiconductors provide superior performance in applications such as high speed and high temperature electronics, light emitters and photo detectors.

In particular, nitride compound semiconductors such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and alloys thereof have been used in III-V group compound semiconductors.

Among nitride compound semiconductors, gallium nitride (GaN) has a bandgap required for a light emitting diode emitting a blue laser and a spectrum having a blue wavelength. Therefore, much research has been conducted on the use of the nitride compound semiconductor.

Zinc sulfide (ZnS) is a representative compound semiconductor material of the II-VI series to replace gallium nitride (GaN). The material properties of zinc sulfide (ZnS) have characteristics similar to those of gallium nitride (GaN), and furthermore, nitrided exciton binding energy, which is a very important factor as a light emitting device, is about 25 meV at room temperature of about 60 meV. Since it appears much higher than gallium (GaN), it is a material having infinite possibilities as a light emitting device.

Because of this, a lot of research has recently been made on light emitting devices using zinc sulfide (ZnS).

However, despite the material properties of zinc sulfide (ZnS) having such an infinite potential, it has not yet achieved such a result as a light emitting device. This is because p-type zinc sulfide (p-ZnS) is very difficult to form due to the inherent material properties of zinc sulfide (ZnS), and thus it is difficult to show characteristics as a light emitting device.

In addition, in the conventional light emitting device, there is a problem in that a lattice mismatch occurs due to a difference between a large thermal expansion coefficient and a lattice constant between the silicon substrate and the GaN semiconductor layer by growing the GaN semiconductor layer on the silicon substrate.

The technical problem to be achieved by the present invention is to reduce the lattice mismatch due to heterojunction between the GaN semiconductor layer and the substrate, and to have a light emitting device having a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer interposed between these semiconductor layers. The application of zinc sulfide to the manufacture of a light emitting device having improved performance by the properties of zinc sulfide.

According to an aspect of the present invention for achieving the technical problem, a step of preparing a porous silicon substrate, and Al _x In _y Ga _{1 -xy} N (0≤x, y, x + on the porous silicon substrate) y≤1) forming a p-type semiconductor layer which is a compound semiconductor, forming a zinc oxide (ZnO) active layer on the p-type semiconductor layer, and forming an n-type zinc sulfide semiconductor layer on the zinc oxide-based active layer It provides a method of manufacturing a zinc sulfide-based light emitting device comprising the step of.

The n-type zinc sulfide semiconductor layer may be doped with Pb and Cu in zinc sulfide.

Etching a portion of the n-type zinc sulfide semiconductor layer, a zinc oxide-based active layer, and a p-type semiconductor layer to expose a portion of the p-type semiconductor layer, and to the n-type zinc sulfide semiconductor layer and the exposed p-type semiconductor layer Forming an electrode may be further included.

The method may further include forming an Al _x Ga _{1- x} N (0 ≦ _x ≦ ₁ ) buffer layer between the porous silicon substrate and the p-type semiconductor layer.

Preferably the step of forming the buffer layer and the p-type semiconductor layer between the _{Al x In y Ga 1 -x- y} N (0≤x, y, x + y≤1) based buffer layer may be further included.

Preferably, the forming of the zinc oxide-based active layer may include a binary to quaternary compound semiconductor layer represented by general formula Zn _x Mg _y Cd _{1-x- y} O (0 ≦ x, y, x + y ≦ 1). The quantum well layer and the barrier layer may be repeatedly stacked to form a multilayer film.

According to still another aspect of the present invention, the porous silicon (porous silicon) substrate, the porous _{Al x In y Ga 1 -x- y} N (0≤x, y, x + y≤1) semiconductor compound on a silicon substrate, A zinc sulfide type light emitting device comprising a p type semiconductor layer, a zinc oxide (ZnO) based active layer formed on the p type semiconductor layer, and an n type zinc sulfide semiconductor layer formed on the zinc oxide based active layer.

The n-type zinc sulfide semiconductor layer may be doped with Pb and Cu in zinc sulfide.

The zinc sulfide-based light emitting device is exposed by etching the portion of the n-type zinc sulfide semiconductor layer, the zinc oxide-based active layer, and the p-type semiconductor layer to expose the n-type zinc sulfide semiconductor layer and a portion of the p-type semiconductor layer. It may further include an electrode formed on the p-type semiconductor layer.

The zinc sulfide based light emitting device may further include an (Al _x In _y Ga _{1 −x− y} N (0 ≦ x, y, x + y ≦ 1) based buffer layer between the porous silicon substrate and the p-type semiconductor layer. Can be.

The zinc sulfide light emitting device may further include an (Al _x In _y Ga _1-xy N (0 ≦ x, y, x + y ≦ 1) based undoped semiconductor layer between the buffer layer and the p-type semiconductor layer. have.

The zinc oxide based active layer has the general formula _{Zn x Mg y Cd 1 -x- y} O (0≤x, y, x + y≤1) 2 -to 4 won compound quantum well layer of the semiconductor layer and a barrier which is represented by The layer is a multilayer film formed by laminating repeatedly.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided as examples to sufficiently convey the spirit of the present invention to those skilled in the art.

Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. In the drawings, lengths, thicknesses, and the like of layers and regions may be exaggerated for convenience. Like numbers refer to like elements throughout.

1 is a process flow chart illustrating a manufacturing process of a ZnS-based light emitting device according to an embodiment of the present invention, Figure 2 is a manufacturing process of a porous silicon substrate used in the ZnS-based light emitting device according to an embodiment of the present invention 3 to 5 are process cross-sectional views according to the manufacturing process thereof. Here, the manufacturing process of the light emitting element using the semiconductor layer which consists of nitride and zinc sulfide among light emitting elements is demonstrated.

1 and 3, a porous Si substrate 100 is prepared in a process chamber (not shown) for forming nitride and zinc oxide (ZnO) and zinc sulfide (ZnS) semiconductor layers ( S1). The porous silicon substrate 100 has a lattice constant similar to that of the nitride semiconductor layer to be formed thereon.

In order to manufacture a porous silicon substrate, a non-porous silicon substrate is prepared as shown in FIG. 2 (S11). As the non-porous silicon substrate, a P-type Si substrate having a (100) planar orientation is used. In addition, the non-porous silicon substrate is cleaned with a cleaning solution comprising Trichloroethylane (T.C.E), acetone and methanol and then prepared for the next step. At this time, in order to obtain a sufficient cleaning effect, the non-porous silicon substrate is held for about 10 minutes in a cleaning liquid at a temperature of approximately 120 ° C.

Next, a KOH etching process is performed as a previous step for forming a porous on the non-porous silicon substrate (S12). In this embodiment, the KOH etching is performed by immersing the non-porous silicon substrate in order of 1 minute each in electrolyzers containing 1.5 mole, 3 mol, and 5 mol of potassium hydroxide solution, wherein the temperature of the potassium hydroxide solution is about Maintained at 75 ° C.

By the KOH etching process as described above, a rough surface having a roughly pyramid shape is formed on the surface of the non-porous silicon substrate, which serves to define a porous site of the porous silicon substrate. The porous silicon substrate to be produced has a uniform and dense porous.

Thereafter, a process of forming an anode electrode on the non-porous silicon substrate is performed (S13). This process is for forming an electrode for applying power to the non-porous silicon substrate in a subsequent process. Aluminum (Al) is formed by depositing on one surface of the non-porous silicon substrate. In addition, the non-porous silicon substrate on which the anode electrode is formed may be heat treated at a temperature of about 400 ° C. for 1 minute.

Finally, a process of forming a non-porous silicon substrate into a porous silicon substrate by anodization is performed (S14). In this step, a solution in which a 50 wt% HF solution and ethanol (C ₂ H ₅ OH) is mixed at a ratio of 1.5: 1 is used as the electrolyte. Use a Teflon beaker that can withstand the HF solution to hold the electrolyte. At this time, ethanol helps to form a uniform pore in the silicon substrate by minimizing the generation of hydrogen bubbles during anodization. When the electrolyte is prepared, the non-porous silicon substrate prepared from the above steps is placed in the electrolyzer filled with the electrolyte, and then the non-porous silicon substrate is used as the anode and the metal such as platinum (Pt) is used as the cathode. Flow the current. As a result, an anodization reaction takes place actively in the electrolyte, thereby forming a porous silicon substrate having a myriad of porous on the surface of the substrate.

A 50 W halogen lamp is used to actively anodic oxidation in the electrolyte, and basically minimizes the influence of external light.

A process of heat-treating the porous silicon substrate subjected to the above process at a temperature of approximately 400 to 700 ° C. for about 30 minutes may be additionally performed, and this heat treatment process is to provide thermal stability to the porous silicon substrate.

Although the manufacturing process of the porous silicon substrate has been described as an example, it is also possible to manufacture the porous silicon substrate by different methods or conditions from the above.

Thereafter, a GaN buffer layer 200 is formed on the porous silicon substrate 100 (S2).

The GaN buffer layer 200 is used to mitigate the lattice mismatch between the semiconductor layers to be formed thereon and the porous silicon substrate 100. The GaN buffer layer 200 may be grown to a thickness of 20 nm to 50 nm at a low temperature, for example, at a temperature of about 400 to about 700 ° C. and a pressure of 50 Torr to 700 Torr.

Thereafter, an undoped GaN semiconductor layer 300 is formed on the GaN buffer layer 200 (S3).

The undoped GaN semiconductor layer 300 is interposed between the GaN buffer layer 200 and the p-type GaN semiconductor layer 400 and is made of undoped GaN.

The undoped GaN semiconductor layer 300 is intended to effectively form a high-quality p-type GaN semiconductor layer 400 made of a GaN-based material thereon.

The GaN buffer layer 200 and the undoped GaN semiconductor layer 300 may include metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), or molecular beam growth (molecular beam). epitaxy, MBE) and the like.

The p-type GaN semiconductor layer 400, the ZnO-based active layer 500, and the n-type ZnO semiconductor layer 600 are sequentially formed on the undoped GaN semiconductor layer 300 (S4).

The p-type GaN semiconductor layer 400 may be formed by doping magnesium (Mg) or zinc (Zn), and may include a p-type cladding layer.

The ZnO-based active layer 500 is a region where electrons and holes are recombined, and includes ZnMgO or ZnCdO. The emission wavelength emitted from the light emitting diode is determined according to the type of material constituting the ZnO-based active layer 500.

That is, ZnO-based active layer 500 is magnesium because it can be controlled with the addition of Zn ^{2 +} ions with a radius of magnesium (Mg) or cadmium (Cd), etc. Similar to zinc oxide (ZnO) to the band gap 2.8eV to 4eV The desired emission wavelength can be determined by adjusting the mole fraction of (Mg) or cadmium (Cd).

That is, as the content of magnesium (Mg) increases, the band gap energy increases, and as the content of cadmium (Cd) increases, the band gap energy decreases. Accordingly, like GaN-based light emitting devices, light of various wavelengths may be generated from ultraviolet rays to infrared rays.

The ZnO-based active layer 500 may be a multilayer film in which a quantum well layer and a barrier layer are repeatedly formed. The barrier layer and the well layer may be binary to quaternary compound semiconductor layers represented by the general formula Zn _x Mg _y Cd _1-xy O (0 ≦ x, y, x + y ≦ 1).

Specifically, zinc oxide (ZnO) and zinc oxide (Zn _{1 - x} Mg _x O (0 ≦ _x ≦ ₁₎ capable of adjusting a band gap by adding magnesium (Mg) or cadmium (Cd) to zinc oxide (ZnO) and zinc oxide (ZnO). ) Or zinc cadmium oxide (Zn _{1 - x} Cd _x O (0 ≦ _x ≦ 1)) may be alternately stacked to form a barrier layer and a well layer of the ZnO-based active layer 500.

For this purpose, dimethyl zinc [Zn (CH ₃ ) ₂ ], an organic metal containing zinc as a reaction precursor, and bis-cyclopentadienyl magnesium (bis-cyclopentadienyl-Mg; (C ₅ H ₅ )) ₂ Mg) and oxygen (O ₂ ) gas, and argon is used as a transport gas.

Argon, which transports diethylzinc and biscyclopentadienyl magnesium, through separate lines, and O ₂ , are appropriately controlled and deposited alternately by organometallic chemical vapor deposition without a metal catalyst.

Preferred pressures and temperatures in the reactor for deposition are 10 ⁻⁵ mmHg to 760 mmHg and 400 to 700 ° C., respectively. After growing zinc oxide (ZnO), zinc magnesium / zinc oxide is grown by appropriately changing the flow of precursors, diethyl zinc and biscyclopentadienyl magnesium, from the exhaust line to the reactor. The magnesium content of zinc magnesium oxide is 12 at.% (Atomic percent).

The n-type ZnS semiconductor layer 600 is formed on the ZnO-based active layer 500 by organometallic chemical vapor deposition without using a metal catalyst.

Specifically, the n-type ZnS semiconductor layer 600 injects zinc-containing organic metal and sulfur-containing gas or sulfur-containing organic material through separate lines into the reactor in which the ZnO-based active layer 500 is formed. It is formed on the ZnO-based active layer 500 by organometallic chemical vapor deposition which chemically reacts the precursors of the reactants under a pressure of 10 torr and a reaction condition of 400 to 700 ° C.

Zinc-containing organic metals used for the deposition of the n-type ZnS semiconductor layer 600 include dimethyl zinc [Zn (CH ₃ ) ₂ ], diethyl zinc [ZnC ₂ H ₅ ) ₂ ], and zinc acetate [Zn (OOCCH _{3). 2} ) H ₂ O], zinc acetate anhydride [Zn (OOCCH ₃ ) ₂ ], zinc acetylacetonate [Zn (C ₅ H ₇ O ₂ ) ₂ ], and the like. For example, H ₂ S).

At this time, Pb and Cu are doped together in ZnS. ZnS co-doped with Pb ^{2 +} and Cu ^{2 +} may be generated together. ZnS, Pb, Cu The doping of is very useful in improving the optical properties of ZnS at room temperature and the fluorescence intensity can be controlled by controlling the relative doping amount of Pb and Cu.

Cu, Pb doped ZnS has an emission peak in the range of approximately 500 to 550 μm and has a relatively broad emission band.

1 and 4, a portion of the n-type ZnS semiconductor layer 600, the ZnO-based active layer 500, and the p-type GaN semiconductor layer 400 in a state where the n-type ZnS semiconductor layer 600 is formed. By etching, a portion of the p-type GaN semiconductor layer 400 is exposed (S5).

1 and 5, upper and lower electrodes 700 and 800 are formed in the n-type ZnS semiconductor layer 600 and the exposed p-type GaN semiconductor layer 400, respectively (S6).

The upper electrode 700 is formed by sequentially depositing titanium (Ti) (10 nm) and gold (Au) (50 nm) using, for example, heat or electron beam evaporation.

The lower electrode 800 is formed by sequentially depositing platinum (Pt) (10 nm) and gold (Au) (50 nm) on the p-type GaN semiconductor layer 400 by heat or electron beam evaporation.

In the manufacture of the upper and lower electrodes 700 and 800, the acceleration voltage and emission current of the electron beam for metal evaporation are 4 to 20 mA and 40 to 400 mA, respectively, and the pressure of the reactor is about 10 ^-5 mmHg when the metal is deposited. The temperature in the reactor was kept at room temperature.

The present invention is not limited to the above described embodiments, and various modifications and changes can be made by those skilled in the art, which are included in the spirit and scope of the present invention as defined in the appended claims.

For example, in an embodiment of the present invention, the use of gallium nitride (GaN) in a III-V group compound semiconductor as a p-type semiconductor layer corresponding to an n-type ZnO semiconductor layer for manufacturing a light emitting device using zinc sulfide is described. It was.

However, in addition to gallium nitride (GaN), various nitride compound semiconductors such as aluminum nitride (AlN), indium nitride (InN), and alloys thereof may be used as p-type semiconductor layers for manufacturing light emitting devices using zinc sulfide. _{Al x in y Ga 1 -x- y} N may be used (0≤x, y, x + y≤1 ). in addition may be used a Group III-V compound semiconductor of GaP and GaAs.

In addition, group II-VI compound semiconductors such as ZnSe, CdSe, CdS and ZnS, semiconductors such as SrCu ₂ O ₂ , SiC, and Si, and the like can be used and these can be easily purchased commercially.

In addition, in an embodiment of the present invention, the use of a gallium nitride (GaN) buffer layer and an undoped layer for manufacturing a light emitting device using zinc sulfide has been described.

However, in addition to gallium nitride (GaN), various nitride compound semiconductors such as aluminum nitride (AlN), indium nitride (InN), and alloys thereof may be used as buffer layers and undoped layers for manufacturing light emitting devices using zinc sulfide. (it may be the _{Al x In y Ga 1 -x- y} N (0≤x, y, x + y≤1).

In addition, in one embodiment of the present invention, zinc sulfide was deposited by an organic chemical vapor deposition method without using a metal catalyst, but also by physical growth methods such as sputtering or pulsed laser deposition, and the like, such as gold (Au) It is also possible by a vapor-phase transport process using a catalyst.

In an embodiment of the present invention, the n-type zinc sulfide semiconductor layer, the zinc oxide-based active layer, and the p-type semiconductor layer are etched to expose a portion of the p-type semiconductor layer, and then a lower electrode is formed on the exposed p-type semiconductor layer. The zinc oxide light emitting device fabricated as described above has been described, but the vertical type of forming a lower electrode on the p-type semiconductor layer after separating the substrate without etching the n-type zinc sulfide semiconductor layer, the zinc oxide-based active layer, and the p-type semiconductor layer. It is also applicable to a light emitting element.

In the zinc sulfide based light emitting device according to the present invention, an Al _x In _y Ga _1-xy N (0 ≦ x, y, x + y ≦ 1) semiconductor layer is formed on a porous silicon substrate. _{Al x In y Ga 1 -x- y} N by a substrate for growing a semiconductor layer using a porous silicon substrate _{Al x In y Ga 1 -x- y} N is an effective way of reducing the lattice mismatch between the semiconductor layer and the porous silicon substrate have.

Further, in the zinc oxide based light-emitting device according to the present invention, magnesium (Mg) is a p-type Al _x In _y Ga _{1 -x- y} doped N semiconductor layer and, as the active layer and the n-type ZnS semiconductor layer of the ZnO-base turn Is formed.

Due to the material properties of zinc sulfide (ZnS), it is difficult to form a p-type compound and exhibits the characteristics of the n-type compound, thereby forming an n-type semiconductor layer with zinc sulfide (ZnS), and Al _x having a material characteristic similar to that of zinc sulfide (ZnS). By forming a p-type semiconductor layer with In _y Ga _{1 -x- y} N, the pn junction structure for the light emitting device can be realized, thereby enabling the use of material properties of zinc sulfide (ZnS) in the light emitting device.

In addition, the ZnO-based active layer alternately forms a layer doped with magnesium or cadmium in zinc oxide (ZnO) and zinc oxide (ZnO) to form a quantum well layer and a barrier layer repeatedly, thereby controlling the mole fraction of magnesium and cadmium. It can generate light of various wavelengths from to infrared.

Further, in the pn junction structure implemented by the present invention, an n-type ZnS semiconductor layer is formed on the uppermost layer. Due to the characteristics of the n-type ZnS, the n-type ZnO formed on the uppermost layer of the GaN-based light emitting device can exhibit high brightness light emitting device characteristics by not only acting as an electron injection layer but also by depositing pad metal without a separate conductive film.

Claims (12)

Preparing a porous silicon substrate, Forming a p-type semiconductor layer of Al _x In _y Ga _{1 -x- y} N (0 ≦ x, y, x + y ≦ 1) compound semiconductor material on the porous silicon substrate; Forming a zinc oxide (ZnO) -based active layer on the p-type semiconductor layer; Forming an n-type zinc sulfide semiconductor layer on the zinc oxide-based active layer. The method of claim 1, wherein the n-type zinc sulfide semiconductor layer is formed of zinc sulfide-based light emitting device in which Pb and Cu are doped in zinc sulfide. The method according to claim 1, Etching a portion of the n-type zinc sulfide semiconductor layer, a zinc oxide-based active layer, and a p-type semiconductor layer to expose a portion of the p-type semiconductor layer; And forming an electrode on the n-type zinc sulfide semiconductor layer and the exposed p-type semiconductor layer. The method according to claim 1, _Zinc sulfide emission further comprising forming an Al _x In _y Ga _{1- x- y} N (0 ≦ x, y, x + y ≦ 1) buffer layer between the porous silicon substrate and the p-type semiconductor layer Method of manufacturing the device. The method according to claim 4, _Zinc sulfide type further comprising forming an Al _x In _y Ga _{1 -x- y} N (0≤x, y, x + y≤1) based undoped semiconductor layer between the buffer layer and the p-type semiconductor layer Method of manufacturing a light emitting device. The method of claim 1, wherein the forming of the zinc oxide based active layer, The multilayer film is formed by repeatedly stacking the quantum well layer and the barrier layer of the binary to quaternary compound semiconductor layer represented by the general formula Zn _x Mg _y Cd _{1 -x- y} O (0≤x, y, x + y≤1). A method of manufacturing a zinc sulfide light emitting device, characterized in that to form a. A porous silicon substrate, A p-type semiconductor layer of Al _x In _y Ga _{1 -x- y} N (0 ≦ x, y, x + y ≦ 1) compound semiconductor material on the porous silicon substrate; A zinc oxide (ZnO) -based active layer formed on the p-type semiconductor layer, Zinc sulfide-based light emitting device comprising an n-type zinc sulfide semiconductor layer formed on the zinc oxide-based active layer. The zinc sulfide type light emitting device according to claim 7, wherein the n-type zinc sulfide semiconductor layer is doped with Pb and Cu in zinc sulfide. The method according to claim 7, A portion of the n-type zinc sulfide semiconductor layer, a zinc oxide-based active layer, and a p-type semiconductor layer is etched to be formed on the n-type zinc sulfide semiconductor layer and the exposed p-type semiconductor layer in a state where a portion of the p-type semiconductor layer is exposed. Zinc sulfide light emitting device further comprising an electrode. The method according to claim 7, Sulfide zinc-based light-emitting device between the porous silicon substrate and the p-type semiconductor layer including a buffer layer based _{Al x In y Ga 1 -x- y} N (0≤x, y, x + y≤1) more. The method according to claim 10, Sulfide zinc-based light-emitting device further comprises a buffer layer and the p-type semiconductor layer between the _{Al x In y Ga 1 -x- y} N (0≤x, y, x + y≤1) type undoped conductive semiconductor layer. The method according to claim 7, wherein the zinc oxide active layer, A quantum well layer and a barrier layer of a binary to quaternary compound semiconductor layer represented by general formula Zn _x Mg _y Cd _{1 -x- y} O (0≤x, y, x + y≤1) are repeatedly stacked. Zinc sulfide light emitting device, characterized in that the multilayer film.

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