KR100732762B1 - Test pattern of semiconductor device having recess gate and manufacturing method thereof - Google Patents

Abstract

The test pattern of the semiconductor device having the recess gate according to the present invention includes a change in the threshold voltage of each of the first transistor disposed in the first active region and the second transistor disposed in the second active region adjacent to the first active region. In the test pattern of the semiconductor device for detecting the semiconductor device, the first test region and the second test region around the first and second active regions, respectively, having the same structure as the first transistor and the second transistor, respectively; A first test pattern and a second test pattern are provided, and the bit line contact region of the first test pattern and the bit line contact region of the second test pattern are electrically connected to each other.

Recess gate, overlay, misalignment, threshold voltage, test pattern

Description

Test pattern in semiconductor device having recess gate and method of fabricating the same}

1 is a graph illustrating changes in cell threshold voltage and drain current according to misalignment.

FIG. 2 is a graph illustrating a change in leakage time at a refresh node and a storage node according to misalignment.

3 is a layout illustrating a test pattern of a semiconductor device having a recess gate according to the present invention.

4 is an equivalent circuit diagram of the test pattern of FIG. 3.

5 is a view illustrating a layout design of the test pattern of FIG. 3.

6 to 11 are layout diagrams shown to explain a method of manufacturing a test pattern according to the present invention.

The present invention relates to a test pattern for detecting a change in the threshold voltage of a cell in a semiconductor device having a recess gate and a method of manufacturing the same.

Recently, as the degree of integration of integrated circuit semiconductor devices has increased and design rules have sharply decreased, it is increasingly difficult to secure stable operation of transistors. For example, the shortening of transistors is rapidly progressing due to the decrease in the width of the gate, and thus short channel effects are frequently generated. Due to the short channel effect, punch-through between the source and the drain of the transistor is seriously generated, which is recognized as a major cause of malfunction of the device. Therefore, in order to overcome the short channel effect, various methods for securing channel lengths without increasing design rules have been studied in various ways. In particular, as a structure for extending the channel length for a limited gate line width, a semiconductor device having a recess gate structure that extends the channel length by recessing the semiconductor substrate under the gate has been in the spotlight.

A semiconductor device having a recess gate structure is typically arranged such that a plurality of active regions defined by an isolation layer are spaced apart from each other, and each active region has a structure overlapping two gate lines. Accordingly, two transistors are disposed in each active region. In forming a semiconductor device having such a recessed gate structure, misalignment may occur due to inconsistency of an overlay, and the threshold voltage of the transistor may be changed by this misalignment. have. The threshold voltage of the transistor is a factor that has an important effect on the operation characteristics of the device. It is necessary to accurately detect such a change in the threshold voltage so that the device can operate normally regardless of the change in the threshold voltage. .

1 is a graph illustrating changes in cell threshold voltage and drain current according to misalignment. FIG. 2 is a graph showing changes in leakage time at the refresh node and the storage node according to misalignments.

Referring first to FIG. 1, the cell threshold voltage CVT increases as the misalignment is biased toward the bit line, that is, as the misalignment has a + value in the graph (see 110), while the drain voltage Id is Decrease (see 120). Conversely, the cell threshold voltage CVT decreases (see 110) while the misalignment is biased toward the storage node, i.e., the misalignment has a negative value in the graph (see 110), while the drain voltage (Id) increases (see 120). . This increases the potential of n-type impurity ions and the increase of n-resistance due to the effect of cell-halo counter doping when the misalignment increases toward the storage node. Because.

Referring next to FIG. 2, the refresh time tREF increases as the misalignment is biased toward the bitline, i.e., the misalignment has a positive value in the graph (see 210), while the leakage current at the storage node is increased. (S-Lka) decreases (see 220). Conversely, as the misalignment is biased toward the storage node, i.e., the misalignment has a negative value in the graph, the refresh time (tREF) decreases (see 210), while the leakage current (S-Lka) on the storage node increases. (See 220).

Conventionally, in order to detect a change in the threshold voltage of a semiconductor device having a recess gate structure, a test pattern identical to the device pattern of the active region is disposed around the active region. That is, the change of the threshold voltage was detected by measuring the threshold voltage after connecting the test pattern with an external terminal. However, in detecting the change of the threshold voltage by using the test pattern, the detection of the transistors in each active region is performed separately. Accordingly, the detection time becomes longer due to the increase in the number of tests for detection. There is a problem that it is difficult to accurately compare the threshold voltage changes with each other.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a test pattern of a semiconductor device having a recess gate capable of accurately detecting a change in a threshold voltage caused by a misalignment with respect to two transistors through a single test.

Another object of the present invention is to provide a method of manufacturing the test pattern.

In order to achieve the above technical problem, a test pattern of a semiconductor device having a recess gate according to the present invention includes a first transistor disposed in a first active region and a second active region disposed in a second active region adjacent to the first active region. A test pattern of a semiconductor device for detecting a change in the threshold voltage of each of the two transistors, the first test region and the second test region surrounding the first and second active regions, the first transistor and the second transistor; Each of the first and second test patterns has the same structure and is disposed, and the bit line contact region of the first test pattern and the bit line contact region of the second test pattern are electrically connected to each other. It is done.

The first test pattern and the second test pattern may include: first and second recess gates each having a stripe shape passing through the first area and the second area in the test area; First and second bit line contacts connected to the bit line contact region in the first region and the bit line contact region in the second region; And a bit line having a stripe shape connected to the first and second bit line contacts and intersecting the first and second recess gates.

The first recess gate and the second recess gate may be commonly connected to an external terminal through the same metal line.

It is preferable that the said 1st area | region and the 2nd area | region are grooved type.

In order to achieve the above technical problem, a method of manufacturing a test pattern of a semiconductor device having a recess gate according to the present invention includes a first transistor disposed in a first active region and a second active adjacent to the first active region. A method of manufacturing a test pattern of a semiconductor device having a recess gate for detecting a change in threshold voltage of each second transistor disposed in a region, the method comprising: a first region and a second region defined by an isolation region on a substrate Forming a; Forming a trench for a first recess gate and a trench for a second recess gate crossing the first region and the second region; Forming a first recess gate and a second recess gate in a stripe form to fill the trench for the first recess gate and the trench for the second recess gate; Forming first and second bit line contacts in contact with first and second bit line contact regions of the substrate defined by the first recess gate and the second recess gate; And forming a stripe-shaped bit line connected to the first and second bit line contacts while crossing the first recess gate and the second recess gate.

The forming of the first region and the second region may include a mask including a light transmission region corresponding to the device isolation region, and a light blocking pattern corresponding to the first region and the second region and having a groove shape. It is preferable to carry out.

In the present invention, the method may further include connecting the first recess gate and the second recess gate with the same wiring.

In this case, a first external terminal connected to the wiring, a second external terminal connected to the bit line, a third external terminal connected to the storage node region of the first region, and a storage node region of the second region The method may further include forming a fourth external terminal connected to the first external terminal and a fifth external terminal connected to the substrate.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.

3 is a layout illustrating a test pattern of a semiconductor device having a recess gate according to the present invention.

Referring to FIG. 3, a semiconductor device according to the present invention may include a first transistor and a second transistor disposed in a first active region and a second active region, and a test pattern region around the first and second active regions, respectively. The first test pattern 300 and the second test pattern 400 are disposed. Two gate lines (word lines) pass through each active region, and impurity regions are disposed in three regions divided by two gate lines. Two impurity regions disposed on both sides of the two gate lines, i.e., disposed at both ends of the active region, respectively become storage node contact regions of the transistor, and an impurity region disposed between the two gate lines is a common bit line of the transistor. It becomes a contact area.

The first test pattern 300 and the second test pattern 400 are disposed in the test pattern area around the active area, in particular, the first test pattern 300 has the same structure as the first transistor, and the second test pattern 400 has the same structure as the second transistor. In detail, the first active region 302 is disposed in the first test pattern region in which the first test pattern 300 is disposed, and the second active region is in the second test pattern region in which the second test pattern 400 is disposed. 402 is disposed. The first active region 302 and the second active region 402 are grooved type active regions protruding from the center thereof. The first gate line 304 is disposed to cross the first active region 302, and the second gate line 404 is disposed to cross the second active region 402. Although only the first test pattern 300 and the second test pattern 400 are shown in two regions of the first and second active regions 302 and 402 in the drawing, this is for the sake of simplicity of the drawing. The same test pattern as the second test pattern 400 and the first test pattern 300 may be disposed on the right side of the active region 302 and the left side of the second active region 402, respectively.

The storage node contact region of the first active region 302 is connected to the first terminal pad 312 through the landing plug 306, the storage node contact 308, and the first metal line 310. The bit line contact region of the first active region 302 is connected to the second terminal pad 320 through the landing plug 314, the bit line contact 316, and the second metal line 318. The first gate line 304 of the first active region 302 is connected to the third terminal pad 322. Similarly, the storage node contact region of the second active region 402 is connected to the fourth terminal pad 412 through the landing plug 406, the storage node contact 408, and the fourth metal line 410. The bit line contact of the second active region 402 is connected to the second terminal pad 320 through the landing plug 414, the bit line contact 416, and the second metal line 318. The second gate line 404 of the second active region 402 is connected to the third terminal pad 322. The bit line contact region of the first test pattern 300 and the bit line contact region of the second test pattern 400 are connected to each other through the second metal line 318 as shown. The first gate line 304 and the second gate line 404 are commonly connected to the third terminal pad 322. As such, the bit line contact regions of the two test patterns 300 and 400 are connected by the same metal line 318, and the gate lines 304 and 404 of the two test patterns 300 and 400 are common to the same terminal pad. Since it is connected to, the change in the threshold voltages of the two transistors can be detected at once.

4 is an equivalent circuit diagram of the test pattern of FIG. 3, and FIG. 5 is a diagram illustrating a layout design of the test pattern of FIG. 3.

4 and 5, the drain terminal D, the source terminal S, and the gate terminal G of the first test pattern 300 are respectively the first terminal pad 312 and the second terminal pad 320. ) And the third terminal pad 322. Similarly, the drain terminal D, the source terminal S, and the gate terminal G of the second test pattern 400 are respectively the fourth terminal pad 412, the second terminal pad 320, and the third terminal pad 322. ) That is, the source terminal S of the first test pattern 300 and the source terminal S of the second test pattern 400 are commonly used, and the gate terminal G and the second of the first test pattern 300 are used in common. The gate terminal G of the test pattern 400 is also commonly used. A bias of a predetermined size is also applied to the substrate or well region where the first test pattern 300 and the second test pattern 400 are disposed, and thus the substrate or well region is also connected to the substrate terminal (B) 500. Connected.

The first resistor R1 is disposed between the storage node contact region and the drain terminal D 312 of the first test pattern 300, and the second resistor R1 is disposed between the bit line contact region and the source terminal S 320. The resistor R2 is disposed. The first resistor R1 and the second resistor R2 are resistors existing by wirings. A third resistor R3 is disposed between the storage node contact region and the drain terminal D (512) of the second test pattern 500, and a fourth resistor is disposed between the bit line contact region and the source terminal S (320). The resistor R4 is disposed. The third resistor R3 and the fourth resistor R4 are also resistors existing by the wiring.

By using such a test pattern, the source terminal (S) 320 has a voltage of 0 V to detect a change in the threshold voltage caused by the misalignment caused by the overlay mismatch between the recess gate trench and the recess gate mask. A bias is applied, a negative bias of -0.8V is applied to the substrate terminal (B) 500, and a 1.4V bias is applied to the drain terminals (D) 312 and 412, respectively. When the voltages of the gate terminals G and 322 are measured, the threshold voltages of the first test pattern 300 and the second test pattern 400 can be simultaneously calculated. Accordingly, the thresholds of the first transistor and the second transistor can be calculated. Voltage can be detected simultaneously.

6 to 11 are layout diagrams shown to explain a method of manufacturing a test pattern according to the present invention.

First, as shown in FIG. 6, the active region is defined using the first mask pattern 600 that defines the active region. The first mask pattern 600 has a light transmission region 610 and a light blocking pattern 620. The light transmission region 610 corresponds to the device isolation region where the trench device isolation layer is to be formed, and the light blocking region 620 corresponds to the active region. The light blocking pattern 620 is a grooved type having a center projecting up and down. This grooved type has the advantage that the drain current amount can be increased. Since the light blocking region 620 of the first mask pattern 600 is grooved, it is obvious that the active region formed is also grooved.

Next, as shown in FIG. 7, a trench for a recess gate and a recess gate are formed in the substrate using the second mask pattern 700. Typically, the buffer oxide film is formed to a thickness of 47-53 kV before forming the recess gate trench. Next, ion implantation using a deep n-well mask is performed to form a deep n-well. The ion implantation may be performed by implanting phosphorus P at an ion implantation energy of 1.0 MeV, a tilt angle of 3, 2 degrees and / or 1.6 degrees and a concentration of 1.4 × 10 ¹³ . The annealing is then performed for approximately 30 minutes at a temperature of approximately 950 degrees. Next, ion implantation using a p-well mask is performed to form a p-well region. The ion implantation may be performed by implanting boron (B) at an ion implantation energy of 300 KeV, a tilt angle of 3, 2 and / or 1.6 degrees and a concentration of 2.0 × 10 ¹³ . Next, ion implantation is performed for field stop formation. This ion implantation can be carried out by implanting boron (B) at an ion implantation energy of 90 KeV, a tilt angle of 7 degrees and a concentration of 3.0 x 10 ¹² . Next, channel threshold voltage ion implantation is performed. This ion implantation can be carried out by implanting BF ₂ at a concentration of 5.0 × 10 ¹² perpendicular to the ion implantation energy of 40 KeV. The cleaning was then performed for approximately 185 seconds with a 50: 1 diluted HF solution, followed by a solution of NH ₄ OH: H ₂ O ₂ : H ₂ O at a ratio of 1: 4: 20 at approximately 25 ° C. The cleaning is performed by dipping for approximately 10 minutes at the temperature of.

Subsequently, in order to form the recess gate, the gate oxide film is first grown to a thickness of approximately 45 kV after the recess gate trench is formed. A gate conductive film such as a polysilicon film, a tungsten silicide film, and a hard mask nitride film are sequentially stacked to a thickness of approximately 2280-2520 mm 3. The recess gate is formed by patterning the second mask pattern 700. The second mask pattern 700 has a stripe shape. After forming the recess gate, a gate light oxidation process is performed to form an oxide film having a thickness of approximately 49-55 kV over the recess gate. Cell-halo ion implantation is performed to improve device characteristics. Cell-halo ion implantation can be carried out by implanting boron (B) four times at ion concentration of 15 KeV, tilt angle of 12 degrees and concentration of 1.1 × 10 ¹³ . After cell-halo ion implantation is performed, n-type impurity ion implantation is performed in the bit line contact region and the storage node contact region of the substrate. This ion implantation can be performed by injecting aside (As) at a concentration of 5.1 x 10 ¹⁴ vertically with an ion implantation energy of 5 KeV.

Next, as shown in FIG. 8, a landing plug contact (LPC) is formed using the third mask pattern 800. The third mask pattern 800 has a light blocking pattern 820 defined by the light transmitting region 810 and the light transmitting region 810. Protruding portions above and below the light blocking pattern 820 are for increasing exposure margin, and in some cases, the protruding portions may not exist. In order to form the landing plug contact using the third mask pattern 800, first, the bit line contact region and the storage node contact region of the substrate are exposed, and then a landing plug contact conductive film is formed on the entire surface. In addition, the landing plug contact is formed by patterning the landing plug contact conductive layer using the third mask pattern 800. Meanwhile, the portion indicated by a dotted line in the drawing represents a recess gate.

Next, as shown in FIG. 9, a bit line contact (BLC) is formed using the fourth mask pattern 900. The second mask pattern 900 has a light blocking pattern 920 defined by the light transmission region 910. The light blocking pattern 920 has a hole type. In order to form the bit line contact, an interlayer insulating film is first formed on the entire surface, and a contact hole is formed through the interlayer insulating film to expose a surface of the landing plug contact, which is in contact with the bit line contact region of the substrate. The contact hole is filled with a conductive film for bit line contact, and then patterning is performed using the fourth mask pattern 900 to form a bit line contact.

Next, as shown in FIG. 10, a bit line is formed using the fifth mask pattern 1000. The fifth mask pattern 1000 has a light blocking pattern 1020 defined by the light transmission region 1010. The light blocking pattern 1020 has a stripe shape that crosses the recess gate line substantially perpendicularly. In order to form the bit line, a bit line conductive film is first formed. The bit line is formed by patterning the conductive film for the bit line using the fifth mask pattern 1000.

This produces a result as shown in FIG. In Fig. 11, reference numeral 1110 denotes a recess gate, reference numeral 1120 denotes a landing plug contact, reference numeral 1130 denotes a bit line contact, and reference numeral 1140 denotes a bit line. . The test pattern formed in each active region in the resultant thus formed has a structure as shown in FIG. 3.

As described above, according to the test pattern of the semiconductor device having the recess gate and the manufacturing method thereof according to the present invention, a change in the threshold voltage can be detected through one test of two transistors, and thus the number of tests This reduces the overall test time by reducing

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

Claims (8)

In the test pattern of the semiconductor device for detecting a change in the threshold voltage of each of the first transistor disposed in the first active region and the second transistor disposed in the second active region adjacent to the first active region, A first test pattern and a second test pattern are disposed in the first test area and the second test area around the first and second active areas, respectively, having the same structure as the first transistor and the second transistor. , And a bit line contact region of the first test pattern and a bit line contact region of the second test pattern are electrically connected to each other. The method of claim 1, wherein the first test pattern and the second test pattern, First and second recess gates having a stripe shape passing through first and second regions of the test region, respectively; First and second bit line contacts connected to the bit line contact region in the first region and the bit line contact region in the second region; And And a bit line having a stripe shape connected to the first and second bit line contacts and intersecting the first and second recess gates. The method of claim 2, The first recess gate and the second recess gate are connected to the external terminal in common through the same wiring, wherein the test pattern of the semiconductor device having a recess gate. The method of claim 2, A test pattern of a semiconductor device having a recess gate, wherein the first region and the second region are grooved. In the method of manufacturing a test pattern of a semiconductor device for detecting a change in the threshold voltage of each of the first transistor disposed in the first active region and the second transistor disposed in the second active region adjacent to the first active region, Forming a first region and a second region defined by the device isolation region on the substrate; Forming a trench for a first recess gate and a trench for a second recess gate crossing the first region and the second region; Forming a first recess gate and a second recess gate in a stripe form to fill the trench for the first recess gate and the trench for the second recess gate; Forming first and second bit line contacts in contact with first and second bit line contact regions of the substrate defined by the first recess gate and the second recess gate; And And forming a stripe-shaped bit line connected to the first and second bit line contacts at the same time and intersecting the first and second recess gates. Method for manufacturing a test pattern of the device. The method of claim 5, The forming of the first region and the second region may include a mask including a light transmission region corresponding to the device isolation region, and a light blocking pattern corresponding to the first region and the second region and having a groove shape. Method of manufacturing a test pattern of a semiconductor device having a recess gate, characterized in that performed by. The method of claim 5, And connecting the first recess gate and the second recess gate with the same wiring, wherein the test pattern of the semiconductor device having the recess gate is formed. The method of claim 7, wherein A first external terminal connected to the wiring, a second external terminal connected to the bit line, a third external terminal connected to the storage node region of the first region, and a storage node region of the second region And forming a fourth external terminal to be connected to the substrate, and a fifth external terminal to be connected to the substrate.

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