KR100719390B1 - Mixer circuit - Google Patents

Abstract

The invention relates to a mixer circuit 31 comprising a mixing component 33 for frequency downconversion which is adapted to downconvert the input radio frequency signals Irf + and Irf−. In order to improve such a mixer circuit, it is proposed that the mixer circuit further comprises an active mixer load circuit 34 connected to the output terminals of the mixing component. The active mixer load circuit is flicker noise generated by an active mixer load 51, T1, T2 and the active mixer load and out of the signal band of the signals Ibb +, Ibb- outputted by the frequency downconversion mixing component. Modulating means (S1-S4) adapted to modulate. The invention also relates to a receiver, a chip and an apparatus comprising such a mixer circuit and a method of using such a mixer circuit.

Description

Mixer circuit

The present invention relates to a mixer circuit comprising a mixing component for frequency downconversion that is adapted to downconvert an input radio frequency signal. The invention also relates to receiver circuits, devices and chips comprising such mixer circuits. The invention also relates to a method of using such a mixer circuit.

Mixer circuits having a mixing component for frequency downconversion for frequency downconverting radio frequency (RF) signals may be used in particular in radio frequency (RF) receivers.

For illustration purposes, a block diagram of a representative analog direct conversion receiver 10 is provided as shown in FIG. 1.

The illustrated receiver 10 comprises a low noise amplifier (LNA) 11 for amplifying received radio frequency (RF) signals, mixers 12 for frequency downconverting the amplified radio frequency (RF) signals, frequency down An analog signal processing component 13 for processing the converted signals, analog-to-digital converters (ADC) 14 for converting the processed analog signals into digital signals, and digital for further processing of the digital signals. A signal processing component (DSP) 15. For the processing of the analog frequency down-converted signal, the analog signal processing component 13 includes an Nth order low pass filter (LPF), an analog gain control (AGC) unit, a direct current (DC) offset remover, and the like. For the processing of the digital signal, the DSP 15 includes decimation stages, LPF, and the like. The output of the DSP 15 forms a digital baseband (BB) output.

The receiver 10 may be integrated into the mobile terminal 16 for receiving and processing radio frequency (RF) signals transmitted by the mobile communication network, for example.

FIG. 2 is a circuit diagram schematically illustrating a simple implementation of the front end of the receiver of FIG. 1. The circuit of FIG. 2 is a radio frequency (RF) amplifier 21 with the low noise amplifier (LNA) 11, a Gilbert cell 22 with mixers 22, and an analog signal processing component 13. It includes two low pass filter (LPF) stages 25 and 27 which are baseband filters. Instead of the second order low pass filters (LPFs) 25,27 shown, higher order low pass filters (LPFs) may also be used.

The low noise amplifier (LNA) 11 comprises two input terminals and two output terminals. The low noise amplifier (LNA) 11 amplifies the received RF signals RF IN and outputs the amplified signals as voltages Urf + and Urf−. The output terminals of the low noise amplifier 11 are connected to two signal input terminals of the mixing component 23 for frequency downconversion of the Gilbert cell 22. The mixing component 23 receives alternating local oscillator signals LO +, LO- via two additional input terminals, the alternating local oscillator signals LO +, LO- receiving input radio frequency signals ( Enable frequency down conversion of RF IN). The resulting baseband signals are output as voltages Ubb + and Ubb− through corresponding output terminals. Moreover, the output of the mixing component 23 is connected to the mixer load 24 in the Gilbert cell 22.

The first output terminal of the mixing component 23 is an operational amplifier of the first low pass filter (LPF) stage 25 through a first input terminal of the first low pass filter stage 25 and a resistor R3a. And a first output of the operational amplifier 26 is connected to a first output terminal of the first low pass filter stage 25. A capacitor C1a on the one hand and a resistor R1a on the other hand are made in parallel to each other between the first input and the first output of the operational amplifier 26.

The second output terminal of the mixing component 22 is connected to the second input of the operational amplifier 26 through a second input terminal of the first low pass filter (LPF) stage 25 and a resistor R3b. The second output of the operational amplifier 26 is connected to the second output terminal of the first low pass filter (LPF) stage 25. A capacitor C1b on the one hand and a resistor R1b on the other hand are made in parallel to each other between the second input and the second output of the operational amplifier 26.

The first output terminal of the first low pass filter 25 is connected to the second low pass filter LPF through a first input terminal of the second low pass filter LPF stage 27 and a resistor R4a. It is connected to the first input of the operational amplifier 28 of (27), and the first output of the operational amplifier 28 is connected to the first output terminal of the second low pass filter (LPF) stage 27. Capacitor C2a on the one hand and resistor R2a on the other hand are made in parallel to each other between the first input and the first output of the operational amplifier 28.

The second output terminal of the first low pass filter (LPF) stage 25 is connected to the operational amplifier 28 through the second input terminal of the second low pass filter (LPF) stage 27 and the resistor R4b. A second output of the operational amplifier 28 is connected to the second low pass filter (LPF) stage 27. A capacitor C2b on the one hand and a resistor R2b on the other hand are made in parallel to each other between the first input and the first output of the operational amplifier 28.

Two low pass filter (LPF) stages 25 and 27 apply second order low pass filtering on baseband signals Ubb + and Ubb− received from Gilbert mixer 22. The resulting low pass filtered baseband signals are transmitted to analog-to-digital converters 14 of FIG.

Implementing a receiver with such a direct conversion architecture has the advantage of being cheaper than other conversion architectures such as superheterodyne architectures, since expensive band pass filter components for intermediate frequencies (IF) can be directly converted. Because it is not necessary.

An additional advantage is that the receiver can be realized as a system on chip (SoC) solution, that is, the components of the receiver can be implemented on a single chip. Because of cost, size and other advantages, the use of deep submicron complementary metal oxide semiconductor (CMOS) technology draws attention to such SoC solutions.

However, when using a deep submicron CMOS implementation, flicker noise, also referred to as 1 / f noise, should be considered because it is inversely proportional to frequency. Flicker noise is particularly problematic in second generation (2G) systems, such as the Global System for Mobile Communications (GSM) and, to a lesser extent, third generation (3G) systems. In modern and future CMOS technologies that require low supply voltages, such noise problems become more common. If the supply voltage is reduced, the noise should also be less. An additional difficulty associated with low supply voltages is linearity. Since the limit and saturation voltages consume most of the supply voltage range in the case of low supply voltages, the linearity worsens in the case of low supply voltages than in the case of high supply voltages. Therefore, the conventional direct conversion receiver becomes increasingly difficult to implement low voltage processes in the future.

The main component of the receiver for direct conversion and the most important component regarding linearity and noise is the mixer. Conventional direct conversion receivers include a passive load for the mixer, which consists of resistors and capacitors to provide first order attenuation for interferences and a suitable signal gain. Such passive mixer loads are difficult to design to obtain the required gain, the required noise, and the required linearity, because these factors are all tied to the load impedance and bias current of the mixing component. Therefore, in modern CMOS architectures operating at low supply voltages, conventional mixer structures present significant noise and linearity problems.

Noise problems in the receiver for direct conversion can be avoided by using a Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) based chip for critical RF and baseband blocks.

Therefore, digital baseband components of a direct conversion receiver, such as a DSP, are usually implemented using CMOS technology. In contrast, radio frequency (RF) components of a direct conversion receiver, including low noise amplifiers (LNAs), mixers, and analog baseband signaling processing components, are often implemented using BiCMOS technology or other analog-oriented semiconductor processes. Thus, a complete receiver is usually implemented using at least two separate chips for radio frequency (RF) and digital baseband, which increases production costs.

It is an object of the present invention to provide an alternating mixer circuit. In particular, it is an object of the present invention to provide a mixer circuit that allows to achieve sufficient mixer linearity without increasing flicker noise.

A mixer circuit is proposed, which includes a mixing component for frequency downconversion and an active mixer load circuit configured to downconvert the input radio frequency signal. The active mixer load circuit is connected to the output terminals of the mixing component for frequency downconversion. The active mixer load circuit comprises modulation means for modulating flicker noise generated by the active mixer load and the active mixer load and deviating from the signal band of the signal output by the mixing component for frequency downconversion.

Moreover, receiver circuits, chips and devices have been proposed that receive radio frequency signals and provide corresponding frequency down-converted signals, each comprising a proposed mixer circuit.

Finally, a method of using a mixer circuit comprising a mixing component for frequency downconversion and an active mixer load circuit is proposed. The proposed method includes frequency downconverting a radio frequency signal received through the mixing component for frequency downconversion. The proposed method further comprises controlling the output voltage of the mixing component for frequency downconversion through the active mixer load of the active mixer load circuit. The proposed method further comprises modulating flicker noise generated by the active mixer load and deviating from the signal band of the frequency down-converted radio frequency signal.

The present invention derives from the consideration that active mixer loads are more suitable for mixer circuits than passive mixer loads, especially for low voltage applications. Active mixer loads provide more freedom in designing the mixer with the desired performance, especially in optimizing voltage gain and headroom, and consequently linearity. When an active mixer load is employed in the mixer circuit, the common mode (CM) and differential impedances can be separated and designed independently of each other to be high or low level. In the case of a passive load these factors are combined.

However, when the passive mixer load of the conventional mixer circuit is replaced by an active mixer load, additional noise due to the active mixer load, in particular the additional flicker noise, is in the signal band of the frequency down-converted signal, for example the baseband of GSM. Is a problem. Therefore, it is further proposed to allow the flicker noise of the active mixer load to be modulated out of the signal band.

Compared with mixer circuits including passive mixer loads, the advantage of the present invention is that the active mixer loads allow for better mixer linearity, i.e., better third order interception point (IIP3). Moreover, this allows an active load controller to be used to control the common mode voltage of the output nodes of the mixer circuit.

Compared to a simple active mixer load topology, the advantage of the present invention is that the flicker noise added by the active mixer load is lowered because the proposed modulation means can remove the flicker noise from the signal band. The low noise level of the signal band is achieved through the use of modulation techniques and no low noise process is required to reduce flicker noise.

The proposed modulation does not reduce flicker noise due to the mixer component itself for frequency down modulation. However, this noise can be further lowered because the bias current of the mixing component can be lowered due to the improved linearity.

Since noise is removed from the signal band through modulation, CMOS technology or other “noisy” semiconductor technology, particularly deep submicron semiconductor technology, can be used to implement mixer circuits on a chip to have sufficient mixer performance. Accordingly, the present invention provides a solution to the problem associated with the interface between frequency downconversion components and subsequent baseband processing components implemented via, for example, submicron CMOS technology. As a result, the present invention can implement a complete receiver using modern deep submicron semiconductor processes with a low supply voltage, in particular a SoC type solution.

The modulation means may for example comprise switching elements. Generally the use of switching or chopping techniques for analog circuits is known in the art for the use of sigma-delta modulators and instrumentation amplifiers. The switching technique used in the receiver is also mentioned in US Pat. No. 6,125,272, but is not cooperating with an active mixer load.

The mixing component for frequency downconversion may be adapted to frequency downconvert radio frequency current mode signals or radio frequency voltage mode signals.

The proposed mixer circuit can be implemented in radio frequency (RF) circuits using digital or analog semiconductor technologies. This is particularly suitable for pure submicron digital CMOS processes without any additional process options.

The proposed mixer circuit can be employed in any intermediate frequency (IF) receiver such as, for example, a low intermediate frequency (IF) receiver or a heterodyne receiver or the like or in a receiver for direct conversion. Moreover, the receiver in which the proposed mixer circuit is implemented may belong to any type of wireless system.

The proposed device may in particular be a device comprising a receiver in which the proposed mixer circuit is employed. Such a device may for example be a mobile terminal or a network element of a wireless communication network.

Other objects and features of the present invention will become apparent from the following detailed description considered in conjunction with the accompanying drawings.

1 is a block diagram illustrating a conventional direct conversion receiver in which the present invention can be implemented.

FIG. 2 is a circuit diagram schematically showing conventional implementation details for radio frequency (RF) and analog front-end of the receiver for direct conversion of FIG. 1.

3 is a circuit diagram schematically showing an implementation for radio frequency (RF) and analog front-end of a direct conversion receiver according to the present invention.

4 is a flowchart illustrating the operation of a receiver according to the present invention.

5 is a circuit diagram schematically showing one embodiment of a switched active load of a mixer according to the present invention.

The present invention is implemented by way of example in the receiver 10 for direct conversion provided above with reference to FIG.

3 shows details of the radio frequency (RF) and analog front-end of the receiver 10 of FIG. 1 in which one embodiment of the mixer circuit according to the invention is employed.

The circuit of FIG. 3 includes a mixer circuit 31, a first low pass filter (LPF) stage 35 and a second low pass filter (LPF) stage 37.

The mixer circuit 31 comprises two input terminals connected to the output of the low noise amplifier (LNA) 11 of FIG. In the mixer circuit 31, the input terminals are connected to the output terminals of the mixer circuit 31 via a transconductance element GM 32 and a mixing component 33. The mixing component 33 comprises additional input terminals for receiving alternating local oscillator signals LO +, LO-. Moreover, an active mixer load circuit 34 is connected to the output terminals of the mixing component 33.

The first output terminal of the mixer circuit 31 is connected to the first of the operational amplifier 36 of the first low pass filter 35 through the first input terminal of the first low pass filter LPF stage 35. Connected to an input, a first output of the operational amplifier 36 is connected to a first output terminal of the first low pass filter (LPF) stage 35. Capacitor C1a on the one hand and resistor R1a on the other hand are made in parallel to each other between the first input and the first output of the operational amplifier 36.

The second output terminal of the mixer circuit 31 is connected to the second input of the operational amplifier 36 through the second input terminal of the first low pass filter (LPF) stage 35 and the operational amplifier ( A second output of 36 is connected to the second output terminal of the first low pass filter (LPF) stage 35. Capacitor C1b on the one hand and resistor R1b on the other hand are made in parallel to each other between the first input and the second output of the operational amplifier 36.

The first output terminal of the first low pass filter (LPF) stage 35 is connected to the second low pass filter through the first input terminal and the resistor R4a of the second low pass filter (LPF) stage 37. (LPF) is connected to the first input of the operational amplifier 38 of the stage 37, the first output of the operational amplifier 38 is the first output terminal of the second low pass filter (LPF) stage 37 Is connected to. Capacitor C2a on the one hand and resistor R2a on the other hand are made in parallel to each other between the first input and the first output of the operational amplifier 38.

The second output terminal of the first low pass filter (LPF) stage 35 is connected to the operational amplifier 38 through the second input terminal of the second low pass filter (LPF) stage 37 and the resistor R4b. And a second output of the operational amplifier 38 is connected to a second output terminal of a second low pass filter (LPF) stage 37. Capacitor C2b on the one hand and resistor R2b on the other hand are configured in parallel with each other between the first input and the first output of the operational amplifier 38.

The capacitors C1a, C1b, C2a, C2b and resistors R1a, R1b, R2a, and R2b at the low pass filter LPF stages 35 and 37 have a configuration of the low pass filter LPF of FIG. Because of the same construction as in stages 25 and 27, the same reference numerals are used.

Finally, two output terminals of the second low pass filter (LPF) stage 37 are connected to the analog-to-digital converter 14 of the receiver 10 of FIG. 1.

In the embodiment provided above, the receiver 10 is realized as a SoC solution, in other words, all components of the receiver 10 shown in FIGS. 1 and 3 are a single deep submicron CMOS chip ( 39).

The operation of the receiver of FIG. 1, including the radio frequency (RF) and analog front-end provided in FIG. 3, will now be described with reference to FIG. 4.

The received radio frequency (RF) voltage mode signals (RF input) are first amplified by the low noise amplifier (LNA) 11. Next, the amplified radio frequency (RF) voltage mode signals RF IN are converted into radio frequency (RF) current mode signals Irf + and Irf− by the transconductance element 32. The transconductance element 32 may comprise one or two transistors for this purpose.

Thereafter, radio frequency (RF) current mode signals Irf +, Irf- are frequency downconverted to baseband by the mixing component 33 via alternating local oscillator signals LO +, LO-. The mixing component 33 may comprise transistors for frequency downconversion for this purpose.

Active mixer load circuit 34 measures the current mode baseband signals Ibb +, Ibb− output by the mixing component 33 to band hold the output voltage to a desired value. The design and operation of the active mixer load circuit 34 will be described in more detail below with reference to FIG. 5.

The differential current mode baseband signals Ibb + and Ibb− are currently supplied to the analog baseband processor 13 for further processing. The current mode interface brings additional benefits for linearity. The analog baseband processing function includes a second order low pass filter function having two low pass filter (LPF) stages 35, 37 shown in FIG. 3. The low pass filtered signals are then converted into a digital domain by an analog-to-digital converter (ADC) 14 and the digital baseband signals are received before the digital baseband signals are output by the receiver as digital baseband output. It is additionally processed by the signal processing component (DSP) 15.

FIG. 5 shows details of the active mixer load circuit 34 of the mixer circuit 31 of FIG. 3.

The connection of the mixing component 33 of the mixer circuit 31 and the mixing component 33 to the active mixer load circuit is shown by dotted lines. The mixer circuit 31 has local oscillator signals LO +, LO- in addition to radio frequency (RF) current mode signals Irf +, Irf- as input signals as mentioned above with reference to FIGS. 3 and 4. ).

The output terminals of the mixer circuit 31 are connected to the first low pass filter (LPF) stage 35 on the one hand as mentioned with reference to FIG. 3. The signals provided to the first low pass filter (LPF) stage 35 are referred to as Outp and Outn in FIG. 5. In the embodiment of FIG. 3, the signals Outp and Outn consequently correspond to current mode baseband signals Ibb + and Ibb−. In another embodiment, the signals Outp and Outn of FIG. 5 may also be voltage mode signals supplied to a later low pass filter (LPF) stage, which is described above for a later low pass filter (LPF) stage. Depends on the type of connection of the mixer circuit.

All of the output terminals of the mixer circuit 31 are additionally connected to the corresponding input of the operational amplifier 51. The third input of the operational amplifier 51 is provided with a common mode reference voltage VCMREF. The output of the operational amplifier 51 is connected to the corresponding gates of the two transistors T1 and T2. The operational amplifier 51 and the transistors T1 and T2 form the actual active mixer load.

The first output terminal of the mixer circuit 31 may be further connected to ground Gnd through the first transistor T1 and the first switching element S1. The first output terminal of the mixer circuit 31 may be connected to ground Gnd through the second transistor T2 and the second switching element S2.

The second output terminal of the mixer circuit 31 may be further connected to ground Gnd through the first transistor T1 and the third switching element S3. The second output terminal of the mixer circuit 31 may be connected to ground Gnd through the second transistor T2 and the fourth switching element S4.

In a conventional active mixer load, in contrast, the first output terminal of the mixing component is fixedly connected to ground via the first transistor, while the second output terminal of the mixing component is fixedly connected to ground via the second transistor.

In the active mixer load circuit of FIG. 5, the switching elements S1 to S4 are included to remove flicker noise due to the actual active mixer loads 51, T1 and T2. The switching elements S1, S4 are closed in this way in an alternating manner with the switching elements S2, S3. The control signal of the switching elements S1 and S4 is shown in FIG. 5 and the complementary control signal for switching of the switching elements S2 and S3 is shown in FIG. 5 as xpch. Through such switching operation, the flicker noise of the active mixer load circuit 34 can be made to be modulated from the baseband to the band near the switching frequency. As a result, the flicker noise problem of conventional active mixer loads is avoided.

As noise is removed from the signal band through modulation, a CMOS based chip can be used for the implementation of the mixer circuit.

The embodiment provided above consequently provides a solution to a significant problem with the interface between the frequency downconversion mixer circuit 31 of the direct conversion receiver and the following baseband processing components implemented via submicron CMOS technology. . This facilitates SoC implementation and enhances the possibility of using the CMOS technology to integrate the radio frequency (RF) portion through the digital baseband. The SoC solution can lower production costs because two chips, one chip is for the radio frequency (RF) part and the other chip is for the baseband part, are replaced by a single chip.

Flicker noise and misalignment of the actual signal frequency downconversion transistors in the mixing component 33 are not mentioned in the embodiment provided above. The above-cited document US Pat. No. 6,125,272 compensates for misalignment of the frequency downconversion transistors of the mixing component that can be combined through the embodiments provided above and improves the resulting secondary non-linearity of the mixing component IIP2. The possibility of doing is disclosed.

It should be noted here that the embodiments mentioned above form only one of several possible embodiments of the invention.

Claims (11)

In the mixer circuit 31, A frequency down-conversion mixing component 33 configured to down-convert the input radio frequency signals Irf + and Irf-; And An active mixer load circuit 34 connected to the output terminals of the mixing component 33 for frequency downconversion, comprising an active mixer load 51, T1, T2 and modulation means S1-S4. Circuitry 34, The active mixer load includes a first transistor T1, a second transistor T2, and an operational amplifier 51, wherein a first output terminal of the frequency downconversion mixing component 33 is the operational amplifier 51. A second output terminal of the mixing component 33 for frequency downconversion, is connected to a second input of the operational amplifier 51, and a reference common mode voltage input of the operational amplifier 51; A reference common mode voltage VCMREF is applied thereto, and an output of the operational amplifier 51 is connected in parallel with corresponding gates of the first transistor T1 and the second transistor T2, The modulation means S1-S4 comprise a plurality of switching elements S1-S4, wherein the switching elements S1-S4 are generated by the active mixer loads 51, T1, T2 and the frequency In order to modulate the flicker noise deviating from the signal bands of the signals Ibb + and Ibb- outputted by the down-conversion mixing component 33 in an alternating manner, on the other hand, through the first transistor T1 A first output terminal of the frequency downconversion mixing component 33 and a second output terminal of the frequency downconversion mixing component 33 through the second transistor T2 are connected to ground Gnd. On the other hand, the first output terminal of the mixing component 33 for frequency downconversion through the second transistor T2 and the mixing component for frequency downconversion through the first transistor T1 ( Even if the second output terminal of 33) is connected to ground (Gnd), The mixer circuit 31, characterized in that the lock. delete delete Mixer circuit (31) according to claim 1, characterized in that the mixing component (33) for frequency downconversion is adapted to frequency downconvert radio frequency current mode signals. 2. Mixer circuit (31) according to claim 1, characterized in that the mixing component for frequency down conversion is adapted to frequency down change radio frequency voltage mode signals. A receiver circuit (10) for receiving radio frequency signals, wherein the receiver circuit (10) provides corresponding frequency down-converted signals, wherein the receiver circuit (10) is one of claims 1, 4 and 5. Receiver circuit (10), characterized in that it comprises a mixer circuit (31) according to one of the preceding claims. 7. A method as claimed in claim 6, characterized in that at least one component (15) of the receiver circuit (10) configured to process at least one of the mixer circuit (31) and digital baseband signals is integrated in a single chip (16). Receiver circuit (10). A chip comprising at least one mixer circuit (31) according to one of claims 1, 4 and 5. 10. The chip of claim 8, wherein the mixer circuit (31) is implemented on the chip via deep submicron semiconductor technology. Apparatus comprising a mixer circuit (31) according to one of the preceding claims. A method of using a mixer circuit (31) comprising a mixing component (33) and an active mixer load circuit (34) for frequency downconversion, wherein the active mixer load circuit (34) comprises an active mixer load, and the active mixer load. Includes a first transistor (T1), a second transistor (T2) and an operational amplifier (51), wherein a first output terminal of the frequency downconversion mixing component (33) is a first input of the operational amplifier (51). A second output terminal of the mixing component 33 for frequency downconversion is connected to a second input of the operational amplifier 51, and a reference common mode voltage input to the reference common mode voltage input of the operational amplifier 51; In the method of using a mixer circuit in which a voltage VCMREF is applied, and an output of the operational amplifier 51 is connected in parallel with corresponding gates of the first transistor T1 and the second transistor T2, The method, Frequency downconverting the radio frequency signals Irf + and Irf− received through the frequency downconversion mixing component 33; Controlling the output voltage of the frequency downconversioning mixing component (33) via an active mixer load (51, T1, T2) of the active mixer load circuit (34); And In an alternating manner, on the one hand, the first output terminal of the mixing component 33 for frequency downconversion through the first transistor T1 and the frequency downconversion through the second transistor T2. The second output terminal of the mixing component 33 is connected to ground Gnd, and on the other hand, the first output terminal of the mixing component 33 for frequency downconversion is connected through the second transistor T2. And by the active mixer loads 51, T1, T2 by connecting the second output terminal of the mixing component 33 for frequency down conversion to ground Gnd through the first transistor T1. And modulating the flicker noise outside the signal band of the frequency down-converted radio frequency signals (Ibb +, Ibb−).

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