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KR100711521B1 - Manufacturing method of defect elimination epitaxial thin film using metal filling - Google Patents

Manufacturing method of defect elimination epitaxial thin film using metal filling Download PDF

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KR100711521B1
KR100711521B1 KR1020050125897A KR20050125897A KR100711521B1 KR 100711521 B1 KR100711521 B1 KR 100711521B1 KR 1020050125897 A KR1020050125897 A KR 1020050125897A KR 20050125897 A KR20050125897 A KR 20050125897A KR 100711521 B1 KR100711521 B1 KR 100711521B1
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substrate
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thin film
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epitaxy
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방욱
김남균
김형우
김상철
서길수
강인호
김기현
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한국전기연구원
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02378Silicon carbide
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02529Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

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Abstract

본 발명에 따른 금속충전을 이용한 결함제거 에피탁시 박막의 제조방법은, 그 내부에 결함이 존재하는 탄화규소 단결정 기판을 KOH 용액 내에서 약 400℃∼700℃의 온도 범위에서 1∼30분 동안 에칭하여 기판 내에 존재하는 결함을 선택적으로 에칭하는 단계; 상기 결함이 선택적으로 에칭된 기판의 표면에 티타늄(Ti), 탄탈륨(Ta), 텅스텐(W) 중의 어느 하나의 금속을 상기 선택적 에칭에 의해 형성된 에치피트들을 충분히 덮을 수 있을 정도의 두께로 증착하는 단계; 상기 금속이 증착된 기판 표면을 연마하여 에치피트 내부에 존재하는 금속을 제외하고 모두 제거하는 단계; 상기 에치피트 내부에만 금속이 채워진 기판을 금속이 산화되지 않도록 환원분위기의 로 내에서 소정의 온도 범위에서 열처리하여 에치피트 내에 존재하는 잔존 금속과 탄화규소 기판과의 반응에 의한 합금을 형성하는 단계; 및 상기 에치피트 내에 합금이 채워진 기판을 고온 박막성장이 가능한 장치에 장착하여 탄화규소 에피탁시 박막을 성장시키는 단계를 포함하여 구성된다.In the method for manufacturing a defect elimination epitaxy thin film using a metal filling according to the present invention, a silicon carbide single crystal substrate having a defect therein is used in a KOH solution at a temperature range of about 400 ° C to 700 ° C for 1 to 30 minutes. Etching to selectively etch a defect present in the substrate; Depositing a metal of any one of titanium (Ti), tantalum (Ta), and tungsten (W) on a surface of the substrate on which the defect is selectively etched to a thickness sufficient to cover etch pits formed by the selective etching; step; Polishing the surface of the metal-deposited substrate to remove all metals except etch pits; Heat-treating the substrate filled with the metal only in the etch pit at a predetermined temperature range in a furnace of a reducing atmosphere so as to prevent the metal from being oxidized to form an alloy by reaction between the remaining metal present in the etch pit and the silicon carbide substrate; And growing a thin film of silicon carbide epitaxy by mounting the substrate filled with the alloy in the etch pit to a device capable of high temperature thin film growth.

이와 같은 본 발명에 의하면, 기존에 존재하는 기판내 결함들을 금속합금으로 선택적으로 충전함으로써 이후 성장되는 에피탁시 박막 내로 이러한 결함들의 침투를 원천적으로 봉쇄할 수 있다.According to the present invention, it is possible to fundamentally block the penetration of these defects into the epitaxial thin film grown by selectively filling the existing defects in the substrate with a metal alloy.

Description

금속충전을 이용한 결함제거 에픽탁시 박막의 제조방법{Method for manufacturing defect removed epitaxy film using metal filling}Method for manufacturing defect removed epitaxy film using metal filling}

도 1은 종래의 특별한 표면처리 없이 에피탁시 박막을 성장한 경우의 기판 및 에피탁시 박막 내부에 존재하는 여러 결함들을 보여주는 도면.1 is a view showing a number of defects existing in the substrate and the epitaxy thin film when the epitaxy thin film is grown without any conventional surface treatment.

도 2는 일반적인 탄화규소 기판의 내부에 존재하는 여러 결함들을 보여주는 도면.2 shows various defects present inside a typical silicon carbide substrate.

도 3은 본 발명에 따른 금속충전을 이용한 결함제거 에피탁시 박막의 제조방법에 있어서, 기판 내부의 결함들을 선택적으로 에칭한 상태를 보여주는 도면. 3 is a view showing a state of selectively etching defects in a substrate in a method of manufacturing a thin film for removing epitaxy using a metal filling according to the present invention.

도 4는 탄화규소 기판의 결함을 KOH 용액을 이용해 에칭한 기판 표면의 실제 모습을 보여주는 광학현미경 사진.Figure 4 is an optical micrograph showing the actual appearance of the substrate surface etched defects of the silicon carbide substrate using a KOH solution.

도 5는 본 발명에 따른 금속충전을 이용한 결함제거 에피탁시 박막의 제조방법에 있어서, 결함을 선택적으로 에칭한 기판 위에 금속막을 증착한 상태를 보여주는 도면. 5 is a view showing a state in which a metal film is deposited on a substrate on which a defect is selectively etched in a method of manufacturing a thin film for removing epitaxy using a metal filling according to the present invention.

도 6은 도 5에서의 금속막을 연마하여 에치피트 부분을 제외한 나머지 부분의 금속을 모두 제거한 상태를 보여주는 도면.FIG. 6 is a view illustrating a state in which all metals except for etch pit are removed by polishing the metal film of FIG. 5; FIG.

도 7은 본 발명에 따른 금속충전을 이용한 결함제거 에피탁시 박막의 제조방법에 있어서, 에피탁시 박막 성장 직전 잔존 금속이 고온에서 탄화규소 기판과 반 응하여 합금을 이룬 상태를 보여주는 도면.FIG. 7 is a view illustrating a state in which a residual metal immediately before epitaxial thin film growth forms an alloy in response to a silicon carbide substrate at a high temperature in the method of manufacturing a defect elimination epitaxy thin film using metal filling according to the present invention.

도 8은 도 7의 합금이 형성된 기판 위에 결함이 제거된 에피탁시 박막이 성장된 상태를 보여주는 도면.FIG. 8 is a view illustrating a state in which a thin film of epitaxy in which defects are removed is grown on a substrate on which the alloy of FIG. 7 is formed.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

100,300...탄화규소 기판
101,820...에피탁시 박막
100,300 ... silicon carbide substrate
101,820 ... epitaxy thin film

102,106,302...micropipe 결함
103,107,303...threading 전위결함
102,106,302 ... micropipe defect
103,107,303 ... threading potential defect

104,108,304...threading 전위와 basal plane 전위가 결합된 형태의 결함104,108,304 ... a defect in the form of a combination of threading potential and basal plane potential

105,109,305...basal plane 전위결함
310...micropipe 결함의 에치피트
105,109,305 ... basal plane potential defect
310 ... micropipe etch etched

311...threading 전위결함의 에치피트
313...basal plane 전위결함의 에치피트
311 ... Etching of threading potential defect
313.Etch pit of potential plane defect

312...threading 전위와 basal plane 전위가 결합된 형태의 결함에 대한 에치피트 312 ... Etch pits for defects in the form of a combination of threading potential and basal plane potential

615...micropipe 결함이 선택적으로 에칭된 부분에 채워진 금속 Metal filled in areas where 615 ... micropipe defects are selectively etched

616...threading 전위결함이 선택적으로 에칭된 부분에 채워진 금속616 ... Metal filled in areas where thread defects are selectively etched

617...threading 전위와 basal plane 전위가 결합된 형태의 결함이 선택적으로 에칭된 부분에 채워진 금속 617 ... metal filled in selectively etched defects of a combination of threading potential and basal plane potential

618...basal plane 전위결함이 선택적으로 에칭된 부분에 채워진 금속Metal filled in areas where the 618 ... basal plane dislocation defect is selectively etched

719...선택적으로 에칭된 부분에 형성된 금속합금 719 ... Metal Alloy Formed on the Etched Part Optionally

본 발명은 에피탁시(epitaxy) 박막의 제조방법에 관한 것으로서, 더 상세하게는 기존에 존재하는 기판내 결함들을 금속합금으로 선택적으로 충전함으로써 이후 성장되는 에피탁시 박막 내로 이러한 결함들이 침투하지 못하게 하며, 결과적으로 고품질, 저결함의 에피탁시 박막 성장을 가능하게 하고, 고 신뢰도의 탄화규소 전자소자를 제조할 수 있도록 하는 금속충전을 이용한 결함제거 에피탁시 박막의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing an epitaxy thin film, and more particularly, by selectively filling existing defects in a substrate with a metal alloy to prevent such defects from penetrating into the later grown epitaxy thin film. And, as a result, the present invention relates to a method for manufacturing a defect elimination epitaxy thin film using metal filling, which enables the growth of a high quality, low defect epitaxy thin film and enables the production of silicon carbide electronic devices with high reliability.

탄화규소는 고출력, 고주파 및 고온에서 작동하는 반도체재료로서 그 특성이 우수하다. 하지만, 탄화규소 기판(100)의 내부에는 도 1 및 도 2에 도시된 바와 같이, micropipe 결함(102) 및 threading 전위결함(103), basal plane 전위결함(105) 및 threading 전위와 basal plane 전위가 결합된 형태의 결함(104) 등 다수의 결함들이 존재하여 탄화규소를 이용한 전자소자의 특성과 신뢰성 등을 나쁘게 하는 요인으로 작용한다. 이러한 결함들은 기판으로 사용하는 웨이퍼 내에 존재하며, 소자 제작에 필수적인 고품질의 에피탁시 박막을 성장할 때 박막 내부로 침투하여 에피탁시 박막(101) 내에도 micropipe 결함(106) 및 threading 전위결함(107), basal plane 전위결함(109) 및 threading 전위와 basal plane 전위가 결합된 형태의 결함(108) 등의 결함들이 존재하게 되고, 결과적으로 에피탁시 박막 위에 형성되는 소자의 특성을 악화시키게 된다. 이러한 기판결함의 에피탁시 박막 내로의 침투를 억 제하기 위해 LPE 성장방법 등이 사용되기도 하였으나, 이 방법으로 성장된 박막의 경우 불순물 농도를 제어하기 힘들고, 표면이 거친 점 등이 실제 소자제작에 응용하기에는 부적합한 것으로 알려져 있다. 최근에는 CVD법을 이용한 전통적인 에피탁시 박막성장 기법에서도 성장속도와 원료가스 내부의 Si/C 비율을 조절하여 박막이 성장하는 동안 micropipe 결함이 여러 개의 screw 전위결함으로 바뀌는 기술이 개발되었으나, 이 경우에는 초기 성장된 박막 내부에는 여전히 micropipe 결함이 존재하고 두껍게 성장된 경우, 표면에 가까운 부분만 micropipe 결함이 없는 영역이 존재하게 되어, 성장시킨 에피탁시 박막 전체를 활용할 수 없는 문제가 있다. 또한 이는 micropipe 결함을 여러 개의 screw 전위결함으로 대체하는 효과를 갖기 때문에 전체 결함의 양은 줄어들지 않는다. 따라서 기판표면에서부터 결함을 제어하여 성장하는 에피탁시 박막 내의 결함을 줄이는 방법이 요구된다. 이러한 기판내 결함들은 KOH 용액에서 선택적으로 에칭되며 그 모양과 크기는 결함의 특성에 따라 달라진다는 것이 Katsuno 등에 의해 보고된 바 있다. 에피탁시 박막성장은 주로 step flow에 의해 이루어지며 표면에 TaC 등의 층이 존재할 때 그 층에는 박막이 성장하지 않는 선택적 에피탁시 방법이 Li 등에 의해 보고되기도 했다.Silicon carbide is a semiconductor material that operates at high power, high frequency and high temperature, and has excellent characteristics. However, inside the silicon carbide substrate 100, as shown in FIGS. 1 and 2, the micropipe defect 102 and the threading dislocation defect 103, the basal plane dislocation defect 105, and the threading potential and the basal plane potential are present. There are a number of defects such as the defect 104 of the combined form, which acts as a factor deteriorating the characteristics and reliability of the electronic device using silicon carbide. These defects are present in the wafer used as a substrate, and penetrate into the thin film when the high-quality epitaxy thin film essential for device fabrication is grown, and the micropipe defect 106 and the threading dislocation defect 107 are also present in the epitaxial thin film 101. ), a defect such as a basal plane potential defect 109 and a defect 108 in which a threading potential and a basal plane potential are combined, resulting in deterioration of the characteristics of the device formed on the thin film during epitaxy. The LPE growth method has been used to suppress the penetration of substrate defects into the thin film during epitaxy.However, in the case of thin film grown by this method, it is difficult to control the impurity concentration, and the roughness of the surface is a factor in the actual device fabrication. It is known to be unsuitable for application. Recently, even in the conventional epitaxial thin film growth technique using CVD, a technique has been developed in which the micropipe defect is changed into several screw dislocation defects during the growth of the thin film by controlling the growth rate and the Si / C ratio in the source gas. There is still a problem that the micropipe defects still exist inside the initially grown thin film, and when grown thickly, only a portion close to the surface is free of micropipe defects, and thus the entire epitaxial thin film cannot be utilized. It also has the effect of replacing micropipe defects with multiple screw potential defects, so the total amount of defects is not reduced. Therefore, there is a need for a method of reducing defects in epitaxial thin films grown by controlling defects from the substrate surface. It has been reported by Katsuno et al. That defects in these substrates are selectively etched in KOH solution and their shape and size depend on the nature of the defects. Thin film growth during epitaxy is mainly performed by step flow, and a selective epitaxy method in which a thin film does not grow on a layer when TaC or the like is present on the surface has been reported by Li et al.

본 발명은 이상과 같은 사항을 감안하여 창출된 것으로서, 기존에 존재하는 기판내 결함들을 금속합금으로 선택적으로 충전함으로써 이후 성장되는 에피탁시 박막 내로 이러한 결함들이 침투하지 못하게 하며, 결과적으로 고품질, 저결함의 에피탁시 박막 성장을 가능하게 하고, 고 신뢰도의 탄화규소 전자소자를 제조할 수 있도록 하는 금속충전을 이용한 결함제거 에피탁시 박막의 제조방법을 제공함에 그 목적이 있다.The present invention has been made in view of the above matters, and by selectively filling the existing defects in the substrate with a metal alloy to prevent such defects from penetrating into the later grown epitaxy thin film, resulting in high quality, low It is an object of the present invention to provide a method for manufacturing a defect elimination epitaxy thin film using metal filling, which enables thin film growth during epitaxy of defects and enables the production of silicon carbide electronic devices with high reliability.

상기의 목적을 달성하기 위하여 본 발명에 따른 금속충전을 이용한 결함제거 에피탁시 박막의 제조방법은,In order to achieve the above object, a method of manufacturing a defect elimination epitaxy thin film using metal filling according to the present invention,

a) 그 내부에 결함이 존재하는 탄화규소 단결정 기판을 KOH 용액 내에서 약 400℃∼700℃의 온도 범위에서 1∼30분 동안 에칭하여 기판 내에 존재하는 결함을 선택적으로 에칭하는 단계;
b) 상기 결함이 선택적으로 에칭된 기판의 표면에 티타늄(Ti), 탄탈륨(Ta), 텅스텐(W) 중의 어느 하나의 금속을 상기 선택적 에칭에 의해 형성된 에치피트들을 충분히 덮을 수 있을 정도의 두께로 증착하는 단계;
a) selectively etching the silicon carbide single crystal substrate having defects therein in the KOH solution at a temperature range of about 400 ° C to 700 ° C for 1-30 minutes to selectively etch a defect present in the substrate;
b) on the surface of the substrate where the defect is selectively etched to a thickness such that any one of titanium (Ti), tantalum (Ta) and tungsten (W) can sufficiently cover the etch pits formed by the selective etching. Depositing;

삭제delete

c) 상기 금속이 증착된 기판 표면을 연마하여 에치피트 내부에 존재하는 금속을 제외하고 모두 제거하는 단계;c) polishing the substrate surface on which the metal is deposited to remove all but the metal present in the etch pits;

d) 상기 에치피트 내부에만 금속이 채워진 기판을 금속이 산화되지 않도록 환원분위기의 로 내에서 소정의 온도 범위에서 열처리하여 에치피트 내에 존재하는 잔존 금속과 탄화규소 기판과의 반응에 의한 합금을 형성하는 단계; 및 d) heat-treating a substrate filled with metal only in the etch pit at a predetermined temperature range in a furnace of a reducing atmosphere so as not to oxidize the metal to form an alloy by reaction between the remaining metal present in the etch pit and the silicon carbide substrate; step; And

e) 상기 에치피트 내에 합금이 채워진 기판을 고온 박막성장이 가능한 장치에 장착하여 탄화규소 에피탁시 박막을 성장시키는 단계를 포함하여 구성된 점에 그 특징이 있다.e) mounting a substrate filled with an alloy in the etch pit to a device capable of high temperature thin film growth, and growing a thin film of silicon carbide epitaxy.

이하 첨부된 도면을 참조하면서 본 발명의 실시예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3 내지 도 8은 본 발명에 따른 금속충전을 이용한 결함제거 에피탁시 박막의 제조방법을 각 단계별로 순차적으로 보여주는 도면이다. 3 to 8 are diagrams sequentially showing the manufacturing method of the thin film when removing the defect epitaxy using the metal filling in accordance with the present invention step by step.

도 3을 참조하면, 본 발명에 따른 금속충전을 이용한 결함제거 에피탁시 박막의 제조방법에 따라 먼저, 그 내부에 결함(302∼305)이 존재하는 탄화규소 단결정 기판(예를 들면, PVT(physical vapor transport)법으로 성장시킨 단결정을 가공하여 제조한 탄화규소 기판)(300)을 특정 용액(예를 들면, KOH 용액) 내에서 소정 온도 범위(예컨대, 약 400℃∼700℃)로 1∼30분 동안 에칭하여 기판(300) 내에 존재하는 결함(302∼305)을 선택적으로 에칭한다. 도 3에서 참조번호 302는 micropipe 결함, 303은 threading 전위결함, 304는 threading 전위와 basal plane 전위가 결합된 형태의 결함, 305는 basal plane 전위결함, 310은 micropipe 결함의 에치피트(etch pit), 311은 threading 전위결함의 에치피트, 312는 threading 전위와 basal plane 전위가 결합된 형태의 결함에 대한 에치피트, 313은 basal plane 전위결함의 에치피트를 각각 나타낸다. Referring to Figure 3, according to the method for manufacturing a defect removal epitaxy thin film using a metal filling according to the present invention, first, silicon carbide single crystal substrate (for example, PVT ( The silicon carbide substrate 300 manufactured by processing the single crystal grown by the physical vapor transport method is 1 to a predetermined temperature range (for example, about 400 ° C to 700 ° C) in a specific solution (for example, KOH solution). Etching for 30 minutes selectively etches defects 302-305 present in substrate 300. In FIG. 3, reference numeral 302 denotes a micropipe defect, 303 denotes a threading dislocation defect, 304 denotes a threading potential coupled with a basal plane potential, 305 denotes a basal plane potential defect, and 310 denotes an etch pit of the micropipe defect, 311 denotes an etch fit of a threading dislocation defect, 312 denotes an etch fit for a defect in the form of a combination of threading potential and a basal plane potential, and 313 denotes an etch fit of a basal plane potential defect.

도 4는 이상과 같이 탄화규소 기판의 결함을 KOH 용액을 이용해 에칭한 기판 표면의 실제 모습을 보여주는 전자현미경 사진이다.Figure 4 is an electron micrograph showing the actual appearance of the surface of the substrate etched defects of the silicon carbide substrate using a KOH solution as described above.

도 4를 통해 알 수 있듯이, 선택적으로 에칭된 에치피트들(310,311,313)은 각각의 결함의 특성 및 결정학적 에너지 상태에 따라 그 크기 및 모양이 각각 다르다. 즉, 가장 불안정한 상태인 micropipe에 의한 결함(302)은 깨끗한 경계면을 갖는 육각형 형태의 에치피트(310)를 형성하며, 그 에칭된 깊이도 가장 깊다. threading 전위결함(303)에 의해 형성된 에치피트(311)는 다소 둥근 형태를 갖는 육각형 모양이며, 일반적으로 그 크기는 micropipe에 의한 에치피트(310)에 비해서는 작으나 각각의 전위의 burgers vector 즉, 스트레스의 크기에 따라 그 크기 및 깊이도 달라진다. 반면 basal plane 전위결함(305)에 의한 에치피트(313)는 기울어진 조개껍질(shell) 형태이며, 그 크기도 일반적으로 작다. 이들 각각의 에치피트의 크기 및 깊이는 KOH 용액의 온도 및 에칭시간을 조절함에 따라 조절할 수 있다. As can be seen in FIG. 4, the selectively etched etch pits 310, 311, and 313 differ in size and shape depending on the nature of each defect and the crystallographic energy state. That is, the defect 302 by the micropipe in the most unstable state forms an etch pit 310 in the form of a hexagon having a clean interface, and the etched depth is also the deepest. The etch pit 311 formed by the threading dislocation defect 303 is a hexagon having a somewhat round shape, and generally has a size smaller than that of the etch pit 310 by the micropipe, but the stress burgers vector of each dislocation, that is, stress Depending on the size, its size and depth also vary. On the other hand, the etch pit 313 due to the basal plane dislocation defect 305 is in the form of an inclined shell, and its size is generally small. The size and depth of each of these etch pits can be adjusted by controlling the temperature and etching time of the KOH solution.

이렇게 하여 결함들에 대한 선택적인 에칭이 완료되면, 도 5에 도시된 바와 같이, 그 선택적으로 에칭된 기판(300)의 표면에 탄화규소와 열처리 과정에서 쉽게 합금을 형성할 수 있고, 고온에서 안정한 특정 금속, 예를 들면, 티타늄(Ti), 탄탈륨(Ta), 텅스텐(W) 등과 같은 금속을 상기 선택적 에칭에 의해 형성된 에치피트들(310∼313)을 충분히 덮을 수 있을 정도의 두께(수 ㎛의 두께)로 증착한다. 이때 금속의 증착법으로는 스퍼터링(sputtering), 전기도금, 증발(evaporation)법 등이 사용될 수 있다. 도 5에서 참조번호 514는 기판 표면에 증착된 금속막을 나타낸다.When the selective etching of the defects is completed in this way, as shown in FIG. 5, an alloy may be easily formed on the surface of the selectively etched substrate 300 during the heat treatment process, and is stable at high temperatures. The thickness of the specific metal, for example, a metal such as titanium (Ti), tantalum (Ta), tungsten (W), or the like to sufficiently cover the etch pits 310 to 313 formed by the selective etching. Thickness). In this case, as the metal deposition method, sputtering, electroplating, evaporation, or the like may be used. In FIG. 5, reference numeral 514 denotes a metal film deposited on the substrate surface.

금속의 증착이 완료되면, 도 6에 도시된 바와 같이, 그 금속이 증착된 기판 표면을 연마하여 에치피트 내부에 존재하는 금속을 제외하고는 모두 제거한다. 이때, 이와 같은 연마작업을 위해 CMP(chemical mechanical polish)법 등이 사용될 수 있다. 도 6에서 참조번호 615는 micropipe 결함이 선택적으로 에칭된 부분에 채워진 금속, 616은 threading 전위결함이 선택적으로 에칭된 부분에 채워진 금속, 617은 threading 전위와 basal plane 전위가 결합된 형태의 결함이 선택적으로 에칭된 부분에 채워진 금속, 618은 basal plane 전위결함이 선택적으로 에칭된 부분에 채워진 금속을 각각 나타낸다.When the deposition of the metal is complete, as shown in FIG. 6, the substrate surface on which the metal is deposited is polished to remove all but the metal present inside the etchpit. In this case, a chemical mechanical polish (CMP) method may be used for such polishing. In FIG. 6, reference numeral 615 denotes a metal filled in a portion where the micropipe defect is selectively etched, 616 denotes a metal filled in a portion where the threading dislocation defect is selectively etched, and 617 denotes a defect in which a threading potential and a basal plane potential are combined. 618 denotes the metal filled in the portion where the basal plane dislocation defect is selectively etched.

이렇게 하여 에치피트 부분을 제외한 나머지 부분에 대한 금속의 제거작업이 완료되면, 도 7에서와 같이, 그 에치피트 내부에만 금속이 채워진 기판을 금속이 산화되지 않도록 환원분위기의 로 내에서 약 800℃∼1400℃의 온도 범위에서 열처리하여 에치피트 내에 존재하는 잔존 금속과 탄화규소 기판과의 반응에 의한 합금(719)을 형성한다. 이때 열처리는 에피탁시 박막성장과 별도로 수행할 수도 있고, 동시에 수행할 수도 있다. 열처리를 동시에 수행하는 경우에는 에피탁시 박막이 성장되기 전 승온 과정에서 우선적으로 합금화가 이루어지고, 이후 박막이 성장되는 과정을 따르게 된다.In this way, when the removal of the metal to the remaining portion except the etch pit is completed, as shown in Figure 7, the substrate filled with only the metal inside the etch pit in the furnace of the reducing atmosphere to prevent the metal from oxidizing The heat treatment is performed at a temperature in the range of 1400 ° C. to form an alloy 719 by reaction between the remaining metal present in the etch pit and the silicon carbide substrate. At this time, the heat treatment may be performed separately from the epitaxial thin film growth, or may be performed at the same time. In the case where the heat treatment is performed at the same time, alloying is preferentially performed during the temperature increase process before the thin film is grown during epitaxy, and then the thin film is grown.

이상에 의해 열처리에 의한 합금의 형성까지 완료되면, 도 8에 도시된 바와 같이, 그 합금이 채워진 기판을 고온 박막성장이 가능한 장치, 예를 들면 CVD (chemical vapor deposition)장치나 LPE(liquid phase epitaxy)장치 내에 장착하여 탄화규소 에피탁시 박막(820)을 성장시킨다. 에피탁시 박막 성장시 결함부분에 선택적으로 존재하는 금속합금의 영향으로 직접적으로 박막이 성장되지 않고, 주변부에서 성장한 에피탁시 박막이 step flow에 의해 확장되어 금속 합금부분을 덮게 되어 결함들이 에피탁시 박막 내부로 침투하는 것을 억제하게 된다. 따라서 성장된 에피탁시 박막(820)은 기판의 결함들이 거의 침투하지 않는 저결함의 에피탁시 박막으로 성장하게 된다. When the alloy is formed by heat treatment as described above, as shown in FIG. 8, the substrate filled with the alloy is capable of high temperature thin film growth, for example, a chemical vapor deposition (CVD) device or a liquid phase epitaxy (LPE). It is mounted in the device to grow the silicon carbide epitaxy thin film 820. When epitaxial thin films are grown, the thin films are not directly grown due to the selective presence of metal alloys in the defects.The epitaxial thin films grown at the periphery are expanded by step flow to cover the metal alloy parts. Infiltration into the thin film is suppressed. Therefore, the grown epitaxial thin film 820 grows into a low defect epitaxy thin film in which defects of the substrate hardly penetrate.

이상의 설명에서와 같이, 본 발명에 따른 금속충전을 이용한 결함제거 에피탁시 박막의 제조방법은 기존에 존재하는 기판내 결함들을 금속합금으로 선택적으 로 충전함으로써 이후 성장되는 에피탁시 박막 내로 이러한 결함들이 침투하지 못하게 하므로, 기존의 탄화규소 단결정 기판 및 에피탁시 박막을 이용하여 제조한 전자소자의 작동을 불가능하게 하거나(micropipe 결함의 경우), 소자의 수명 또는 신뢰성을 저하시키는 기판내 결함들(threading dislocation, basal dislocation)의 에피탁시 박막 내부로의 침투를 봉쇄할 수 있다. As described above, the method for manufacturing a defect elimination epitaxy thin film using the metal filling according to the present invention is such a defect into the epitaxy thin film which is subsequently grown by selectively filling the existing substrate defects with a metal alloy. This prevents them from penetrating, making it impossible to operate electronic devices fabricated using conventional silicon carbide single crystal substrates and epitaxy thin films (in the case of micropipe defects), or defects in substrates that degrade device lifetime or reliability ( When epitaxy of threading dislocation (basal dislocation) can block the penetration into the thin film.

그리고, 이상과 같은 본 발명의 방법을 이용하여 성장시킨 탄화규소 에피탁시 박막을 이용함으로써 저결함의 고품질 탄화규소 에피탁시 박막을 성장시킬 수 있고, 또한 이를 이용하여 탄화규소 전자소자의 특성을 향상시키고 신뢰성을 향상시킬 수 있다.Further, by using the silicon carbide epitaxy thin film grown using the method of the present invention as described above, it is possible to grow a high quality silicon carbide epitaxy thin film with low defects, and also to use the silicon carbide electronic device to Can improve the reliability.

Claims (7)

a) 그 내부에 결함이 존재하는 탄화규소 단결정 기판을 KOH 용액 내에서 약 400℃∼700℃의 온도 범위에서 1∼30분 동안 에칭하여 기판 내에 존재하는 결함을 선택적으로 에칭하는 단계;a) selectively etching the silicon carbide single crystal substrate having defects therein in the KOH solution at a temperature range of about 400 ° C to 700 ° C for 1-30 minutes to selectively etch a defect present in the substrate; b) 상기 결함이 선택적으로 에칭된 기판의 표면에 티타늄(Ti), 탄탈륨(Ta), 텅스텐(W) 중의 어느 하나의 금속을 상기 선택적 에칭에 의해 형성된 에치피트들을 충분히 덮을 수 있을 정도의 두께로 증착하는 단계;b) on the surface of the substrate where the defect is selectively etched to a thickness such that any one of titanium (Ti), tantalum (Ta) and tungsten (W) can sufficiently cover the etch pits formed by the selective etching. Depositing; c) 상기 금속이 증착된 기판 표면을 연마하여 에치피트 내부에 존재하는 금속을 제외하고 모두 제거하는 단계;c) polishing the substrate surface on which the metal is deposited to remove all but the metal present in the etch pits; d) 상기 에치피트 내부에만 금속이 채워진 기판을 금속이 산화되지 않도록 환원분위기의 로 내에서 소정의 온도 범위에서 열처리하여 에치피트 내에 존재하는 잔존 금속과 탄화규소 기판과의 반응에 의한 합금을 형성하는 단계; 및 d) heat-treating a substrate filled with metal only in the etch pit at a predetermined temperature range in a furnace of a reducing atmosphere so as not to oxidize the metal to form an alloy by reaction between the remaining metal present in the etch pit and the silicon carbide substrate; step; And e) 상기 에치피트 내에 합금이 채워진 기판을 고온 박막성장이 가능한 장치에 장착하여 탄화규소 에피탁시 박막을 성장시키는 단계를 포함하여 구성된 것을 특징으로 하는 금속충전을 이용한 결함제거 에피탁시 박막의 제조방법.e) manufacturing a defect removal epitaxy thin film using a metal charge, comprising the step of growing a silicon carbide epitaxy thin film by mounting the substrate filled with alloy in the etch pit to a device capable of high temperature thin film growth Way. 삭제delete 삭제delete 삭제delete 제1항에 있어서,The method of claim 1, 상기 단계 c)에서의 기판 표면의 연마는 CMP 법을 이용하여 이루어지는 것을 특징으로 하는 금속충전을 이용한 결함제거 에피탁시 박막의 제조방법.Polishing the surface of the substrate in step c) is made using a CMP method, the method of manufacturing a thin film for removing defects epitaxy using metal filling. 제1항에 있어서,The method of claim 1, 상기 단계 d)에서 기판을 환원분위기의 로 내에서 800℃∼1400℃의 온도 범위에서 열처리하는 것을 특징으로 하는 금속충전을 이용한 결함제거 에피탁시 박막의 제조방법.In step d), the substrate is heat-treated in a furnace in a reducing atmosphere at a temperature ranging from 800 ° C. to 1400 ° C. A method for manufacturing a defect elimination epitaxy thin film using metal filling. 제1항에 있어서,The method of claim 1, 상기 단계 d)에서의 열처리를 상기 단계 e)에서의 에피탁시 박막성장과 별도로 수행하지 않고, 에피탁시 박막성장시의 승온과정에서 잔존금속과 탄화규소 기판과의 반응에 의해 합금을 형성하는 것을 특징으로 하는 금속충전을 이용한 결함제거 에피탁시 박막의 제조방법.The heat treatment in step d) is not performed separately from the epitaxial thin film growth in step e), and an alloy is formed by the reaction of the remaining metal and the silicon carbide substrate in the temperature rising process during epitaxial thin film growth. Method for producing a thin film epitaxial defect removal using a metal filling, characterized in that.
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WO2013027995A3 (en) * 2011-08-22 2013-04-18 Lg Innotek Co., Ltd. Process of surface treatment for wafer
CN115159449A (en) * 2022-07-25 2022-10-11 上海华虹宏力半导体制造有限公司 Method for improving etching defect
CN116885069A (en) * 2023-09-05 2023-10-13 至芯半导体(杭州)有限公司 Light extraction layer, ultraviolet LED epitaxial structure, and preparation method and application thereof

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013027995A3 (en) * 2011-08-22 2013-04-18 Lg Innotek Co., Ltd. Process of surface treatment for wafer
US9719189B2 (en) 2011-08-22 2017-08-01 Lg Innotek Co., Ltd. Process of surface treatment for wafer
CN115159449A (en) * 2022-07-25 2022-10-11 上海华虹宏力半导体制造有限公司 Method for improving etching defect
CN116885069A (en) * 2023-09-05 2023-10-13 至芯半导体(杭州)有限公司 Light extraction layer, ultraviolet LED epitaxial structure, and preparation method and application thereof
CN116885069B (en) * 2023-09-05 2023-12-19 至芯半导体(杭州)有限公司 Light extraction layer, UV LED epitaxial structure and preparation method and application thereof

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