KR100708826B1 - Computer system and method for outputting clock signal suitable for a plurality of memory modules - Google Patents

Abstract

The present invention relates to a computer system for detecting an operating frequency of a plurality of DIMM memory modules used as main memory and correspondingly generating a clock signal suitable for each memory module. The computer system includes a memory module clock determiner for determining a clock speed of the memory module and a clock generator for outputting clock signals of a central processing unit, a memory, and a system controller. The clock generation unit receives the first and second clock control signals from the central processing unit, and determines the clock signals of the central processing unit, the memory, and the system controller in conjunction with the detection signal according to the determination result. Therefore, a memory clock signal suitable for each memory module is generated.

Description

COMPUTER SYSTEM OF GENERATING CLOCK SIGNAL FITTED FOR A PLURALITY OF OF MEMORY MODULES AND METHOD OF THE SAME

1 is a block diagram illustrating some components of a general computer system having a plurality of memory modules;

2 is a block diagram schematically showing some components of a computer system according to the present invention; And

FIG. 3 is a block diagram illustrating a connection configuration between the memory modules illustrated in FIG. 2 and a clock signal of a clock generator.

* Explanation of symbols on the main parts of the drawing *

100: computer system 104: central processing unit

106: system controller 108: clock generator

110: memory section

112a through 112c: memory modules

114, 114a to 114c: memory module clock determination unit

116, 116a ~ 116c: resistance

P24: Pin 24 of the memory module

The present invention relates to a computer system, and more particularly, to an apparatus and method for determining a frequency of operation of memory modules of a computer system having a plurality of memory modules to generate a clock signal suitable for each memory module. .

Dual In-line Memory Module (DIMM), the most commonly used RAM (SDRAM) memory module used in computer systems, uses signals defined by the Joint Electron Device Engineering Council (JEDEC) standard or the Intel standard.

In addition, speeds representing characteristics of the memory module are classified into PC 66, PC 100, and PC 133. This rate represents the operating frequency of the memory, for example, PC 100 refers to a clock rate of 100 MHz. However, the clock speed of a memory module is not recognized or automatically controlled by a conventional computer system.

Referring to FIG. 1, a general computer system 2 includes a central processing unit 4 (CPU) and a memory unit 10 having at least one or more memory modules (for example, three or four) and a central processing unit. A system controller (eg, a northbridge controller) 6 is connected to the apparatus 4 to control the writing and reading of the memory unit 10. And a clock generator 8 for outputting clock signals from the central processing unit 4, the memory unit 10, and the system controller 6.

The computer system 2 includes components of a typical computer system (e.g., input / output devices such as a keyboard and a mouse, and auxiliary storage devices such as hard disk drives and CD-ROM drives and display devices, etc.) (not shown). .

Accordingly, the clock generator 8 may respond to the clock control signal CONT_CLK generated from the central processing unit 4, and the clock signals CLK_CPU, of the central processing unit 4, the memory unit 10, and the system controller 6 may be adjusted. Generate CLK_MEM and CLK_CONT). At this time, the clock signals CLK_CPU, CLK_MEM, and CLK_CONT generated by the clock control signal CONT_CLK correspond to the operating speeds of the central processing unit 4, the memory unit 10, and the system controller 6. Or another frequency.

The clock generator 8 may include a predetermined size ROM (EEPROM), and may logically adjust the clock speed of the memory module using data stored in the ROM (EEPROM).

The clock speeds of the memory unit 10 are generally divided into clock frequencies of 66 MHz, 100 MHz or 133 MHz. However, this clock frequency cannot be changed again once the computer system 2 is determined by operation. Each of the plurality of memory modules includes a ROM (eg, 128 bytes of EEPROM) that supports the Serial Pesence Detect (SPD) standard, which is instituted by Intel. The ROM stores memory information such as a memory capacity of the RAM included in the memory module, a write read timing, and the like.

Therefore, when power is supplied, the computer system 2 determines the clock speeds of the central processing unit 4, the memory unit 10, and the system controller 6 in response to the clock control signal CONT_CLK. At this time, the system controller 6 reads the memory information from the ROM of the memory module through the SM bus and provides it to the clock generator 8. Therefore, through this, the memory clock speed of the memory unit 10 may be recognized.

However, since the clock generator 8 determines the memory clock speed before reading the memory information from the ROM of the memory module, it is impossible to readjust the memory clock speed according to the memory information.

As described above, since there is no function of automatically recognizing or notifying the memory clock frequency from the memory unit 10, that is, the memory modules, the clock generator 8 may be configured to supply the clock control signal of the central processing unit regardless of the type of the memory module. In response, it generates a memory clock signal. As a result, when the memory type is not correctly recognized, an inappropriate clock frequency is provided to the equipped memory module to cause a malfunction, and even if it is correctly recognized, there is no method of changing the clock frequency after powering up the computer system.

In particular, when the same type of memory modules are used, there are few problems, but when different types of memory modules are used, the computer system may cause a fatal malfunction due to an incorrect clock frequency.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems, and to implement a computer system and method for determining an operating frequency of a plurality of memory modules and generating a clock signal suitable for the corresponding memory module using the determined information. have.

According to one aspect of the present invention for achieving the above object, a computer system comprising: a central processing unit for outputting first and second clock control signals for controlling clock signals for overall operation of the system; A plurality of memory modules having means for outputting discrimination information capable of discriminating each clock speed; And a clock generator which receives the first and second clock control signals and the discrimination information and outputs clock signals having frequencies suitable for the respective memory modules.

In a preferred embodiment of this aspect, the means comprises a resistor provided between a specific pin and a ground terminal of each of the memory modules, and the clock speed of each of the memory modules according to the voltage level of the specific pin. The determination information to be determined is output.

According to a preferred embodiment of the present invention, the memory controller may further include a system controller configured to read memory information from a ROM that supports an SPD standard of the memory module and provide the read memory information to a clock generator. The clock speeds of the memory modules are determined through memory information.

Therefore, according to the present invention, the clock generator generates a clock signal suitable for each memory module by using the identification information for determining the clock speeds of the memory modules and the clock control signal of the central processing unit.

(Example)

DETAILED DESCRIPTION Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.                     

2 is a block diagram schematically showing some components of a computer system according to the present invention.

Referring to the drawings, the computer system 100 includes a central processing unit 104, a novel memory unit 110, a clock generator 108, and a system controller 106.

The central processing unit 104 has, for example, a system clock (FSB: Front Side Bus) speed of 66 MHz, 100 MHz, or 133 MHz, and includes the system controller 106 and the clock generator 108. First and second clock control signals (SELECT0 and SELECT1 of FIG. 3) for controlling clock signals for performing an operation are output. In addition, the system controller 106 outputs address, data, and control signals ADDR, DATA, and CONTROL for controlling the overall system operation.

The memory unit 110 includes a plurality of memory modules, and each memory module includes a new memory module clock determination unit 114. And the memory module has an operating frequency of clock speed of 100 NHz or 133 MHz.

The memory module clock determination unit 114 is provided as a resistor, and is provided between a specific pin of the corresponding memory module and a ground according to the size of the resistor or the presence or absence of a resistor. Accordingly, the determination result, that is, the detection signal DETECT is output to the clock generator 108 and the system controller 106 corresponding to the voltage level of the specific pin.

The system controller 106 is, for example, a north bridge controller connected to the central processing unit 104 through a host bus to control address, data and control of writing, reading and controlling system operations of the memory unit 110. Output control signals ADDR ', DATA', and CONTROL '.

And the system controller 106 has an operating frequency of clock speed of 66 MHz, 100 NHz or 133 MHz. In addition, the memory information is read from the ROM supporting the SPD standard of the memory module through the SM bus and provided to the clock generator 108. In this way, the clock generator 108 may recognize memory information such as a memory capacity of a RAM (SRAM) of the memory unit 110, a write read timing, and the like.

In addition, the clock generator 108 receives the detection signal DETECT from the first and second clock control signals SELECT0 and SELECT1 and the memory module clock discrimination unit 114 to communicate with the central processing unit 104. The clock signals CLK_CPU, CLK_MEM, and CLK_CONT of the memory unit 110 and the system controller 106 are generated.

In detail, FIG. 3 illustrates a detailed connection configuration according to the clock signals of the memory modules and the clock generator illustrated in FIG. 2.

Referring to the drawings, the CPU 104 outputs first and second clock control signals SELECT0 and SELECT1 to the clock generator 108 and the system controller 106.

The memory unit 110 includes a plurality of memory modules 112a through 112c, and each of the memory modules 112a through 112c includes memory module clock determination units 114a through 114c, respectively.

The memory module clock discrimination units 112a to 112c are provided with resistors 116a to 116c according to an exemplary embodiment, and are located between a specific pin of each of the memory modules 112a to 112c, for example, pin 24 (P24) and ground. Is provided. The detection signal DETECT corresponding to the output voltage level of pin 24 is output to the clock generator 108 and the system controller 106.

Thus, as shown in Table 1, the computer system 100 corresponds to the central processing unit 104 and the memory unit 110 in response to the first and second clock control signals SELECT0 and SELECT1 and the detection signal DETECT. And clock signals CLK_CPU, CLK_MEM, and CLK_CONT of the system controller 106.

That is, the logical level of the detection signal DETECT is determined corresponding to the output voltage levels of the memory module clock determination units 114a to 114c, and the same or different operation is performed in conjunction with the clock control signals SELECT0 and SELECT1. The clock signals CLK_CPU, CLK_MEM, and CLK_CONT of the central processing unit 104, the memory unit 110, and the system controller 106 having the frequency are generated.

TABLE 1

Clock control signal Detection signal Clock signal SELECT0 SELECT1 DETECT CLK_CPU CLK_CONT CLK_MEM LOW LOW LOW  66 MHz  66 MHz 100 MHz LOW HIGH LOW 100 MHz 100 MHz 100 MHz HIGH LOW LOW 133 MHz 133 MHz 100 MHz HIGH HIGH HIGH 133 MHz 133 MHz 133 MHz

Referring to Table 1, a part of a clock signal used in a computer system is shown. The memory clock signal of the corresponding memory module is determined by interlocking the first and second clock control signals with a detection signal.

 As described above, the present invention can output a memory clock signal suitable for each memory module in response to the clock control signals and the detection signal, so that the clock signal suitable for the memory modules can be automatically adjusted. This eliminates the need for separate clock adjustment and selection circuitry, which is effective in designing computer systems.

In addition, since the clock signals of the central processing unit and the system controller interoperate with each other, there is no need to adjust the clock speeds of the central processing unit, the memory, and the system controller separately when upgrading the central processing unit.

Claims (3)

In a computer system: A central processing unit for outputting first and second clock control signals for controlling clock signals for general operation of the system; A plurality of memory modules having means for outputting discrimination information capable of discriminating each clock speed; And a clock generator which receives the first and second clock control signals and the discrimination information and outputs clock signals having frequencies suitable for the respective memory modules. The method of claim 1, The means, And a resistor provided between a specific pin of each of the memory modules and a ground terminal, and outputting the determination information for determining a clock speed of each of the memory modules according to a voltage level of the specific pin. system. The method of claim 1, And a system controller configured to read memory information from a ROM supporting the SPD standard of the memory module and provide the read memory information to a clock generator, wherein the clock generator is configured to clock the memory module through the memory information. And determine the speeds.

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