KR100687320B1 - Liquid crystal display device and driving method thereof - Google Patents

Abstract

The present invention provides a liquid crystal capable of reducing signal distortion due to noise by dividing the data driver into two groups and thereby separating the input data, thereby reducing the frequency at the data output to 1/2 of the data at the data input. A driving method of a display element is provided.

According to an aspect of the present invention, there is provided a liquid crystal display device including a liquid crystal panel in which a plurality of data lines and a plurality of scan lines are arranged to cross each other, the plurality of drivers including a plurality of drivers for driving the data lines, wherein the plurality of drivers are odd drivers. And a data driver divided into two groups of good drivers; A gate driver for driving the scan line; The gate driver and the data driver are driven, and input data is input at a first frequency to separate odd-bit odd data and even data, and each of the corresponding odd-numbered drivers is divided into odd-numbered data and even-number data. And a controller that provides an excellent driver.

Description

Liquid crystal display device and driving method thereof {LCD AND METHOD FOR DRIVING THE SAME}

1 is a block diagram of a general TFT-LCD,

2 is a view showing an arrangement of a Y-driver (data driver) in the liquid crystal display device according to the embodiment of the present invention;

3 is a view for explaining a method of driving a liquid crystal display device according to an embodiment of the present invention;

4 is a data waveform diagram for describing an operation of a controller of a liquid crystal display device according to an exemplary embodiment of the present invention;

5 is a detailed view of a data processing unit built in a controller in the liquid crystal display device according to the embodiment of the present invention;

(Explanation of symbols for the main parts of the drawing)

100: liquid crystal panel 200: gate driver

300: data driver 400: controller

41: data parallelizing means 42, 43: memory element

44: write address control signal generating means

45: read address control signal generating means

31, 32: Driver IC

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor liquid crystal display device, wherein a liquid crystal display device capable of preventing electromagnetic interference (EMI) by outputting data having 1/2 frequency of input data using dual-pod SRAM and its It relates to a driving method.

1 is a block diagram of a general liquid crystal display device. Referring to FIG. 1, a TFT-LCD panel 10, a gate driver 20 and a data driver 30 for driving a liquid crystal panel 10 by generating a gate driving signal and a data driving signal, respectively, and the gate driver ( 20) and a controller 40 for controlling the data driver 30.

In general, the controller 30 receives a signal from the outside to generate a signal for controlling each component of the liquid crystal display such as the gate driver 20 and the data driver 30.

However, the controller has the same frequency of the input data applied from the outside and the data output to drive the data driver, such a controller has a problem that is vulnerable to EMI.

The present invention provides a liquid crystal display device and a liquid crystal display that can reduce the impact on EMI by allowing the data output from the controller to have a frequency 1/2 of the data input to the controller in order to solve the problems of the prior art as described above The purpose is to provide a driving method.

In order to achieve the above object, the present invention is a liquid crystal display device having a liquid crystal panel that is arranged so that a plurality of data lines and a plurality of scan lines cross each other, a plurality of drivers for driving the data line A data driver having a plurality of drivers divided into two groups, a radix driver and an even driver; A gate driver for driving the scan line; The gate driver and the data driver are driven, and input data is input at a first frequency to separate odd-bit odd data and even data, and each of the corresponding odd-numbered drivers is divided into odd-numbered data and even-number data. And it provides a liquid crystal display device having a controller to provide a good driver.

The second frequency is 1/2 of the first frequency at the time of data input, and the data parallelizing means separates the input data into odd data and even data by 80 bits.

The controller includes data parallelization means for inputting input data at a first frequency and separating the odd data and the even data; A first memory element for storing the odd data separated from the data parallelizing means in accordance with the write address control signal and providing the odd data to the odd address driver according to the read address control signal; And a second memory element for storing even data separated from the data parallelizing means in accordance with the write address control signal and providing the even data to the even driver according to the read address control signal.

The first memory device stores odd data of a certain bit, and the even data of a predetermined bit is stored in the second memory device, and then the even data stored in the second memory device is outputted to the odd driver and outputted to the odd driver. The second memory device stores certain bits of even data, and then outputs odd-numbered odd data previously stored to the odd driver and to the even driver. The first and second memories may be dual port SRAMs.

In addition, the present invention provides a liquid crystal display panel comprising a plurality of data lines and a plurality of scan lines arranged to cross each other; A liquid crystal display device comprising: a plurality of drivers for driving the data lines, the plurality of drivers having a data driver separated into two groups of odd and even drivers; inputting input data at a first frequency ; Dividing the input data into a bit of odd data and even data; And providing the separated odd data and the even data to each corresponding odd driver and the even driver at a second frequency to drive the liquid crystal panel.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a schematic block diagram of a liquid crystal display device according to an exemplary embodiment of the present invention. 2, a liquid crystal display device according to an exemplary embodiment of the present invention includes a TFT-LCD panel 100, a gate driver 200, a data driver 300, and a controller 400. The controller 400 according to an exemplary embodiment of the present invention does not generate the output data Dout to the data driver 300 at the same frequency as the input data Din, but at 1/2 the frequency of the input data. The output data is output to the data driver 300.

That is, as shown in FIG. 2, the odd-numbered output data Dout_odd for driving the odd-numbered data line among the output data Dout having one-half frequency of the input data is generated to the data driver 300 and inputted. The even output data Dout_even for driving the even-numbered data line among the output data Dout having 1/2 frequency of the data is generated by the data driver 400.

The data driver 300 according to the embodiment of the present invention is composed of a plurality of driver ICs. A plurality of driver ICs of the data driver 300 are divided into two groups, and one group inputs odd output data Dout_odd outputted at a frequency 1/2 of the input data from the controller 400 so that the liquid crystal panel 100 can be input. The driver ICs 311 and 31n are used to drive the odd data lines among the data lines, and another group inputs even output data Dout_even outputted from the controller 400 at the remaining half frequency of the input data. The driver ICs 321 and 32n are used to drive even-numbered data lines of the data lines of the liquid crystal panel 100.

3 is a timing diagram illustrating a method of driving a liquid crystal display device according to an exemplary embodiment of the present invention. Data input to the liquid crystal display device during one horizontal display period (1H) is different depending on the mode of XGA, SGA, etc. In the embodiment of the present invention, 640-bit input data (Din) during one horizontal display period (1H) Assume that it is entered.

When the input data Din as shown in FIG. 3B is applied during the 1H period as shown in FIG. 3A, the timing controller 400 converts the input data Din into odd data Dout_odd and even data Dout_even as shown in FIG. 3C. The data is transmitted to the corresponding driver ICs 311 and 31n and 321 and 32n. Accordingly, the odd-numbered driver ICs 311 and 31n of the plurality of drivers are inputted with the odd-number data Dout_odd applied from the controller 400 to drive the TFT-LCD panel 100, and the even-numbered drivers are arranged. The ICs 321 and 32n input the even data Dout_even applied from the controller 400 to drive the TFT-LCD panel 100.

At this time, the controller 400 separates the input data Din into even data and odd data, which are separated according to the arrangement state of the data driver. That is, even data is data provided to the even driver of the plurality of drivers and odd data is data provided to the odd driver of the plurality of drivers.

5 is a block diagram illustrating an internal configuration of a controller according to an exemplary embodiment of the present invention. Referring to FIG. 5, the controller according to an embodiment of the present invention inputs data Din at a predetermined frequency and divides the data into odd data Dout_odd and even data Dout_even in 80-bit units to output the data in parallel. (41) and odd data (Dout_odd) among the data provided from the data parallelizing means (41) are stored in accordance with the write address control signal (WCS), and the stored data is stored in accordance with the read address control signal (RCS). The first memory device 42 implemented as SRAM and the even data Dout_even among the data provided from the data parallelization means 42 for providing to the IC 31 are stored in accordance with the write address control signal WCS. And a second memory element 43 made of SRAM for providing the stored data to the corresponding driver IC 32 according to the read address control signal RCS.

In addition, the controller 400 of the present invention includes write address control signal generating means 44 for generating a write address control signal WCS to the first and second memory elements 42 and 43, and the first and second values. Read address control signal generating means 45 for generating read address control signal RCS to two memory elements 42 and 43 is further provided.

The operation of the controller of the present invention having the configuration as described above will be described with reference to the operation timing shown in FIG.

The data parallelizing means 41 of the controller 400 sequentially inputs 640 bits of input data Din in synchronization with the clock signal of FIG. 4A. As shown in FIGS. 3B and 3C, the input data Din is inputted into the radix data D1-D80, D161-D240, and even data D81-D160, D241 in 80-bit units. -D320) ... Radix data (D1-D80), (D161-D240), ... outputted from the data parallelizing means (41) are the first by the write address control signal (WCS) generated from the write address control signal generating means (44). The even data (D81-D160), (D241-D320), ... are stored in the memory device 42, and the second data is generated by the write address control signal WCS generated from the write address control signal generating means 44. It is stored in the memory element 43.

Eighty-bit odd data and even data stored in the first and second memory elements 42 and 43 are simultaneously read out by the read address control signal RCS generated from the read address signal generating means 45 to input data. Are transmitted to the odd driver IC 31 and the even driver IC 32, respectively.

At this time, the controller 400 stores the first 80-bit odd data Dout_odd through the first memory device 42 by the write address control signal WCS generated from the write address control signal generating means 44. Next, the next 80-bit even data dout_even is stored through the second memory device 43. Next, the controller 400 generates 80-bit odd data stored in the first memory device 42 of FIG. 4C and FIG. 4D by the read address control signal RCS generated from the read address control signal generating means 45. FIG. The 80-bit even data stored in the second memory device 43 of the second memory device 43 is simultaneously transmitted to the corresponding drivers 31 and 32.

That is, the controller 400 conventionally takes a method of sequentially inputting and storing data one bit per clock and then sequentially outputting one bit to one driver, but in the embodiment of the present invention, the input data is 1 The data is sequentially input and stored by 1 bit per clock, and then separated into even data and odd data. The odd data and even data are output to the radix and storm drivers 31 and 32 at the same time for each 2CLK. It was driven.

At this time, the 80-bit odd data Dout_odd is stored through the first memory element 42 according to the write address control signal WCS generated from the write address control signal generating means 44, and the next 80-bit even data ( Dout_even is stored through the second memory element 43 and then output to the corresponding driver 31 according to the read address control signal RCS generated from the read address control signal generating means 45.

Meanwhile, the 80-bit even data Dout_even is stored through the second memory element 43 according to the write address control signal WCS generated from the write address control signal generating means 44, and then stored for the previous 80 clocks. When the odd data stored in the first memory element 42 is output, they are output at the same time. To this end, the present invention uses dual port SRAMs as the first and second memory elements 42 and 43.

As described above, the controller of the present invention outputs data by setting the clock at data output to half the clock frequency at data input, thereby reducing EMI. That is, as shown in the following equation, the EMI is proportional to the period of the clock frequency. Since the data at the data output is reduced by 1/2 of the frequency at the data input, it can be seen that the EMI effect is also reduced.

As described in detail above, the liquid crystal display device of the present invention arranges drivers in parallel to separate input data through a controller, and transmits data to a corresponding driver at a frequency 1/2 of the frequency at the time of data input to a corresponding liquid crystal panel. By driving the, there is an advantage that can reduce the EMI effect of the frequency reduction.

According to the present invention, the data driver is largely divided into two groups, and accordingly, the controller is separated into odd data and storm water data and provided to the driver. However, the data driver is divided into a plurality of groups to drive the data driver. EMI can also be reduced.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (12)

A liquid crystal display device comprising a liquid crystal inner panel arranged such that a plurality of data lines and a plurality of scan lines cross each other. A data driver having a plurality of drivers for driving the data lines, wherein the plurality of drivers are divided into two groups of odd and even drivers; A gate driver for driving the scan line; The gate driver and the data driver are driven, and input data is input at a first frequency to separate odd-bit odd data and even data, and each of the corresponding odd-numbered drivers is divided into odd-numbered data and even-number data. And a controller providing an excellent driver. The liquid crystal display device of claim 1, wherein the second frequency is 1/2 of a first frequency at the time of data input. The liquid crystal display device according to claim 1, wherein the data parallelizing means separates the input data into odd data and even data by 80 bits. The method of claim 1, wherein the controller Data parallelization means for inputting input data at a first frequency and separating the odd data and the even data; A first memory element for storing the odd data separated from the data parallelizing means in accordance with the write address control signal and providing the odd data to the odd address driver according to the read address control signal; And a second memory element for storing even data separated from the data parallelizing means in accordance with the write address control signal and providing the even data to the even driver in accordance with the read address control signal. The memory device of claim 4, wherein the first memory device stores odd data of a predetermined bit, the even data of a predetermined bit is stored in the second memory device, and then the odd data stored in the second memory device is outputted to the even driver, A liquid crystal display device characterized by outputting by a driver. The liquid crystal display device of claim 4, wherein the second memory device stores certain bits of even data and then outputs odd-numbered odd data stored in a predetermined bit to the odd driver and simultaneously to the even driver. The liquid crystal display device of claim 5 or 6, wherein the first and second memories comprise dual port SRAMs. A liquid crystal inner panel arranged such that the plurality of data lines and the plurality of scan lines cross each other; A liquid crystal display device comprising: a plurality of drivers for driving the data lines, and a plurality of drivers having a data driver separated into two groups of odd and even drivers; Inputting input data at a first frequency; Dividing the input data into a bit of odd data and even data; And providing the separated odd data and the even data to the corresponding odd driver and the even driver at the second frequency to drive the liquid crystal panel. The method of claim 8, wherein the second frequency at the time of data output is 1/2 of the first frequency at the time of data input. 10. The method of claim 8, wherein the even data and the odd data are separated in units of 80 bits. The memory device of claim 8, wherein the first memory device stores odd data of a predetermined bit, the even data of a predetermined bit is stored in the second memory device, and then the even data stored in the second memory device is outputted to an even driver. A method of driving a liquid crystal display device, characterized in that outputted by a driver. The liquid crystal display device of claim 8, wherein the second memory device stores certain bits of even data and then outputs odd-numbered odd data previously stored to the odd driver and simultaneously to the even driver. Way.

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