KR100685632B1 - Manufacturing Method of NAND Flash Memory Device - Google Patents

Abstract

The present invention relates to a method of manufacturing a NAND flash memory device, and to etching a metal layer and a polysilicon layer to form a control gate, the polysilicon layer is etched only a predetermined thickness, and then a barrier film is formed on the sidewalls of the metal layer and the polysilicon layer. In one state, the polysilicon layer is completely patterned by an etching process to form a control gate, and the lower layer is also etched by a self-aligned etching process to form a floating gate, so that even if the thickness of the polysilicon layer is different in each region, the thickness is thin. It is possible to prevent the excessive etching of the polysilicon layer to prevent the gate line from thinning, and to prevent structural deformation due to volatiles generated from the metal layer, equipment contamination by metal contamination sources, and deterioration of device characteristics.

Flash Memory, Polysilicon Layer, Transient Etch, Gate Line

Description

Method of manufacturing a nand flash memory device             

1 is a layout view of a typical NAND flash memory array.

2A through 2C are cross-sectional views of devices for describing a method of manufacturing a NAND flash memory device according to the prior art.

3A to 3E are cross-sectional views of devices for describing a method of manufacturing a NAND flash memory device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

101, 301: semiconductor substrate 102, 302: device isolation film

103, 303: tunnel oxide film 104, 304: first polysilicon layer

105, 305: second polysilicon layer 106, 306: floating gate

107, 307: dielectric film 108, 308: third polysilicon layer

108a, 308a: lower third polysilicon layer

109, 309: metal layer 110, 310: control gate

111, 311: hard mask 312: source / drain                 

313: blocking film

The present invention relates to a method of manufacturing a NAND flash memory device, and more particularly, to a method of manufacturing a NAND flash memory device for preventing a line width of a gate line from being narrowed during an etching process for forming a floating gate and a control gate.

In the case of a NAND flash device having a design rule of 70 nm or less, a highly conductive material such as tungsten is introduced into the gate structure to reduce the resistance of the gate line. As such, when the metal material is used, structural problems may occur or equipment may be contaminated due to the high oxidative property and the high volatile material of the metal during the subsequent deposition process or the thermal process. In addition, there is a problem that it is difficult to properly adjust the gate line width due to the drastic reduction of design rules and development limitations of the lithography process.

Referring to the drawings, the above problem will be described in more detail.

1 is a layout view of a typical NAND flash memory array.

2A through 2C are cross-sectional views of devices for describing a method of manufacturing a NAND flash memory device according to the prior art.                         

1 and 2A, a trench type isolation layer 102 is formed in an isolation region of a semiconductor substrate 101, and a floating gate including first and second polysilicon layers 104 and 105 is formed on an active region. Form 106. Here, the first polysilicon layer 104 is isolated by the protrusions of the device isolation layer 102. The second polysilicon layer 105 is formed such that an edge thereof partially overlaps the device isolation layer 102. This is to increase the coupling ratio of the floating gate 106, and since the formation of such a structure is a well known technique, a detailed description thereof will be omitted.

Subsequently, the dielectric film 107, the third polysilicon layer 108 for the control gate, and the metal layer 109 are sequentially formed on the entire structure including the second polysilicon layer 105. The hard mask 111 in which a word line pattern is defined is formed on the metal layer 109.

Here, the metal layer 109 may be formed of tungsten or silicide layer, preferably formed of tungsten.

1 and 2B, the metal layer 109 and the third polysilicon layer 108 are sequentially etched and patterned in the word line direction by an etching process using the hard mask 111 as an etching mask. As the metal layer 109 and the third polysilicon layer 108 are patterned, the lower dielectric layer 107 is partially exposed. As a result, the control gate 110 including the metal layer 109 and the third polysilicon layer 108 is formed.

1 and 2C, the dielectric layer 107, the second polysilicon layer 104, and the first polysilicon layer 103 are sequentially etched by a self-aligned etching method using the hard mask 111. As a result, the floating gate 106 including the first polysilicon layer 104 and the second polysilicon layer 105 is formed, thereby forming a flash memory cell.

Looking at the process step, it can be seen that the thickness of the third polysilicon layer 108 is etched in each region in FIG. 2B. That is, referring to the drawing in the CC ′ direction, the third polysilicon layer 108 is thickly formed in the region between the second polysilicon layers 105, and the third polysilicon is formed on the second polysilicon layer 105. Layer 108 is thinly formed. Therefore, the etching process of the third polysilicon layer 108 should be performed based on the thickness of the third polysilicon layer 108 between the second polysilicon layers 105. For this reason, while the third polysilicon layer 108 is excessively etched on the second polysilicon layer 105, a phenomenon that the lower portion 108a of the third polysilicon layer 108 is thinned occurs.

When the lower portion 108a of the third polysilicon layer 108 is thin in this manner, the second polysilicon layer 105 and the first polysilicon layer 104, which are lower layers thereof, are also etched in a narrow width. This causes ONO smiling, which slows down program speed, and seriously affects the device's electrical characteristics.

In addition, there may be a problem that the structure is deformed or the equipment is contaminated due to the high oxidation and high volatility of the metal contained in the metal layer during the subsequent thermal process or deposition process.

In contrast, in the method of manufacturing a NAND flash memory device according to the present invention, a polysilicon layer is etched only a predetermined thickness during etching of a metal layer and a polysilicon layer to form a control gate, and then a barrier layer is formed on the sidewalls of the metal layer and the polysilicon layer. Forming the control gate by fully patterning the polysilicon layer in the etching process in the state of forming a, and forming a floating gate by etching the lower layer in a self-aligned etching process, even if the etching thickness of the polysilicon layer is different for each region It is possible to prevent the excessive etching of the polysilicon layer in the portion to prevent the gate line from thinning, and to prevent structural deformation due to volatile substances generated from the metal layer, equipment contamination due to metal contamination sources, and deterioration of device characteristics. .

In the method of manufacturing a NAND flash memory device according to an embodiment of the present invention, forming a device isolation film in the device isolation region of the semiconductor substrate, forming a tunnel oxide film and a polysilicon layer for the floating gate in the active region, Sequentially forming a dielectric film, a control silicon polysilicon layer, and a metal layer on the entire structure including the silicon layer; etching the metal layer into a gate line pattern; and forming the control silicon polysilicon layer according to the gate line pattern. Primary etching by a predetermined thickness, forming a blocking film for preventing sidewall etching of the polysilicon layer for control gates, secondary etching the control gate polysilicon layer to form a gate line pattern, Patterning a polysilicon layer for the dielectric film and the floating gate, and active zero To and forming a source / drain.                     

In the above description, the floating silicon polysilicon layer is formed of a first polysilicon layer isolated by a protrusion of a device isolation layer protruding higher than a semiconductor substrate, and a first polysilicon layer formed on the first polysilicon layer and having an edge overlapping an edge of the device isolation layer. It consists of 2 polysilicon layers.

The metal layer may be formed of a metal layer or silicide layer, and the metal layer may be formed of tungsten or cobalt silicide.

The primary etching of the control gate polysilicon layer etches the control gate polysilicon layer so that the control gate polysilicon layer is patterned only by a predetermined thickness on the floating gate polysilicon layer, and may be etched by a thickness of 100 μs to 1000 μs. Can be.

The blocking film may be formed of any one of oxide, nitride or oxynitride.

The secondary etching process of the polysilicon layer for the control gate may be performed by an etching process using plasma. In this case, N ₂ may be added to the plasma to suppress sidewall etching of the polysilicon layer for the control gate during the secondary etching process, or He may be added to the plasma to improve plasma stabilization or polymer removal ability.

In the second etching process of the polysilicon layer for the control gate, HBr gas is used as the main etching gas, and O ₂ may be added to control the etching selectivity.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

On the other hand, when a film is described as being "on" another film or semiconductor substrate, the film may exist in direct contact with the other film or semiconductor substrate, or a third film may be interposed therebetween. In the drawings, the thickness or size of each layer is exaggerated for clarity and convenience of explanation. Like numbers refer to like elements on the drawings.

3A to 3E are cross-sectional views of devices for describing a method of manufacturing a NAND flash memory device according to an embodiment of the present invention.

1 and 3A, a trench type isolation layer 302 is formed in an isolation region of a semiconductor substrate 301, and a floating gate including first and second polysilicon layers 304 and 105 is formed on an active region. 306 is formed. Here, the first polysilicon layers 304 are separated from each other by the protrusions of the device isolation layer 302. The second polysilicon layer 305 is formed such that an edge thereof partially overlaps the device isolation layer 302. This is to increase the coupling ratio of the floating gate 306. Since the formation of such a structure is a well known technique, a detailed description thereof will be omitted.

Subsequently, the dielectric film 307, the third polysilicon layer 308 for the control gate, and the metal layer 309 are sequentially formed on the entire structure including the second polysilicon layer 305. The hard mask 311 in which a word line pattern is defined is formed on the metal layer 309.

The metal layer 309 may be formed of a single metal material or a silicide layer having low resistance, and specifically, may be formed of a tungsten or cobalt silicide layer.

1 and 3B, the metal layer 309 is patterned in the word line direction by an etching process using the hard mask 311 as an etching mask. Subsequently, the third polysilicon layer 308 is etched, but the third polysilicon layer 308 is first etched only by a predetermined thickness. In this case, the etching thickness of the third polysilicon layer 308 is determined in consideration of the thickness of the third polysilicon layer 308 of the thinnest portion formed on the second polysilicon layer 305. For example, the third polysilicon layer 308 is etched only by a predetermined thickness so that the third polysilicon layer 308 is not completely patterned on the second polysilicon layer 305. For example, the third polysilicon layer 308 may be etched by a thickness of 100 kPa to 1000 kPa.

1 and 3C, a barrier layer 313 is formed over the entire structure including exposed sidewalls of the third polysilicon layer 308 and the metal layer 309. The barrier layer 313 is excessively etched in the third polysilicon layer 308 having a thin thickness in the process of further etching the third polysilicon layer 308 for complete patterning of the third polysilicon layer 308. It is formed to prevent this from occurring. In addition, the blocking layer 313 may block exposure of the metal layer 309 to block oxidation of the metal layer 309 or release of volatile material from the metal layer 309 in a subsequent thermal process.                     

That is, the blocking film 313 is formed to prevent deformation of the pattern due to the subsequent process.

The blocking film 313 may be formed of an oxide, a nitride, or an oxynitride, and may be formed to have a thin thickness of about 5 μs to about 200 μs.

1 and 3D, the third polysilicon layer 308 is further etched to completely pattern the third polysilicon layer 308. As a result, the control gate 310 including the metal layer 309 and the third polysilicon layer 308 is formed. A portion of the lower dielectric layer 307 is exposed while the third polysilicon layer 308 is completely patterned. As the third polysilicon layer 308 is further etched, the blocking layer 313 remains only on sidewalls of the patterns formed on the substrate.

Here, the etching process of the third polysilicon layer 308 may be performed in-situ while maintaining the vacuum state without time delay in the same chamber after forming the blocking layer 313. Polysilicon may be etched in a number of ways, and these techniques are already well known, and thus detailed descriptions thereof will be omitted.

Meanwhile, while the third polysilicon layer 308 thickly formed between the second polysilicon layers 305 is etched, it is etched on the sidewall of the third polysilicon layer 308 thinly formed on the second polysilicon layer 305. Will be affected. That is, even if the blocking film 313 is formed on the sidewall of the third polysilicon layer 308, since the additional etching process is performed based on the thick portion of the third polysilicon layer 308, the patterned second polysilicon layer is completed. The sidewalls of the third polysilicon layer 308 on the upper portion 305 may be affected by the excessive etching.                     

In order to minimize this, N ₂ may be added to the plasma gas during additional etching of the third polysilicon layer 308. In addition, He may be added to the plasma gas in order to increase the etching uniformity or to improve the plasma stabilization or polymer removal ability when the third polysilicon layer 308 is etched. When the third polysilicon layer 308 is etched using plasma as described above, the etching process of the third polysilicon layer 308 may be an inductively coupled plasma (ICP) type, an electron cyclotron resonance (ECR) type, or a microwave. ) And CCP (Capacitively Coupled Plasma) types may be implemented in any one of the equipment.

If HBr is used as the main etching gas when the third polysilicon layer 308 is etched, O ₂ may be added to control the etching selectivity between the insulating layer and the polysilicon.

1 and 3E, the dielectric layer 307, the second polysilicon layer 304, and the first polysilicon layer 303 are sequentially etched by a self-aligned etching method using the hard mask 311. As a result, the floating gate 306 formed of the first polysilicon layer 304 and the second polysilicon layer 305 is formed.

Subsequently, the source / drain 312 is formed by an ion implantation process. As a result, a flash memory cell is formed.

As described above, in the present invention, after etching the metal layer and the polysilicon layer to form the control gate, the polysilicon layer is etched only a predetermined thickness, and then the polysilicon is formed in the barrier layer formed on the sidewalls of the metal layer and the polysilicon layer. The control gate is formed by completely patterning the layer by an etching process, and the floating layer is formed by etching the lower layer by a self-aligned etching process, so that even if the etching thickness of the polysilicon layer is different for each region, the polysilicon layer is excessive in the thin part. The etching process can be prevented from being thinned, and the structural deformation caused by the volatile material generated from the metal layer, the equipment contamination by the metal contamination source, and the deterioration of device characteristics can be prevented.

Claims (11)

Forming a device isolation film in the device isolation region of the semiconductor substrate, and forming a tunnel oxide film and a polysilicon layer for the floating gate in the active region; Sequentially forming a dielectric film, a control gate polysilicon layer, and a metal layer on the entire structure including the floating gate polysilicon layer; Etching the metal layer to be patterned according to a gate line pattern; First etching the thinned thickness of the polysilicon layer for the control gate between the patterned metal layers; Forming a blocking film for preventing sidewall etching of the poly-etched polysilicon layer which is primary etched; Second etching the polysilicon layer for the control gate to be patterned according to the gate line pattern; Patterning the dielectric film and the polysilicon layer for the floating gate; And Forming a source / drain in the active region. The method of claim 1, The floating silicon polysilicon layer is formed on the first polysilicon layer and is separated by the protrusion of the device isolation layer protruding higher than the semiconductor substrate, and the edge overlaps the edge of the device isolation layer. A method of manufacturing a NAND flash memory device comprising a second polysilicon layer. The method of claim 1, A method for manufacturing a NAND flash memory device in which the metal layer is made of a single metal material or silicide layer. The method of claim 1, And a metal layer made of tungsten or cobalt silicide. The method of claim 1, The primary etching of the control gate polysilicon layer is a method of manufacturing a NAND flash memory device for etching the polysilicon layer for the control gate so that the thickness of the control gate polysilicon layer on the floating gate polysilicon layer is thinner. . The method according to claim 1 or 5, And etching the control gate polysilicon layer by a thickness of 100 μs to 1000 μs during the first etching of the control gate polysilicon layer. The method of claim 1, The blocking film is formed of any one of an oxide, nitride or oxynitride. The method of claim 1, The second etching process of the polysilicon layer for the control gate is a manufacturing method of the NAND flash memory device which is performed by the etching process using a plasma. The method of claim 8, And adding N ₂ to the plasma to suppress sidewall etching of the control gate polysilicon layer during the second etching process of the control gate polysilicon layer. The method of claim 8, And adding He to the plasma in order to improve plasma stabilization or polymer removal capability in the secondary etching process of the control gate polysilicon layer. The method of claim 1, The method of manufacturing a NAND flash memory device using HBr gas as the main etching gas in the secondary etching process of the control silicon polysilicon layer, and O ₂ is added to adjust the etching selectivity.

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