KR100684471B1 - Self-repair method and device of built-in SRAM - Google Patents

Abstract

The present invention relates to a self-recovery method and device of the internal SRAM, and more specifically, to determine whether the memory failure through the self-test of the built-in memory and to replace the failed portion of the memory to the spare memory to allow the user to It's about memory self-healing that allows us to use it like normal memory.

Self-recovery device of the built-in SRAM of the present invention includes a self-fault test circuit for determining whether the failure occurred at any location of the main memory divided into blocks; A spare memory relocation circuit configured to receive a signal of a failure generated in the self-failure test circuit, store a failure block of the main memory, arrange a recovery block at an arbitrary location of the spare memory, and store the allocated address; According to the signal of the spare memory rearrangement circuit there is a technical feature comprising a self-recovery recovery circuit to replace the recovery block of the spare memory and the failure block of the main memory.

Therefore, the self-recovery method and apparatus of the embedded SRAM according to the present invention operates as a circuit independent of the physical structure of the memory by normally operating the SOC in the event of a memory failure, and yields the memory by reusing expensive memory using a spare memory. Has the effect of increasing.

Embedded, memory, BIST, BISR, BIRA, SRAM

Description

Build-in self repair method and device for embedded SRAM

1 is a block diagram of a method of relocating a failed memory using an existing spare memory.

2 is an existing BISR structure.

3 is a basic conceptual diagram of block relocation.

4 is a view showing a self-repairing device of the built-in SRAM according to the present invention.

5 is a BIST and BISR integrated structure process according to the present invention.

6 is a block diagram of a BIST according to the present invention.

7 is a structure diagram of a BIRU according to the present invention.

8 is an example of block information for spare memory allocation according to the present invention.

9 is a block diagram of a BISR according to the present invention.

10 is a structural diagram of a comparator and a spare row address selector according to the present invention.

11 is a structural diagram of a failed block selector according to the present invention.

12 is a structural diagram of a spare block selector and a read / write block selector according to the present invention.

13 is a structural diagram of a data output block selector according to the present invention.

<Description of the symbols for the main parts of the drawings>

100: BIST 120: BISR

130: spare memory 140: main memory

200: BIST 210: control module

220: address generation module 230: data generation module

240: data comparison module

The present invention relates to a self-recovery method and device of the internal SRAM, and more specifically, to determine whether the memory failure through the self-test of the built-in memory and to replace the failed portion of the memory to the spare memory to allow the user to It's about memory self-healing that allows us to use it like normal memory.

As semiconductor process technology advances and VLSI improves in performance, more and more cores are becoming SOC (System On Chip). Among them, internal memory accounts for 80-90% of the total number of SOC transistors, and testing of internal memory is a new problem when developing SOC. As a result, memory test becomes more important in SOC than ever before, and there is a need for a technology that can increase memory yield by reusing expensive memory as spare memory, in addition to judging whether memory is broken or not.

Inside the SOC, the BIST (Built-In Self Test) circuit for testing the SOC itself and the test result by the BIST are used to determine whether it is recoverable, and the BISR (Built-In) to perform its own recovery in the chip by software. In Self Repair circuit can be used to reuse the failed memory.

The BISR configuration requires the BIST technique, which is the most widely used method to determine whether the internal memory is broken, and the BIRU (Built-In Remapping Unit) circuit, which enables the proper placement of the failed main memory cell in the spare memory. Do.

The method of obtaining spare memory is divided into hard redundancy and soft redundancy. Hard redundancy implements the storage of information of memory elements to be relocated as a fuse, and the fuse includes a laser fuse, an electrical fuse, and an EPROM memory. Laser fuses, electrical fuses, and EPROMs are lasers or electronically cut into chips so that the spare memory can store the values in the main memory. Spare memory made of chips can use spare memory semi-permanently for one memory, but it requires other external test equipment and it is not easy to use spare memory for other memory.

Soft redundancy, on the other hand, is a hassle to run BIST and BIRU modules to relocate between spare memory and faulty main memory when the chip is powered up. However, there is no need to use external test equipment, and spare memory can be flexibly applied to all main memories.

1 is a structural diagram of relocating a failed memory using an existing spare memory. After dividing the main memory and spare memory into blocks based on columns, if a cell in the main memory block fails, the entire block containing the failed cell is replaced with a spare memory block. When replacing failed memory with spare memory, main memory and spare memory are relocated into blocks of the same row. The disadvantage of the conventional method is that the memory can be repaired only in the same column after dividing into blocks. Therefore, if the same column of main memory has a lot of failures, it will be replaced by the same column in the spare memory. Nevertheless, there is a lot of disadvantages and problems in terms of cost and time due to unnecessary memory consumption because it is not recoverable.

2 is an existing BISR structure. It can be seen that the row address r of the main memory and the spare memory of the row address m, the column address n, and the block address l is simplified. In other words, the memory has m word lines (W ₀ -W _M-1 ), n bit lines, and l virtual row banks (VRB _{0 -} VRB _l-1 ). R spare memory rows have been added for memory self-recovery If the spare memory address access bit is 2 and the VRB is 4, then there are 16 spare memory blocks because a row has 4 blocks. The basic mechanism of self-healing is to replace a failed block with spare memory blocks in the same bank.If the failure occurs, four rows fail in the conventional method of replacing an entire row. This required four spare memory rows, but with virtual blocks, two rows can be self-recovered, so block-by-block recovery is more efficient than row-by-row recovery. It can be seen that having the rate. This method is difficult, that is, it is difficult to test with the input of the memory, output to the test pinman moreuna whether the proposed method is useful when the memory fundamentally designed after the memory was created.

Unlike the existing test equipment, BISR does not perform physical recovery, but instead, the recovery algorithm is installed on the chip itself to determine whether it can be recovered, and then, if recoverable, performs software logical recovery.

Among the circuits having the prior art BIST and BISR, Korean Patent Application Publication No. 2002-68768, "Semi-conductor device having a built-in self repair circuit for built-in memory," uses hard redundancy in a method of implementing a spare memory. Although it can be used semi-permanently for one memory, there is a problem that other external test equipment is needed and other memory is not easy to use, and by using a plurality of low redundancy and column redundancy, there was unnecessary memory consumption in the block relocation method. Republic of Korea Patent Publication No. 2001-76937 In addition, there is a problem that unnecessary memory consumption by using a plurality of low redundancy and column redundancy.

Accordingly, the present invention is to solve the above-mentioned disadvantages and problems of the prior art, by dividing the main memory of the built-in SRAM into blocks to determine whether or not the main memory failure using a self-fault test circuit, SUMMARY OF THE INVENTION An object of the present invention is to provide a self-healing method and apparatus for self-recovering an internal SRAM that provides transparency to a user by relocating a block included in a generated cell to an arbitrary location of a spare memory.

The object of the present invention is a self-fault test circuit for determining whether or not the failure occurred at any position of the main memory divided into blocks; A spare memory relocation circuit configured to receive a signal of a failure generated in the self-failure test circuit, store a failure block of the main memory, arrange a recovery block at an arbitrary location of the spare memory, and store the disposed address; And a self failure recovery circuit configured to replace a recovery block of the spare memory and a failure block of the main memory according to a signal of the spare memory relocation circuit.

The above object of the present invention is to determine whether or not the failure occurred at any position of the main memory divided into blocks; Receiving a failure signal generated by the self failure test circuit, storing a failure block of the main memory, placing a recovery block at an arbitrary location of the spare memory, and storing the disposed address; And replacing a recovery block of the spare memory and a failure block of the main memory according to a signal of the spare memory relocation circuit.

Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

3 is a basic conceptual diagram of block relocation according to the present invention. Referring to FIG. 3, when one cell or several cells of the main memory fail, all blocks included in the cell are rearranged to blocks of the spare memory, and the memory fails only in the same column as in FIG. 1. By recovering the error, many failures occur in the same column, and even though there is memory to recover in another column of the same row, it cannot be recovered, thereby preventing the memory yield from dropping. In the present invention, BIST, BIRU, and BISR divide a main memory having a 5-bit address and 1 word (32-bit) and a spare memory having a 2-bit address and 1 word (32-bit) into 4 blocks (8 bits) in 1 word (32 bits). Explain.

4 is a view showing a self-repairing device of the built-in SRAM according to the present invention. Referring to FIG. 4, after test data is applied to a point indicated by a test address in the main memory 140 in the BIST 100 circuit, test data and data read from the main memory (Reference Data) Compared to determine whether the main memory 140 has a failure.

If a failure does not occur, normal operation is performed, and if a failure occurs, the number of blocks including the failed cell is transmitted to the BIRU 110 through a faulty group count. If the BIRU can determine the state of the spare memory 130 and then relocate it, the BIRU transmits an active high value to the BIST 100 through a spare memory enable signal. The BIST 100 circuit receiving the signal provides the BIRU 110 with information including the failed address FA and the failed cell FB in the main memory 140.

Upon completion of the BIST 100 operation, the BIRU 110 passes the information FA, FB, SA, SB on the failure of the main memory 140 to the BISR 120.

5 is a BIST and BISR integrated structure process according to the present invention. Referring to FIG. 5, a series of processes are performed when power is supplied to a circuit. Alternatively, the test mode is started by a start signal. When the integrated structure begins, BIST creates a test pattern using an algorithm.

First of all, the failure of spare memory is examined and the spare memory that is found is disabled through BIRU. The primary reason for testing spare memory is to avoid recovery failures when spare memory is present when memory relocation occurs due to a failure of main memory.

When the spare memory test is completed, the main memory test is started. If a failure is detected during the test, the BIRU sends the information of the block containing the failed cell to the BISR. At the end of the full memory test, the test mode transitions from BISR mode to normal memory operation.

6 is a BIST configuration diagram according to the present invention. Referring to FIG. 6, the BIST 200 enables a test to be spontaneously performed by the chip itself without receiving a control signal or test data from the outside.

The memory BIST 200 circuit used in the present invention includes a control module 210 for controlling the operation of the BIST 200 circuit, a test address generation module 220 for generating an address of a memory to which a test pattern is applied, and a test pattern. Test data generation module 230 to generate, and a data comparison module 240 for comparing the test results. The control module 210 generates a control signal required in the test mode. The control module 210 has a state machine for background data defined for each memory and an execution state machine for the algorithm described in the configuration file.

The performing state machine repeats one March step until "EndOfAddress" is generated from the address generation module 220. The background data state machine moves to the next state when the "EndOfMarch" signal is generated from the execution state machine, and generates a signal "EndOfTest" in the background data state machine according to the memory currently being tested.

The control module 210 generates a control signal for the memory and an "AglEn" signal for the address generation module 220 in each state of the performance data state machine, and the data generation module 230 generates a "DglEn" signal. . And generates a "DclEn" signal for the data comparison module 240. The generated "AglEn", "DglEn" and "DclEn" signals activate the operation of each module. Address and test data are generated.

The address generation module 220 generates a memory address to which test data is applied by a signal "AglEn" generated from the control module 210 in the test mode. The address used in the memory test algorithm changes in the direction of increasing or decreasing address from address 0 to the last address.

Therefore, we made a counter that repeats the address from address 0 to the last address, and used the counter output's complement when the address in decreasing direction is needed. In addition, when multiple memories are used, the last memory address can be adjusted to match the size of the address of the memory currently being tested.

The data generation module 230 generates a test pattern by the "DGLEnable" signal generated from the control module 210. The "Data" signal is the test data applied to the actual memory. When the value of the "DglEn" signal is 0, the data register value is left as it is. If the value is 1, the data register complement value is output. The data register value refers to data for the memory currently being tested, and in the case of the memory defining the background data, it refers to the background data required in the current step.

The data comparison module 240 performs an exclusive logical OR operation on the value read from the memory after the test result and the reference value generated by the data generation module 230, and then performs an OR operation on the comparison register value. After that, save the result. The comparison result is stored in the comparison register when the "DclEn" signal is activated at the edge of the clock.

When the "ShiftEnable" signal is activated at the edge of the clock, the comparison register performs a shift operation, which transfers the test result to the ShiftOut port and outputs the final test result value externally through IEEE 1149.1 or IEEE P1500. do. In the integration module with BISR, if the data is not the same after comparison, it is regarded as a failure, and then the address value of the main memory and the block value are transmitted to the BIRU module.

7 is a structure diagram of a BIRU according to the present invention. As shown in FIG. 7, the BIRU may be divided into two parts, a process part and an address remapping unit (ARU). If the main memory of the BIST is identified in the BIST data comparison module, the number of blocks containing the failed cell is sent to the BIRU process. The process compares the number of failed blocks (Faulty Group Count) with the available spare memory (Valid & Fail Count), and if the number of failed blocks is less than the number of spare memory blocks, the value of the failed block in main memory (FB). : Faulty Block; in order of block; '1000', '0100', '0010', '0001'), main memory address value (FA: Faulty Address), spare memory address value (SA: Spare Address) Is stored in the ARU temporary register, and then the value of the spare memory block (SB: Spare Block) is also stored.

If the number of failed blocks is larger, check whether the spare memory address at that time is the last spare memory address. If not, increase the spare memory address to the next address and compare again. If the spare memory address was last, it means that there are more blocks of failed cells in main memory than the size of the spare memory that cannot be relocated, and there is no need to run BISR.

8 is an example of block information for spare memory allocation according to the present invention. Referring to FIG. 8, a spare memory having an address of 2 bits and one word (32 bits) is divided into four blocks. 2 is an example in which the respective block relocation setting values are marked in the spare memory for relocating the failed block in the main memory to the spare memory. BISR will be described as an example as above.

9 is a block diagram of a BISR according to the present invention. Referring to FIG. 9, when the control signal of the main memory has RAMEN (RamEnable) = '0', WE (WriteEnable = '0', OE (Output Enable) = '1', data is written to the main memory and RAMEN (RamEnable) = '0', WE (WriteEnable) = '1', OE (Output Enable) = '0' read data from main memory Spare memory to use spare memory due to cell failure in main memory The domain memory must perform the same read and write operations during read and write operations.

In the present invention, the main memory and the spare memory are divided so that the main memory and the spare memory can read and write at the same time with the / WE signal.

10 is a structural diagram of a comparator and a spare row address selector according to the present invention. Referring to FIG. 10, when writing data to the main memory, an address is selected and data is written to the selected address. At this time, it is possible to know whether or not there is a failure in the selected address through the circuit. The comparator circuit compares the FA values of each block from the BIRU with the address that accessed the main memory in parallel. Exclusive logical sum (XOR) operation is performed on the FA value and the address value, respectively, and grouped by the OR gate.

If the address matches, it outputs a '0' value, and if it is not the same, it outputs a '1'. When reading or writing data with '00010' address in main memory, '1111111111111000' value is output from the comparator circuit. This output has inputs to the row address selector circuit, the spare block selector circuit, and the failed block selector circuit, and selects the MUX so that the BISR circuit can be output without operating when accessing a word in the main memory without a fault. It is applied as the input value of the line.

The row address selector circuit receives the R row address value from the BIRU in units of blocks and applies the output value of the comparator to the selection line of the three-phase buffer of the row address selector circuit and sets the value '00' through the OR gate. Will print. This value is applied to the spare memory as an address value.

11 is a structural diagram of a failed block selector according to the present invention. Referring to FIG. 11, failed block values in a BIRU are input to the three-phase buffer in units of blocks. The selection line of the three-phase buffer at this time is determined as '1111111111111000' which is an output value of the comparator circuit. The values that can be output to the output of the three-phase buffer by the select line are '1000', '0010' and '0001'. Pass this value to the OR gate and apply the value '1011' to the input of the read / write block selector and the data output block selector.

The data input to the main memory is divided into the number of blocks, and one data block input to the main memory is input as many as the input of the spare memory. The spare memory input block is selected by the output value of the read / write block selector. Decide

12 is a structural diagram of a spare block selector and a read / write block selector according to the present invention. 12, the SB value in the BIRU is input to the three-phase buffer input of the spare block selector circuit in units of blocks. The selection line of the three-phase buffer at this time is set to '1111111111111000', which is an output value of the comparator circuit. The values that can be output to the output of the three-phase buffer by the select line are '0100', '0010' and '0001'.

The value '0111' after the OR is applied as the input value of the read / write block selector circuit. The read / write block selector circuit receives the OR of the failed block selector circuit and the spare block selector circuit as inputs to the multiplexing (MUX) circuit. The select line of the multiplexer (MUX) has a value of / WE, which is a control signal of the main memory, and has a value of '1' for the read operation of the main memory and an opposite value of '0' for the write operation. When the select line of the multiplexer (MUX) is determined by the value of / WE, each multiplexed (MUX) output value enters the input of the divider circuit. The values output through the divider circuit pass through the branch circuit and enter the spare block selector circuit. The input values are applied to the selection line of the three-phase buffer and write the failed block in the main memory to the spare memory.

13 is a structural diagram of a data output block selector according to the present invention. Referring to FIG. 13, when a faulty position of the main memory is read, the value of the block written to the spare memory and the value of the main memory are replaced. The word value of the spare memory is output to the data output block selector input in units of blocks.

Spare memory word values input to the data output block selector circuit have the output value of the read / write block selector and the failed block selector circuit output value to select the position block to be replaced with the word value output from the main memory. It is applied to the three-phase buffer of the selector circuit and the select line of the multiplexer (MUX).

When the values ('0000', '0100', '0100', '0010', '0001') from the read / write block selector are input to the selection line of each three-phase buffer, the data values output from the spare memory are selected. The location is separated by a line. The data values output from the main memory with the failed block are multiplied by the value of '1011' from the failed block selector in order to be replaced by the data values from the spare memory and the three-phase buffer and the OR gate. The data value replaced by the MUX goes to the output value of the main memory without any trouble. In case of reading the address without fault, '1111111111111111' value comes out from the comparator and the value is bypassed without going through the circuit of BISR with the select line of the multiplexer (MUX) hanging at "DataOut".

Therefore, the self-recovery method and apparatus of the internal SRAM according to the present invention normally operate the SOC in case of any memory failure, and exist as an independent circuit in the physical structure of the memory to reuse the expensive memory as a spare memory, thereby yielding the memory. This has the advantage of increasing the cost, and has the effect of reusing broken memory.

Claims (14)

In the internal SRAM-based self-healing device, A self-failure test circuit for detecting the presence or absence of a failure of the spare memory and a failure occurring at an arbitrary position of the main memory divided into blocks; After receiving the failure signal generated in the self failure test circuit, the information of the failure block of the main memory included in the failure signal is stored, and a recovery block is placed at an arbitrary position of the spare memory and the allocated address A spare memory relocation circuit for storing a; And Self-failure recovery circuit for replacing the failure block of the main memory with the recovery block of the spare memory in accordance with the signal transmitted from the spare memory relocation circuit Self-repairing device of the built-in SRAM. The method of claim 1, The self-failure test circuit is a self-healing device of the built-in SRAM comprising a control module, an address generation module, a data generation module and a data comparison module. The method of claim 2, wherein the control module A performance state machine for performing algorithms needed to self test a memory failure; And Background data state machine for setting a background state by receiving a signal transmitted from said performing state machine Self-repairing device of built-in SRAM. The method of claim 2, The address generation module is a self-recovery device of the internal SRAM capable of receiving a signal from the control module to read and write a test data value at the corresponding address location. The method of claim 2, The data generation module is a self-recovery device of the built-in SRAM to generate a test pattern after receiving a signal from the control module, and to generate the data or background data for the memory under test to the memory. The method of claim 2, After the test result, the data comparison module performs an exclusive logical sum (XOR) operation on the value stored in the memory and the data value generated by the data generation module, and performs a logical OR operation on the comparison register value. Self-recovery device of the built-in SRAM for transmitting the value of the failure block to the spare memory relocation circuit in comparison with the value measured in the recovery circuit. The method of claim 6, The spare memory relocation circuit includes a process and an ARU. The method of claim 7, wherein The process receives the number of available blocks of the first address in the spare memory from the ARU, and then compares the number of failed blocks in the data generation module with the number of blocks available for the spare memory. SRAM's self-healing device. delete In the self-recovery method based on the built-in SRAM, (a) detecting, by the self-failure test circuit, whether or not the spare memory is broken and a failure occurred at an arbitrary position of the main memory divided into blocks; (b) receiving a failure signal transmitted from the self-failure test circuit in a spare memory rearrangement circuit, storing information of a failure block of the main memory included in the failure signal, and restoring to an arbitrary location of the spare memory; A relocation step of placing the block and storing the placed address; And (c) replacing a failure block of the main memory with a recovery block of the spare memory in a self-failure recovery circuit according to a signal generated in the relocation step; Self-recovery method of built-in SRAM containing a. The method of claim 10, wherein step (b) A process of receiving the number of available blocks of a first address in the spare memory from an ARU and comparing the number of failed blocks with the number of blocks available for the spare memory; And An ARU process of storing a failed block value of the main memory, an address value of the main memory, and an address value of the spare memory in an ARU temporary register when the number of failed blocks is smaller than the number of spare memories. Self-recovery method of built-in SRAM containing a. delete delete The method of claim 10 or 11, In the step (c), when the main memory performs a read and write operation in order to use the data value of the failed main memory as the spare memory instead of the setting value of the ARU process in the step (b), Spare memory self-recovery method of the internal SRAM that performs the same read and write operations as the main memory.

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