KR100680705B1 - Driving apparatus and driving method of plasma display panel - Google Patents

Abstract

The present invention relates to a driving apparatus and a driving method of a plasma display panel. More particularly, when a scan reference voltage is supplied to a scan electrode in an address period, the scan reference voltage rises with a slope, thereby reducing the generation of noise. The present invention relates to a display apparatus and a driving method thereof, which may reduce noise and improve driving efficiency, and also prevent electrical damage of circuit elements, thereby reducing manufacturing costs of the circuit elements.

The plasma display apparatus of the present invention includes a plasma display panel including a plurality of scan electrodes, a scan reference voltage supply unit and a scan reference voltage supply unit supplying a scan reference voltage rising with a slope for a predetermined period of the address period after the set down period. And a driving signal output unit configured to output the scan reference voltage to be supplied to the scan electrode of the plasma display panel through a predetermined switching operation.

Description

Driving device and driving method of plasma display panel {Device and Method for Driving Plasma Display Panel}

1 is a perspective view showing the structure of a typical plasma display panel.

2 is a diagram illustrating a method in which a conventional plasma display panel implements image gray scale.

3 is a view showing a driving waveform generated by a driving apparatus of a conventional plasma display panel.

4 is a view for explaining a scan driving device among driving devices of a conventional plasma display panel;

FIG. 5 is a diagram for explaining a scan reference voltage supplied in an address period in a conventional plasma display panel driving apparatus. FIG.

FIG. 6 is a view for explaining noise generated by a scan reference voltage supplied by the driving apparatus of the conventional plasma display panel to the scan electrodes Y ₁ to Y _m in an address period.

Fig. 7 is a diagram for explaining the configuration of a scan driving device of a plasma display panel of the present invention.

8 is a view for explaining a driving waveform of the driving apparatus of the plasma display panel of the present invention;

9 is a view for explaining in more detail the operation of the waveform generator in the driving apparatus of the plasma display panel of the present invention.

FIG. 10 is a view for explaining noise generated due to scan reference voltages supplied to scan electrodes Y ₁ to Y _m in an address period among driving waveforms of a plasma display panel of the present invention; FIG.

FIG. 11 is a diagram illustrating scan electrodes Y ₁ to Yn formed in a plasma display panel divided into four scan electrode groups in order to explain a method of driving a plasma display panel according to the present invention.

12 is a view for explaining an example of dividing a plurality of scan electrodes formed in a plasma display panel according to the present invention into a scan electrode group including one or more scan electrodes;

13 is a view for explaining the magnitude of the resistance of the waveform generator corresponding to the scan electrode group in the driving apparatus of the plasma display panel according to the present invention;

14A to 14B are diagrams for explaining an example of a change in time when the scan reference voltage Vsc rises according to the resistance value of the waveform generator.

15A to 15B are views for explaining another example of a change in time when the scan reference voltage Vsc rises according to the resistance value of the waveform generator.

<Explanation of symbols for the main parts of the drawings>

700: energy recovery circuit unit 710: setup supply unit

720: scan reference voltage supply unit 721: waveform generation unit

730: drive signal output unit 740: set down supply unit

750: negative scan voltage supply unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel. More particularly, when a scan reference voltage is supplied to a scan electrode in an address period, driving of the plasma display panel reduces the generation of noise by adjusting the scan reference voltage. An apparatus and a driving method are provided.

In general, a plasma display panel is a partition wall formed between a front panel and a rear panel to form one unit cell, and each cell includes neon (Ne), helium (He), or a mixture of neon and helium (Ne + He) and An inert gas containing the same main discharge gas and a small amount of xenon is filled. When discharged by a high frequency voltage, the inert gas emits vacuum ultraviolet rays to emit phosphors formed between the partition walls, thereby realizing an image. Such a plasma display panel has a spotlight as a next generation display device because of its thin and light configuration.

1 illustrates a structure of a general plasma display panel.

As shown in FIG. 1, the plasma display panel includes a front panel in which a plurality of sustain electrode pairs formed by pairing a scan electrode 102 and a sustain electrode 103 are arranged on the front glass 101, which is a display surface on which an image is displayed. 100 and the rear panel 110 on which the plurality of address electrodes 113 are arranged so as to intersect the plurality of storage electrode pairs described above on the rear glass 111 forming the rear surface are coupled in parallel with a predetermined distance therebetween.

The front panel 100 is made of a scan electrode 102 and a sustain electrode 103, that is, a transparent electrode (a) formed of a transparent ITO material and a metal material to mutually discharge and maintain light emission of the cells in one discharge cell. The scan electrode 102 and the sustain electrode 103 provided as the bus electrode b are included in pairs. The scan electrode 102 and the sustain electrode 103 are covered by one or more upper dielectric layers 104 that limit the discharge current and insulate the electrode pairs, and facilitate discharge conditions on top of the upper dielectric layer 104. In order to do this, a protective layer 105 on which magnesium oxide (MgO) is deposited is formed.

The rear panel 110 is arranged in such a manner that a plurality of discharge spaces, that is, barrier ribs 112 of a stripe type (or well type) for forming discharge cells are maintained in parallel. In addition, a plurality of address electrodes 113 are arranged in parallel with the partition wall 112 to perform address discharge so that the inert gas in the discharge cell generates vacuum ultraviolet rays. On the upper side of the rear panel 110, red (R), green (G), and blue (B) phosphors 114 which emit visible light for image display during sustain discharge are coated. A lower dielectric layer 115 is formed between the address electrode 113 and the phosphor 114 to protect the address electrode 113.

A method of implementing image gradation in the plasma display panel having such a structure is shown in FIG. 2.

2 is a diagram illustrating a method of implementing image grayscale of a conventional plasma display panel.

As shown in FIG. 2, in the conventional method of expressing a gray level of a plasma display panel, a frame is divided into several subfields having different number of emission times, and each subfield is a reset period (RPD) for initializing all cells again. ) Is divided into an address period APD for selecting a cell to be discharged and a sustain period SPD for implementing gradation according to the number of discharges. For example, when displaying an image with 256 gray levels, a frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8 as shown in FIG. 2, and eight subfields. Each of the SFs SF1 to SF8 is divided into a reset period, an address period, and a sustain period.

The reset period and the address period of each subfield are the same for each subfield. The address discharge for selecting the cells to be discharged is caused by the voltage difference between the address electrodes and the transparent electrodes that are the scan electrodes Y ₁ to Y _m . The sustain period is increased at a rate of 2 ⁿ ( ^where n = 0, 1, 2, 3, 4, 5, 6, 7) in each subfield. In this way, since the sustain period is different in each subfield, the gray scale of the image is expressed by adjusting the sustain period of each subfield, that is, the number of sustain discharges.

A driving method of a conventional plasma display panel according to the general image gray scale representation method is as shown in FIG. 3.

3 is a diagram illustrating a driving waveform generated by a driving apparatus of a conventional plasma display panel.

As shown in Fig. 3, the plasma display panel erases the reset period for initializing all the cells, the address period for selecting the cells to be discharged, the sustain period for maintaining the discharge of the selected cells, and the wall charges in the discharged cells. It is divided into an erase period for driving.

In the reset period, the rising ramp waveform Ramp-up is simultaneously applied to all the scan electrodes Y1 to Ym in the setup period. This rising ramp waveform causes weak dark discharge within the full discharge cells. By this setup discharge, positive wall charges are accumulated on the address electrodes X ₁ to X _n and the sustain electrodes, and negative wall charges are accumulated on the scan electrodes Y1 to Ym.

During the set-down period, after the rising ramp waveform is supplied, the falling ramp waveform (Ramp-down) starts to fall from the positive voltage lower than the peak voltage of the rising ramp waveform and falls to a specific voltage level below the ground (GND) level voltage. By generating a weak erase discharge in the inside, the wall charges excessively formed in the scan electrodes Y1 to Ym are sufficiently erased. By this set-down discharge, wall charges such that the address discharge can stably occur remain uniformly in the cells.

In the address period, the negative scan pulse -Vy is sequentially applied to the scan electrodes Y1 to Ym, and the positive data pulse is applied to the address electrodes X ₁ to X _n in synchronization with the scan pulse. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the reset period are added, address discharge is generated in the discharge cell to which the data pulse is applied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when the sustain voltage Vs is applied. The positive voltage Vz is supplied to the sustain electrode Z so as to reduce the voltage difference between the scan electrodes Y1 to Ym during the set down period and the address period so as to prevent erroneous discharge from the scan electrodes Y1 to Ym.

In the sustain period, the sustain pulse Su is applied to the scan electrodes Y1 to Ym and the sustain electrodes Z alternately. In the cell selected by the address discharge, the sustain voltage, that is, the display discharge, is generated between the scan electrodes Y1 to Ym and the sustain electrode Z every time the sustain pulse is applied as the wall voltage and the sustain pulse in the cell are added.

After the sustain discharge is completed, in the erase period, a voltage of an erase ramp waveform Ramp-ers having a small pulse width and a low voltage level is supplied to the sustain electrode to erase the wall charge remaining in the cells of the full screen.

Here, a driving apparatus of a conventional plasma display panel for generating such a driving waveform is connected to the panel to form a plasma display apparatus. Among these driving apparatuses, a scan driving apparatus for driving a scan electrode is as follows. .

4 is a diagram for describing a scan driving device among driving devices of a conventional plasma display panel.

As shown in FIG. 4, a driving apparatus of a conventional plasma display panel includes an energy recovery circuit unit 400, a drive integrated circuit 430, a setup supply unit 410, a set down supply unit 440, and a negative scan voltage supply unit 450. ) Is connected between the scan reference voltage supply unit 420 and the seventh switch Q7 connected between the setup supply unit 410 and the drive integrated circuit 430, and between the setup supply unit 410 and the energy recovery circuit 400. A sixth switch Q6 is provided.

The drive integrated circuit 430 is connected in a push / pull form and includes an energy recovery circuit 400, a setup supply unit 410, a set down supply unit 440, a negative scan voltage supply unit 450, and a scan reference voltage supply unit. And third and fourth switches Q3 and Q4 to which a voltage signal is input from 420. The output line between the third and fourth switches Q3 and Q4 is connected to any one of the scan electrode lines Y1 to Ym of the panel Cp.

The energy recovery circuit 400 recovers energy recovered from the panel Cp and supplies the sustain voltage Vs to the panel Cp.

The negative scan voltage supplier 450 supplies a scan pulse having a voltage magnitude of -Vy to the scan electrode lines Y1 to Ym in the address period.

The scan reference voltage supply unit 420 supplies the scan reference voltage Vsc to the scan electrode lines Y1 to Ym in the address period.

The set down supply unit 440 supplies the falling ramp pulse to the scan electrode lines Y1 to Ym in the set down period of the reset period.

The setup supply unit 410 supplies a ramp-up pulse to the scan electrode lines Y1 to Ym in the setup period of the reset period.

On the other hand, the driving apparatus of the conventional plasma display panel is a scan which rises sharply at the same time to each scan electrode Y ₁ to Y _{m in} the address period (the area of A1 shown in FIG. 3) after the above-described reset period. The reference voltage Vsc is supplied, which is illustrated in FIG. 5.

5 is a diagram for describing a scan reference voltage supplied to an address period in a conventional plasma display panel driving apparatus.

As shown in FIG. 5, the driving apparatus of the conventional plasma display panel supplies the scan reference voltage Vsc which rises rapidly at the same time to the scan electrodes Y ₁ to Y _m in the address period. At this time, when a rapidly changing voltage is supplied to each scan electrode, a capacitor component, that is, a coupling, of the scan reference voltage pulse is generated between adjacent cells, thereby generating a relatively large noise.

In addition, when the rapidly changing scan reference voltage Vsc is supplied to each scan electrode Y ₁ to Y _m at the same time point ts in all cells, the noise of the waveform of the scan reference voltage Vsc becomes more and more. Deepen. An example in which such noise is generated will be described with reference to FIG. 6.

FIG. 6 is a diagram for describing noise generated due to a scan reference voltage supplied to scan electrodes Y ₁ to Y _m in an address period by a driving apparatus of a conventional plasma display panel.

As shown in FIG. 6, when the driving apparatus of the conventional plasma display panel supplies the scan reference voltage Vsc which rises rapidly at the same time point ts at the scan electrodes Y ₁ to Y _m , respectively, during the address period, scan is performed. Large noise occurs in the driving waveforms applied to the electrodes Y ₁ to Y _m . Such noise is caused by coupling through the capacitance of the panel. When the scan reference voltage increases, rising noise is generated in the driving waveform applied to the scan electrodes (Y ₁ to Y _m ). do.

As described above, the noise generated as the scan reference voltage Vsc rapidly changes to the scan electrodes Y ₁ to Y _m at the same time point ts is the absolute value Vn of the instant when the scan reference voltage is input. Make) large. Therefore, there is a problem that the driving margin is reduced when driving the plasma display panel, thereby reducing the driving margin.

In addition, the absolute value of the voltage (Vn) due to the noise may cause electrical damage to the circuit elements, and accordingly there is a problem that the use of the device with a high withstand voltage characteristics is required to increase the manufacturing cost.

In order to solve the above problems, an object of the present invention is to provide a plasma display device capable of improving driving efficiency by reducing noise generated in a scan reference voltage with a scan electrode in an address period to stabilize driving.

In addition, another object of the present invention is to provide a plasma display device that can prevent the electrical damage of the circuit elements, thereby reducing the manufacturing cost of the device.

The plasma display device of the present invention for achieving this purpose is a plasma display panel including a plurality of scan electrodes and a scan reference voltage for supplying a scan reference voltage rising with a slope for a predetermined period of the address period after the set-down period to the scan electrode And a driving signal output unit configured to output a scan reference voltage supplied by the supply unit and the scan reference voltage supply unit to a scan electrode of the plasma display panel through a predetermined switching operation.

In addition, the scan reference voltage supply unit is provided on the supply path of the scan reference voltage from an external scan reference voltage source to the drive signal output unit, and the first switch is turned on after the set-down period, and the drive One end is connected to the signal output unit, and the other end is connected in series with the first switch to include a waveform generator for causing the scan reference voltage to rise with a slope for a predetermined period after the set-down period when the first switch is turned on. It is characterized by.

The driving signal output unit may include a third switch and a fourth switch connected in a push-pull form, and the scan electrode of the plasma display panel is disposed between one end of the third switch and one end of the fourth switch. A second switch connected to the other end of the third switch of the driving signal output unit and one end of the waveform generator, and the other end of the scan reference voltage supply unit connected to the other end of the fourth switch and the scan A reverse current blocking unit connected between a reference voltage source and the first switch to block reverse current flowing to the scan reference voltage source, and one end is commonly connected between the reverse current blocking unit and the first switch, and the other end of the second switch The common node is connected to the other end of the switch and the other end of the fourth switch to form a common node, and the voltage supplied to the first switch is the scan reference voltage. Holding voltage to maintain characterized in that it further comprises: a.

The predetermined period may be adjusted within a period from a time when the scan reference voltage supplied in the address period starts to increase to a time when the first scan pulse is supplied to the scan electrode.

The predetermined period of time may be controlled within a range of 0 ms (microsecond) and 20 ms (microsecond) or less.

The predetermined period of time may be adjusted within a range of 6 ms (microseconds) and 10 ms (microseconds) or less.

In addition, the slope at which the scan reference voltage increases during the predetermined period after the set down period is smaller than the slope of the sustain pulse applied in the sustain period.

The waveform generator may be one of a fixed resistor and a variable resistor.

In addition, the resistance value of the fixed resistor or the variable resistor may vary according to the panel characteristics of the plasma display panel.

The waveform generating unit may include a resistor, and the magnitude of the resistance of the waveform generating unit corresponding to one or more scan electrode groups among a plurality of scan electrode groups including one or more scan electrodes may correspond to another scan electrode group. It is characterized in that it is different from the magnitude of the resistance of the generator.

The number of scan electrode groups may be two or more and less than the total number of scan electrodes.

The scan electrode group may include one or more of the scan electrodes.

The scan electrode group may include the same number of scan electrodes or one or more different numbers of scan electrodes.

The scan electrode group including the plurality of scan electrodes among the plurality of scan electrode groups may have the same magnitude of resistance of the waveform generator corresponding to each scan electrode.

Hereinafter, a plasma display device of the present invention will be described in detail with reference to the accompanying drawings.

7 is a view for explaining the configuration of a scan driving device of the plasma display panel of the present invention.

As shown in FIG. 7, the driving apparatus of the conventional plasma display panel includes an energy recovery circuit 700, a drive integrated circuit 730, a setup supply 710, a set-down supply 740, and a negative scan voltage supply 750. ), A seventh switch Q7 connected between the scan reference voltage supply unit 720 and the setup supply unit 710 and the drive integrated circuit 730, and between the setup supply unit 710 and the energy recovery circuit 700. A sixth switch Q6 is provided.

The drive integrated circuit 730 is connected in a push / pull form and includes an energy recovery circuit 700, a setup supply unit 710, a setdown supply unit 740, a negative scan voltage supply unit 750, and a scan reference voltage supply unit. And third and fourth switches Q3 and Q4 to which a voltage signal is input from 720. The output line between the third and fourth switches Q3 and Q4 is connected to any one of the scan electrode lines Y1 to Ym of the panel Cp.

The energy recovery circuit 700 supplies the sustain voltage Vs to the panel Cp, and recovers the reactive energy of the panel Cp. The energy recovery circuit unit 700 may include, for example, an energy storage capacitor C1 for charging energy recovered from the scan electrode lines Y1 to Ym, an energy storage capacitor C1, and a scan drive integrated circuit. The inductor L1 connected between the 730 and the eighth switch Q8, the first diode D1, the second diode D2, and the second connected in parallel between the inductor L1 and the external capacitor C1. A ninth switch Q9, a sustain voltage source Vs for supplying the sustain voltage Vs, and a ground voltage source for supplying voltages of the twelfth switch Q12 and ground level GND connected between the inductor L1 described above; The thirteenth switch Q13 is connected between the above-described inductor L1.

Referring to the operation of the energy recovery circuit unit 700 as follows. First, it is assumed that the energy storage capacitor C1 is charged with the voltage Vs / 2. Here, when the above-mentioned eighth switch Q8 is turned on, the voltage charged in the energy storage capacitor C1 is the eighth switch Q8, the first diode D1, the inductor L1, The scan drive integrated circuit 730 is supplied to the scan drive integrated circuit 730 via the sixth switch Q6 and the seventh switch Q7, and the scan drive integrated circuit 730 transfers the voltage supplied thereto to the scan electrode lines Y1 to Ym. Supply.

At this time, since the inductor L1 forms a series LC resonant circuit together with the capacitance Cp of the plasma display panel discharge cell, a voltage of Vs is supplied to the scan electrode lines Y1 to Ym.

Thereafter, the twelfth switch Q12 is turned on. When the twelfth switch Q12 is turned on, the sustain voltage Vs is supplied to the drive integrated circuit 730 via the internal diode of the sixth switch Q6 and the seventh switch Q7. The scan drive integrated circuit 730 supplies the sustain voltage Vs supplied thereto to the scan electrode lines Y1 to Ym. Due to the sustain voltage Vs, the voltage level on the scan electrode lines Y1 to Ym maintains the sustain voltage Vs, and thus sustain discharge occurs in the discharge cells of the panel Cp.

After the sustain discharge occurs in the discharge cells of the panel Cp, the thirteenth switch Q13 is turned on. When the thirteenth switch Q13 is turned on, the scan electrode lines Y1 to Ym, the scan drive integrated circuit 730, the internal diode of the seventh switch Q7, the sixth switch Q6, and the inductor L1 are turned on. The reactive power is recovered to the energy storage capacitor C1 via the second diode D2 and the ninth switch Q9. That is, energy from the plasma display panel Cp is recovered to the energy storage capacitor C1. Subsequently, the thirteenth switch Q13 is turned on to maintain the voltage on the scan electrode lines Y1 to Ym at the potential GND at the ground level.

In this way, the energy recovery circuit unit 700 recovers energy from the plasma display panel Cp, and then supplies voltage to the scan electrode lines Y1 to Ym using the recovered energy to discharge the battery during the setup period and the sustain period. Excessive power consumption is reduced.

The negative scan voltage supply 750 includes an eleventh switch Q11 connected between the first node n1 and the scan voltage source -Vy. The eleventh switch Q11 is switched in response to a control signal supplied from a timing controller (not shown) during the address period, thereby scanning the negative scan voltage (-Vy) falling from the scan reference voltage Vsc. ).

The setup supply unit 710 is provided between the third diode D3 and the fifth switch Q5 connected between the setup voltage source Vst and the first node n1 and the setup voltage source and the energy recovery circuit unit 700. Two capacitors C2. The third diode D3 blocks the reverse current flowing from the second capacitor C2 toward the setup voltage source Vst. The second capacitor C2 stores the setup voltage Vst supplied from the setup voltage source supplying the setup voltage Vst, and the voltage supplied to the fifth switch Q5 during the setup period of the reset period is set up by the setup voltage Vst. Keep it constant.

In the setdown supply unit 740, the sixth switch Q6 is turned off and the tenth switch Q10 is turned on in the setdown period after the setup period of the reset period. The tenth switch Q10 has a predetermined slope with a negative scan voltage (-Vy) of the voltage of the first node n1 while the channel width is adjusted by the second variable resistor VR2 installed at the front end thereof. Lower In this case, a setdown pulse, that is, a ramp ramp down, is supplied to the scan electrode lines Y1 to Ym.

The scan reference voltage supplying unit 720 includes a voltage holding unit C3 including a capacitor connected between the scan voltage source Vsc and the common node n2, and between the scan voltage source Vsc and the common node n2. It comprises a first switch (Q1) and a second switch (Q2) connected to. The first switch Q1 and the second switch Q2 are supplied by the control signal supplied from the timing controller during the address period to supply the voltage of the scan voltage source Vsc to the drive integrated circuit 730. The voltage holding unit C3 keeps the scan reference voltage Vsc supplied from the scan reference voltage source constant.

The reversal flows from the first switch Q1 to the scan reference voltage source Vsc between the scan reference voltage source Vsc and the first switch Q1 which supplies the scan reference voltage Vsc to the scan reference voltage supply unit 720. It is preferable to further include a reverse current blocking unit (D4) for blocking the flow.

Here, the aforementioned voltage holding unit C3 stores the scan reference voltage Vsc supplied by the scan reference voltage source Vsc. The voltage holding part C3 plays a role of constantly maintaining the waveform of the scan reference voltage Vsc supplied from the scan reference voltage source Vsc as described above so as not to shake.

One end of the waveform generator 721 is connected to the first switch Q1 in series, and the other end thereof is connected to the scan drive integrated circuit 750. The waveform generator causes the scan reference voltage Vsc to gradually rise with a slope for a predetermined period of the address period after the set-down period when the first switch Q1 is turned on.

The waveform generator 721 may be made of a fixed resistor having a predetermined resistance value and may be made of a variable resistor.

On the other hand, the resistance of the waveform generator 721 may be changed in accordance with the panel characteristics of the plasma display panel. For example, the magnitude of the resistance of the waveform generating unit 721 varies according to the composition ratio of the discharge gas in the discharge cell of the plasma display panel, the characteristics of the phosphor in the discharge cell of the plasma display panel, or the distance between electrodes. The magnitude of the resistance of the waveform generator 721 may vary depending on the variable.

The characteristics and operation of the waveform generator 721 will be more clearly explained through the description of the driving waveforms later.

8 is a diagram for describing driving waveforms of the driving apparatus of the plasma display panel according to the present invention.

As shown in Fig. 8, the plasma display panel erases the reset period for initializing all the cells, the address period for selecting the cells to be discharged, the sustain period for maintaining the discharge of the selected cells, and the wall charges in the discharged cells. It is divided into an erase period for driving.

In the reset period, the rising ramp waveform Ramp-up is simultaneously applied to all the scan electrodes Y1 to Ym in the setup period. This rising ramp waveform causes weak dark discharge within the full discharge cells. This setup discharge causes positive wall charges to accumulate on the address electrodes X ₁ to X _n and the sustain electrodes, and negative wall charges to accumulate on the scan electrodes Y1 to Ym.

During the set-down period, after the rising ramp waveform is supplied, the falling ramp waveform (Ramp-down) starts to fall from the positive voltage lower than the peak voltage of the rising ramp waveform and falls to a specific voltage level below the ground (GND) level voltage. By generating a weak erase discharge in the inside, the wall charges excessively formed in the scan electrodes Y1 to Ym are sufficiently erased. By this set-down discharge, wall charges such that the address discharge can stably occur remain uniformly in the cells.

In the address period, the negative scan pulse -Vy is sequentially applied to the scan electrodes Y1 to Ym, and a positive data pulse is applied to the address electrodes X ₁ to X _n in synchronization with the scan pulse. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the reset period are added, address discharge is generated in the discharge cell to which the data pulse is applied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when the sustain voltage Vs is applied. The positive voltage Vz is supplied to the sustain electrode Z so as to reduce the voltage difference between the scan electrodes Y1 to Ym during the set down period and the address period so as to prevent erroneous discharge from the scan electrodes Y1 to Ym.

In the sustain period, the sustain pulse Su is applied to the scan electrodes Y1 to Ym and the sustain electrodes Z alternately. In the cell selected by the address discharge, as the wall voltage and the sustain pulse in the cell are added, a sustain discharge, that is, a display discharge occurs between the scan electrodes Y1 to Ym and the sustain electrode Z whenever the sustain pulse is applied.

After the sustain discharge is completed, in the erase period, a voltage of an erase ramp waveform Ramp-ers having a small pulse width and a low voltage level is supplied to the sustain electrode to erase the wall charge remaining in the cells of the full screen.

Here, the scan reference voltage supply unit of the driving apparatus of the plasma display panel according to the present invention, which is different from the conventional one, supplies the scan reference voltage rising with a slope for a predetermined period in the address period (region of A2) after the reset period. Next, as shown in FIG.

9 is a view for explaining in more detail the operation of the waveform generator in the driving apparatus of the plasma display panel of the present invention.

As shown in FIG. 9 (a), after the falling ramp pulse (Ramp-down) supplied in the set-down period of the reset period ends, the scan period is supplied with the address period begins. In this case, the above-described waveform generation unit allows the scan reference voltage to rise with a slope (first slope) for a predetermined period. By applying a waveform gradually rising in this way, a change in voltage occurs gradually, and noise can be reduced. In addition, there is an effect that the driving is stable, thereby improving the driving efficiency.

In addition, since the noise is reduced, it is possible to prevent electrical damage of the circuit elements, thereby reducing the manufacturing cost of the device.

Here, the above-described predetermined period is characterized in that it is within a period from the time when the scan reference voltage supplied in the address period starts to rise until the first scan pulse is supplied to the scan electrodes (Y1 to Ym). Noise can be reduced more effectively as the maximum time the ramp pulse can be maintained.

More preferably, as shown in (a) of FIG. 9, the rising period d1 of the scan reference voltage adjusted within the period from when the scan reference voltage starts to increase until the first scan pulse is supplied is It can be adjusted within the range of 0 microseconds and 20 microseconds. Further, more preferably, it can be adjusted within the range of 6 microseconds (microseconds) and 10 microseconds (microseconds) or less, in order to prevent driving margins falling by increasing the driving time.

In addition, preferably, the voltage at the end of the set-down pulse described above and the voltage (-Vy) of the scan pulse falling from the scan reference voltage Vsc may be adjusted to the same voltage to simplify driving.

In addition, when comparing (a) and (b) of FIG. 9, the slope (first slope) in which the aforementioned scan reference voltage rises for a predetermined period after the set-down period is the slope of the sustain pulse applied in the sustain period (second slope). Smaller than That is, the rising slope (first slope) of the above-mentioned rising waveform of the scan reference voltage is smaller than the rising slope (second slope) of the sustain pulse in the ER-Up Time at which the voltage of the sustain pulse increases, that is, the voltage per hour. By reducing the rate of change of the noise, noise can be reduced.

The effect of the scan reference voltage shown in the present invention is more clearly shown in FIG.

FIG. 10 illustrates noise generated due to scan reference voltages supplied to scan electrodes Y ₁ to Y _m in an address period among driving waveforms of the plasma display panel of the present invention.

As shown in FIG. 10, when the driving apparatus of the plasma display panel of the present invention supplies the scan reference voltage Vsc which rises with a predetermined slope to the scan electrodes Y ₁ to Y _m in the address period, the scan electrodes The generation of noise is relatively reduced in the driving waveforms applied to (Y ₁ to Y _m ) as compared with the prior art. The reason why the noise is reduced is because the rate of change of the instantaneous voltage change of the scan reference voltage Vsc is reduced to reduce the influence of coupling through the capacitance of the panel.

As described above, the scan reference voltage Vsc applied to the scan electrodes Y ₁ to Y _m gradually increases with a predetermined slope in the address period, thereby reducing the generation of noise. This prevents it from becoming unstable.

In addition, since the noise is reduced, the absolute value Vn of the voltage generated when the scan reference voltage is applied is reduced to prevent electrical damage of the circuit elements. As a result, even a device having a low withstand voltage characteristic can be used, thereby reducing the manufacturing cost of the circuit device.

Although not mentioned in the above description, the resistance of the waveform generator corresponding to the plurality of scan electrodes Y ₁ to Y _m on the plasma display panel may have one or more different values, which will be described below.

Before describing the case where the resistance of the waveform generator has two or more different resistance values, the scan electrodes (Y ₁ to Y _m ) of the plasma display panel are divided into a plurality of scan electrode groups in order to help the understanding of the present invention. An example will be described with reference to FIG. 11 as follows.

FIG. 11 is a diagram illustrating scan electrodes Y ₁ to Y _m formed in a plasma display panel divided into four scan electrode groups in order to explain a method of driving the plasma display panel according to the present invention.

As shown in FIG. 11, assuming that the total number of scan electrodes formed on the plasma display panel 1100 is 100, such scan electrodes Y ₁ to Y ₁₀₀ may be, for example, the A scan electrode group Y. FIG. ₁ to Y ₂₅ ) 1101, B scan electrode group (Y ₂₆ to Y ₅₀ ) 1102, C scan electrode group (Y ₅₁ to Y ₇₅ ) 1103, and D scan electrode group (Y ₇₆ to Y ₁₀₀ ) (1104). In the case of FIG. 11, each scan electrode group includes 25 scan electrodes.

The number of scan electrode groups may be set between 2 ≦ N ≦ (n−1) when the number of scan electrodes is at least two to less than the maximum number of scan electrodes, that is, the total number of scan electrodes is n. .

Meanwhile, in FIG. 11, although the number of scan electrodes included in each scan electrode group 1101, 1102, 1103, and 1104 is the same, the scan electrodes included in each scan electrode group 1101, 1102, 1103, and 1104 are the same. It is also possible to set the number differently from each other. The number of scan electrode groups can also be adjusted. As described above, an example of changing the number of scan electrodes included in each scan electrode group or adjusting the number of scan electrode groups will be described with reference to FIG. 12.

FIG. 12 is a diagram for describing an example of dividing a plurality of scan electrodes formed on a plasma display panel into one or more scan electrode groups including different numbers of scan electrodes.

Referring to FIG. 12, assuming that the total number of scan electrodes formed on the plasma display panel 1200 is 100, these scan electrodes Y ₁ to Y ₁₀₀ are scanned, for example, including 15 scan electrodes. Electrode group (Y ₁ to Y ₁₅ ) 1201, B scan electrode group (Y ₁₆ to Y ₆₀ ) 1202 including 45 scan electrodes, C scan electrode group (Y ₆₁ to 10) including 10 scan electrodes Y ₇₀ ) 1203 and D scan electrode groups (Y ₇₁ to Y ₁₀₀ ) 1204 including 30 scan electrodes.

Based on the concept of the electrode group as described above with reference to FIGS. 11 and 12, the driving apparatus of the plasma display panel of the present invention will be described.

13 is a view for explaining the magnitude of the resistance of the waveform generation unit corresponding to the scan electrode group in the driving apparatus of the plasma display panel according to the present invention.

Referring to FIG. 13, the waveform generator 721 of FIG. 7 generates a slope such that the scan reference voltage Vsc supplied to the plurality of scan electrodes in the address period rises with a slope for a predetermined period of the address period after the above-described reset period. Is connected to the plurality of scan electrodes. Here, the magnitude of the resistance of the waveform generator 721 corresponding to one or more scan electrode groups among the plurality of scan electrode groups including one or more of the scan electrodes is the resistance of the waveform generator 721 corresponding to another scan electrode group. Is different from the size. For example, as shown in FIG. 13, a total of 100 scan electrodes are included in the plasma display panel 1100, and each of the 100 scan electrodes includes 25 scan electrodes, each of which includes 25 scan electrodes. When divided into (1101, 1102, 1103, 1104), it corresponds to the scan electrodes of the A scan electrode groups (Y ₁ to Y ₂₅ ) 1101, that is, the scan electrodes from the Y ₁ scan electrode to the Y ₂₅ scan electrode. The resistance of the waveform generator 721 to be obtained is R1.

In addition, the resistance of the waveform generator 721 corresponding to the scan electrodes of the B scan electrode groups Y ₂₆ to Y ₅₀ 1102, that is, the scan electrodes from the Y ₂₆ scan electrode to the Y ₅₀ scan electrode, is R1 described above. Is different from R2.

In addition, the resistance of the waveform generator 721 corresponding to the scan electrodes of the C scan electrode groups Y ₅₁ to Y ₇₅ 1103, that is, the scan electrodes from the Y ₅₁ scan electrode to the Y ₇₅ scan electrode, is R1 described above. And R3 different from R2.

In addition, the resistance of the waveform generator 721 corresponding to the scan electrodes of the D scan electrode groups Y ₇₆ to Y ₁₀₀ 1104, that is, the scan electrodes from the Y ₇₆ scan electrode to the Y ₁₀₀ scan electrode is R1 described above. , R2 is different from R2 and R3.

Here, in the scan electrode group including the plurality of scan electrodes among the plurality of scan electrode groups, the resistance of the waveform generator 721 corresponding to each scan electrode is preferably the same. For example, assuming that any one of the plurality of scan electrode groups includes a total of 10 scan electrodes, the resistances of the 10 scan electrodes and the corresponding waveform generator 721 have the same resistance value. will be.

The R1, R2, R3, and R4 have a resistance greater than 0 ms (microseconds) for a period from which the magnitude of the resistance starts to rise above the scan reference voltage Vsc until the first scan pulse is supplied. It is desirable to have a range to be adjusted below (microseconds). The slope of the scan reference voltage waveform generated according to the magnitude of the resistance of the waveform generator 721 will be more clearly described with reference to FIGS. 14A to 14B.

Although R1, R2, R3, and R4 described above only have different resistance values, differently, one or more resistors selected from R1, R2, R3, and R4 may have different resistance values compared to other resistors. It is also possible. For example, R1, R2, and R3 of the above-described R1, R2, R3, and R4 may have the same resistance value, and R4 may have different resistance values from R1, R2, and R3.

As described above, by varying the resistance value of the waveform generator 721 corresponding to the plurality of scan electrode groups by one or more, the scan reference voltage Vsc supplied to the scan electrode in the address period has a predetermined slope. It is to be gradually raised with an example of this, as shown in Figure 14a to 14b.

14A to 14B are views for explaining an example of a change in time when the scan reference voltage Vsc rises according to the resistance value of the waveform generator.

First, referring to FIG. 14A, a scan reference voltage Vsc is supplied to a scan electrode in an address period according to a resistance value of a waveform generator of a driving apparatus of a plasma display panel of the present invention corresponding to a plurality of scan electrode groups on a plasma display panel. The rising time of is controlled. For example, as shown in FIG. 14A, all the scan electrodes included in the A scan electrode group as shown in FIG. 13 are started to rise at the time point t _{0 in} the address period and thus the time point t ₁ . Is supplied with a scan reference voltage reaching the scan reference value Vsc. This is achieved by the R1 resistance of the waveform generator of FIG.

In addition, all scan electrodes included in the B scan electrode group are supplied with a scan reference voltage starting to rise at the time point t _{0 in} the address period and reaching the scan reference voltage value Vsc at the time point t ₂ . This is achieved by the R2 resistance of the waveform generator of FIG. Here, the voltage rise time of the scan reference voltage supplied to all the scan electrodes included in the B scan electrode group is longer than that of the A scan electrode group described above, which means that the resistance value of the R2 resistance is larger than the above-described R1 resistance.

Further, all scan electrodes included in the C scan electrode group are supplied with a scan reference voltage starting to rise at the time point t _{0 in} the address period and reaching the scan reference voltage value Vsc at the time point t ₃ . This is achieved by the R3 resistance of the waveform generator of FIG. This means that the resistance value R3 is larger than the resistances R1 and R2 described above.

Further, all scan electrodes included in the D scan electrode group are supplied with a scan reference voltage starting to rise at the time point t _{0 in} the address period and reaching the scan reference voltage value Vsc at the time point t ₄ . This is achieved by the R4 resistance of the waveform generator of FIG. This means that the resistance of R4 is larger than the resistances of R1, R2 and R3 described above.

That is, the voltage rise time of the scan reference voltage Vsc supplied to the scan electrode in the address period is adjusted differently according to the resistance value of the waveform generator corresponding to each scan electrode group.

Here, the rising time of the scan reference voltage is a time from the start of the rising of the voltage applied to the scan electrodes Y1 to Ym after the set-down period of the reset period until the scan reference voltage value Vsc is reached. Preferably, the rise time of this scan reference voltage is adjusted within the range of 0 microseconds and 20 microseconds. That is, the resistances R1, R2, R3, and R4 of the above-described waveform generating unit have a resistance of which the rise time of the scan reference voltage is greater than 0 ms (microseconds) and 20 ms (microseconds) or less. Has a value to be adjusted.

In addition, in FIG. 14A, the resistance value of the waveform generator is adjusted so that the difference between the rise times of two scan reference voltages having different rise times is the same. That is, a scan applied to the B scan electrode group when the difference between the rise time of the scan reference voltage applied to the A scan electrode group and the rise time of the scan reference voltage applied to the B scan electrode group is 5 microseconds (microseconds). The difference between the rise time of the reference voltage and the rise time of the scan reference voltage applied to the C scan electrode group, the rise time of the scan reference voltage applied to the C scan electrode group, and the rise of the scan reference voltage applied to the D scan electrode group. The difference with time is all set to 5 ms (microseconds) as described above.

Alternatively, the resistance value of the waveform generator may be adjusted so that the difference between the rise times of two scan reference voltages having different rise times is different. The driving waveforms are as follows in FIG. 14B.

14B, the difference between the rise times of two scan reference voltages having different rise times is different. That is, the difference between the rise time of the scan reference voltage applied to the A scan electrode group and the rise time of the scan reference voltage applied to the B scan electrode group, that is, the difference between t ₂ and t ₁ is 5 ms (microsecond). The difference between the rise time of the scan reference voltage applied to the B scan electrode group and the rise time of the scan reference voltage applied to the Yc scan electrode group, i.e., the difference between t ₃ and t ₂ is 7 s (microsecond), C The difference between the rise time of the scan reference voltage applied to the scan electrode group and the rise time of the scan reference voltage applied to the D scan electrode group, that is, the difference between t ₄ and t ₃ is set to 10 ms (microsecond). The resistance value of the generator is adjusted.

This further reduces the amount of noise generated by the scan reference voltage applied to the scan electrodes in the address period.

The reason why the noise is reduced is that the scan electrodes are divided into a plurality of electrode groups without the same rise time of the scan reference voltages applied to all scan electrodes Y ₁ to Y _m , and at least one or more of the scans in an address period. Coupling through the capacitance of the panel at the time of applying each scan reference voltage by adjusting the rise time of the scan reference voltage applied to the electrode group differently from the rise time of the scan reference voltage applied to the remaining scan electrode groups. By reducing (Coupling), the rising noise generated in the waveform applied to the scan electrode is reduced when the scan reference voltage rises sharply. This prevents electrical damage of the plasma display panel drive element, for example, the scan driver IC of the scan driver.

Meanwhile, in the above description, the resistance value of the waveform generator is adjusted to divide the scan electrodes Y ₁ to Y _m into a plurality of scan electrode groups so that the rise time of the scan reference voltage applied to the scan electrodes in the address period varies for each scan electrode. Alternatively, the rising time of the scan reference pulse applied to each of the scan electrodes in the address period may be different for each scan electrode, which will be described with reference to FIGS. 15A to 15B.

15A to 15B are diagrams for describing another example of a change in time when the scan reference voltage Vsc rises according to the resistance value of the waveform generator.

First, referring to FIG. 15A, a scan reference voltage Vsc supplied to a scan electrode in an address period according to a resistance value of a waveform generator of a driving apparatus of a plasma display panel corresponding to a plurality of scan electrodes on a plasma display panel is described. The rise time is adjusted. For example, as shown in FIG. 15A, the Y ₁ scan electrode is supplied with a scan reference voltage that starts rising at the time point t _{0 in} the address period and reaches the scan reference voltage value Vsc at the time point t ₁ . The Y ₂ scan electrode is supplied with a scan reference voltage that starts rising at the time t _{0 in} the address period and reaches the scan reference voltage value Vsc at the time t ₂ , and the Y ₃ scan electrode is supplied with a t _{0 in} the address period. at the time of starting to increase at time t ₃ to a scan reference voltage to reach the scan reference voltage Vsc is supplied, Y _m scan in this way, Pole has started to rise at a time point of t ₀ to the address period, a scan reference voltage to reach the scan reference voltage Vsc at the time of t _m is supplied. This is achieved by the resistance of the waveform generator of the driving apparatus of the plasma display panel of the present invention. This is because the resistance of the waveform generator corresponding to the Y ₁ scan electrode, the resistance of the waveform generator corresponding to the Y ₂ scan electrode, the resistance of the waveform generator corresponding to the Y ₃ scan electrode, and the resistance of the waveform generator corresponding to the Y ₄ scan electrode. And resistances of the waveform generators corresponding to the Ym scan electrodes have different resistance values.

In FIG. 15A, only differences between voltage rise times of scan reference voltages Vsc having different voltage rise times are the same, but voltages of scan reference voltages Vsc having different voltage rise times are illustrated in FIG. 15B. It is also possible for the difference between rise times to be different.

15A to 15B are cases when the plurality of scan electrode groups of FIGS. 14A to 14B each include one scan electrode as compared with FIGS. 14A to 14B described above. 15A to 15B are not the same as the number of scan electrodes included in the scan electrode group as compared with the case of FIGS. 14A to 14B, and thus the description thereof will not be repeated.

As such, the technical configuration of the present invention described above can be understood by those skilled in the art that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention.

Therefore, the exemplary embodiments described above are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the appended claims rather than the foregoing detailed description, and the meaning and scope of the claims are as follows. And all changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

As described above in detail, the plasma display device according to the present invention has an effect of reducing driving noise and improving driving efficiency.

In addition, another effect of the plasma display device according to the present invention is to prevent electrical damage to the circuit elements, thereby reducing the manufacturing cost.

Claims (14)

A plasma display panel including a plurality of scan electrodes; A scan reference voltage supply unit configured to supply a scan reference voltage rising to the scan electrode with a slope for a predetermined period after a set-down period until a scan reference voltage; And A driving signal output unit configured to output the scan reference voltage supplied by the scan reference voltage supply unit to a scan electrode of the plasma display panel through a predetermined switching operation; Plasma display device comprising a. The method of claim 1, The scan reference voltage supply unit A first switch installed on a supply path of the scan reference voltage from an external scan reference voltage source to the drive signal output unit and turned on after the set-down period; One end is connected to the driving signal output part, and the other end is connected in series with the first switch so that the scan reference voltage rises with a slope for a predetermined period after the set down period when the first switch is turned on. Plasma display device comprising a. The method of claim 2, The drive signal output unit A third switch and a fourth switch connected in a push-pull form, and are connected to the scan electrodes of the plasma display panel between one end of the third switch and one end of the fourth switch, The scan reference voltage supply unit A second switch having one end connected in common to the other end of the third switch of the driving signal output unit and one end of the waveform generating unit, and the other end connected to the other end of the fourth switch; A reverse current blocking unit connected between the scan reference voltage source and the first switch to block reverse current flowing to the scan reference voltage source; And One end is commonly connected between the reverse current blocking unit and the first switch, and the other end is commonly connected to the other end of the second switch and the other end of the fourth switch to form a common node and supplied to the first switch. A voltage maintaining unit for maintaining a constant voltage at a scan reference voltage; Plasma display device further comprising. The method of claim 2, The predetermined period And a time period from the time when the scan reference voltage supplied in the address period starts to rise to the time when the first scan pulse is supplied to the scan electrode. The method of claim 4, wherein The predetermined period A plasma display device, wherein the plasma display device is adjusted within a range of 0 microseconds to 20 microseconds. The method of claim 5, The predetermined period A plasma display device, wherein the plasma display device is adjusted within a range of 6 microseconds (microseconds) and 10 microseconds (microseconds) or less. The method of claim 2, And the slope at which the scan reference voltage rises for a predetermined period after the set-down period is smaller than the slope of the sustain pulse applied in the sustain period. The method of claim 2, And wherein the waveform generator is one of a fixed resistor and a variable resistor. The method of claim 8, The resistance value of the fixed resistor or the variable resistor is variable according to the panel characteristics of the plasma display panel. The method of claim 2, The waveform generator A resistance of the waveform generator of one or more scan electrode groups among the plurality of scan electrode groups including one or more scan electrodes may be equal to the magnitude of the resistance of the waveform generator corresponding to another scan electrode group. Plasma display device, characterized in that different. The method of claim 10, And the number of the scan electrode groups is two or more and less than the total number of the scan electrodes. The method of claim 11, And the scan electrode group includes one or more of the scan electrodes. The method of claim 12, And the scan electrode group includes the same number of scan electrodes or one or more different numbers of the scan electrodes. The method of claim 10, And a scan electrode group including a plurality of scan electrodes among the plurality of scan electrode groups, wherein the resistance of the waveform generator corresponding to each scan electrode has the same magnitude.

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