KR100675881B1 - Back bias voltage generator circuit - Google Patents

Abstract

The present invention relates to a back bias voltage (VBB) generation circuit for implementing a low voltage DRAM, the first to fourth clock signal input circuit unit for applying the first to fourth clock signal to the first to fourth node, respectively; The clamp circuit unit clamps the highest voltages of the first and second nodes to zero, and the first precharge unit and the second node signal to precharge the third node according to the first node signal. A second precharge unit for precharging the fourth node, a first pumping circuit unit for selectively outputting a charge of a third node having a negative potential to a back bias voltage terminal VBB according to the fourth node signal; And a second pumping circuit unit for selectively outputting a charge of the fourth node having a negative potential to a back bias voltage terminal according to the third node signal.

Back Bias Voltage (VBB)

Description

Circuit for Generating Back Bias Voltage {Circuit for Generating of Back Bias Voltage}

1 is a conventional back bias voltage (VBB) generation circuit diagram

FIG. 2 is a timing diagram in a steady state of the circuit of FIG. 1.

3 is a circuit diagram for generating a back bias voltage (VBB) according to the present invention.

4 is a timing diagram in a steady state of the circuit of FIG.

Explanation of symbols for the main parts of the drawings

P1 to P4: first to fourth PMOS

MP3 to MP8: 5th to 10th PMOS

N3 to N6: first to fourth nodes

MN2, MN3: first and second NMOS

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM DRAM power supply circuit, and more particularly to a back bias voltage (VBB) generation circuit for a next generation low voltage DRAM (DRAM).

In general, the back bias voltage VBB is used as a negative power source applied to a P well of a DRAM.

Hereinafter, a conventional back bias voltage VBB generation circuit will be described with reference to the accompanying drawings.

1 is a circuit diagram of a conventional back bias voltage VBB, and FIG. 2 is a timing diagram in a steady state of the circuit of FIG. 1.

The conventional bias voltage (VBB) generation circuit adopts a hybrid pumping method and is used in a 1.5V DRAM chip.

으로 클램핑(Clamping)하는 제 1 피모스(MP1)와, 상기 클럭 신호(CLK) 단자와 상기 제 1 노드(N1) 사이에 연결되는 제 1 캐패시터(C1)와, 상기 한쪽이 인버터(INV)의 출력 단자에 연결되는 제 2 캐패시터(C2)와, 게이트 전극이 상기 제 1 노드(N1)에 연결되고 한쪽 전극이 접지단(GND)에 연결되어 상기 제 1 노드(N1)값에 따라서 다른쪽 전극 단자인 제 2 노드(N2)를 프리차지(Precharge)하는 제 2 피모스(MP2)와, 게이트 단자가 상기 제 1 노드(N1)에 연결되고 한쪽 전극이 상기 제 2 노드(N2)에 연결되어 상기 제 1 노드(N1)의 신호에 따라서 상기 제 2 노드(N2)의 신호를 다른쪽 전극 단자인 백바이어스전압 단자(VBB)로 출력하는 엔모스(MN1)로 이루어진다.The detailed configuration is as shown in FIG. 1, when the inverter INV for inverting the clock signal CLK, the gate electrode and one electrode are connected to the ground terminal GND, and the clock signal CLK is VDD. , The highest voltage of the first node N1, the other electrode terminal,

The first PMOS MP1 clamping to the first capacitor C1, the first capacitor C1 connected between the clock signal CLK terminal and the first node N1, and one side of the inverter INV. A second capacitor C2 connected to an output terminal, a gate electrode connected to the first node N1, and one electrode connected to a ground terminal GND, and the other electrode according to the value of the first node N1. A second PMOS MP2 for precharging the second node N2 as a terminal, a gate terminal connected to the first node N1, and one electrode connected to the second node N2 The NMOS MN1 outputs the signal of the second node N2 to the back bias voltage terminal VBB which is the other electrode terminal according to the signal of the first node N1.

가 되어 상기 엔모스(MN1)는 오프되고 상기 제 2 피모스(MP2)는 온되어 상기 제 2 피모스(MP2)를 통해 상기 제 2 노드(N2)의 전압이 0으로 프리차지(Precharge)된다.In the operation of the conventional back bias voltage generation circuit configured as described above, as shown in FIG. 2, when the voltage of the clock signal CLK is 0 (GND level), the voltage of the first node N1 is increased.

The NMOS MN1 is turned off and the second PMOS MP2 is turned on to precharge the voltage of the second node N2 to 0 through the second PMOS MP2. .

가 되어 상기 제 2 피모스(MP2)는 오프되고 상기 엔모스(MN1)는 온된다. 그리고, 상기 제 2 캐패시터(C2)를 통한 캐패시티브 커플링(Capacitive Coupling)에 의해 상기 제 2 노드(N2)의 전압이 -VDD가 되어 상기 온 상태의 엔모스(MN1)를 통하여 상기 제 2 노드(N2)의 네거티브 차지(Negative Charge)가 백바이어스전압 단자(VBB)로 출력된다.When the voltage of the clock signal CLK is changed from 0 to VDD, the voltage of the first node N1 is increased.

The second PMOS MP2 is turned off and the NMOS MN1 is turned on. In addition, the voltage of the second node N2 becomes -VDD by capacitive coupling through the second capacitor C2, and thus the second through the on-state NMOS MN1. The negative charge of the node N2 is output to the back bias voltage terminal VBB.

Here, as shown in FIG. 2, the charge pumping operation occurs only once during one period (T).

-VDD이며, 상기 제 2 피모스(MP2)가 온되기 위해서 상기 제 1 노드(N1)의 전압이 -

보다 작아야 한다.When the voltage of the clock signal CLK is 0, the voltage of the first node N1 is

VDD, and the voltage of the first node N1 is-to turn on the second PMOS MP2.

Should be smaller than

Otherwise, the second PMOS MP2 is in a cut-off area due to weak inversion, and the pumping efficiency is lowered.

Therefore, VDD must satisfy the following equation.

-VDD < - ;

-VDD <-;

< VDD2

<VDD

보다 커야 한다.That is, the VDD is 2

Must be greater than

이다.Therefore, the low voltage limit of the VDD is -2 ×.

to be.

However, the conventional back bias voltage generation circuit as described above has a problem in that a loss occurs in low voltage operation due to the threshold voltage V _TP of the clamp transistor, which is unsuitable for the low voltage design which is strongly required in the next generation DRAM.

The present invention has been made to solve the above problems to provide a back bias voltage generation circuit that can improve the pumping capability, eliminate the loss caused by the threshold voltage (V _TP ) of the clamp transistor to design a low voltage DRAM. There is a purpose.

The back bias voltage generation circuit of the present invention for achieving the above object comprises a first to fourth clock signal input circuit unit for applying the first to fourth clock signal to the first to fourth node, respectively, and the first node; And a clamp circuit for clamping the highest voltage of the second node to zero, a first precharge unit for precharging the third node according to the first node signal, and the fourth node according to the second node signal. A second precharge unit for precharging and a first pumping circuit unit and a third node for selectively outputting a charge of a third node having a negative potential to a back bias voltage terminal VBB according to the fourth node signal. And a second pumping circuit unit for selectively outputting the charge of the fourth node having a negative potential to the back bias voltage terminal according to the signal.

Hereinafter, a back bias voltage generation circuit of the present invention will be described with reference to the accompanying drawings.

3 is a circuit diagram of a back bias voltage generation circuit according to the present invention, and FIG.

The back bias voltage circuit of the present invention employs a two-phase method as shown in FIG. 3.

That is, according to the present invention, the first to fourth clock signals CLK1 to CLK4 applied to both electrodes are connected to the first to fourth nodes N3 to N6 through the gate electrode. Fourth PMOS P1 to P4, a gate electrode and one electrode are connected to the ground terminal GND, and the other electrode is connected to the first node N3, so that the first node during the initial time. The fifth PMOS MP3 and the other electrode clamping the highest operating voltage of N3 to V _TP and the other electrode are connected to the second node N4 so that the highest operation of the second node N4 is performed during the initial time. The sixth PMOS MP4 clamping the voltage to V _TP and the second node N4 signal are applied to the gate electrode and are connected between the first node N3 and the ground terminal GND to provide a normal state ( The seventh PMOS MP5 that makes the highest voltage of the first node N3 zero in the Steady State; The signal of the first node N3 is applied to the gate electrode and is connected between the second node N4 and the ground terminal GND to zero the highest voltage of the second node N4 in the normal state. 8 PMOS (MP6).

Accordingly, the steady state voltages of the first and second nodes N3 and N4 swing between -VDD and 0 due to the seventh and eighth PMOS MP5 and MP6.

In addition, a signal of the first node N3 is applied to a gate electrode, and is connected between the third node N5 and the ground terminal GND, and the third node (N3) according to the signal of the first node N3. A signal of the second node N4 is applied to a ninth PMOS MP7 precharging N5 and a gate electrode, and is connected between the fourth node N6 and the ground terminal GND. The tenth PMOS MP8 precharges the fourth node N6 according to the signal of N4 and the signal of the fourth node N6 applied to the gate electrode of the third node N5. The first node MN2 selectively outputs a signal to the back bias voltage terminal VBB, and the signal of the fourth node N6 is back according to the signal of the third node N5 applied to the gate electrode. The second NMOS MN3 selectively outputs the bias voltage terminal VBB.

As shown in FIG. 4, when the voltage of the first clock signal CLK1 is 0 in the normal state, the voltage of the first node N3 is maintained at −VDD and the eighth and ninth PMOS signals. MP6 and MP7 are turned on to precharge the voltages of the second node N4 and the third node N5 to zero.

When the voltage of the first clock signal CLK1 changes from 0 to VDD, the voltage of the first node N3 becomes 0 and both the eighth and ninth PMOS MP6 and MP7 are turned off. .

When the voltage of the third clock signal CLK3 changes from VDD to 0 while the voltage of the first clock signal CLK1 is maintained at VDD, the voltage of the third node N5 becomes -VDD. Next, when the voltage of the fourth clock signal CLK4 changes from 0 to VDD while the voltages of the first clock signal CLK1 and the third clock signal CLK3 are maintained at VDD and 0, respectively, the first NMOS MN2. ) Is turned on and outputs a negative charge of the third node N5 to the back bias voltage terminal VBB through the first NMOS MN2.

In a similar manner, the voltage of the fourth node N6 is set to -VDD and the second NMOS MN3 is turned on to charge the negative charge of the fourth node N6 through the second NMOS MN3. Output to the back bias voltage terminal (VBB).

Therefore, the charge pumping operation occurs twice in one period T.

For the proper operation of the circuit, the ninth PMOS MP7 and the tenth PMOS MP8 should operate when the gate electrode voltage, that is, the voltage of the first node N3 is -VDD.

Therefore, VDD must satisfy the condition of Equation 2 below.

-VDD < ;

-VDD <;

< VDD

<VDD

보다 크면 되므로 약 1.0V까지 동작할 수 있게 된다.Accordingly, the present invention eliminates the loss caused by the threshold voltages of the fifth PMOS MP3 and the sixth PMOS MP4, which are clamp transistors, by using the seventh PMOS MP5 and the eighth PMOS MP6. So that VDD

If it is larger, it can operate to about 1.0V.

The back bias voltage generation circuit of the present invention as described above has the following effects.

First, since the pumping operation can be performed twice per cycle, the charge pumping capability can be improved.

Second, since the voltage loss due to the threshold voltage V _TP of the clamp transistor can be eliminated, a DRAM having a low voltage can be designed.

Claims (4)

First to fourth clock signal input circuit sections for applying the first to fourth clock signals to the first to fourth nodes, respectively; A clamp circuit part configured to clamp the highest voltages of the first node and the second node to zero; A first precharge unit which precharges the third node according to the first node signal and a second precharge unit which precharges the fourth node according to the second node signal; A first pumping circuit unit for selectively outputting a charge of a third node having a negative potential to the back bias voltage terminal VBB according to the fourth node signal, and the negative of the negative potential according to the third node signal And a second pumping circuit unit for selectively outputting charges of the fourth node to the back bias voltage terminals. The back bias of claim 1, wherein the first to fourth signal input parts output 0 to the first to fourth nodes when the first to fourth clock signals are VDD and -VDD to the first to fourth nodes. Voltage generating circuit. 2. The clamp circuit of claim 1, wherein the clamp circuit part comprises: a first PMOS having a gate terminal connected to a ground terminal and connected between the first node and a ground terminal; A second PMOS connected between the second node signal to a gate terminal and a third PMOS connected between the first node and a ground terminal, and a sound first node signal to a gate terminal; A back bias voltage generation circuit comprising a fourth PMOS connected between a node and a ground terminal. 2. The back bias voltage generator circuit of claim 1, wherein the first pump circuit and the second pump circuit are configured to perform two pumping operations during one period of the first to fourth clock signals.

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