KR100675006B1 - Level-Converted Flip-Flops for Multiple Supply Voltage Systems - Google Patents

Abstract

Disclosed is a level converting flip-flop that can be used in a multiple supply system. A CP flip-flop according to an embodiment of the present invention stores a clock delay unit driven by a low supply voltage, a switch unit switching input data, and one or more output signals. A latch portion is provided. The IP flip-flop according to the embodiment of the present invention responds to a first delay signal of a clock delay unit driven by a low power supply voltage, a switch unit switching to ground power, and a clock delay unit A preliminary charging unit configured to generate a preliminary charging signal to be charged by the battery; A latch unit for storing a low signal by a ground power source is provided. CP flip-flop according to the present invention has a low power consumption, IP flip-flop according to the present invention has an effect that the operation speed is fast.

Description

Level converting flip-flops for multi-supply system

BRIEF DESCRIPTION OF THE DRAWINGS In order to more fully understand the drawings recited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a circuit diagram of a CP flip-flop (Complementary Pass transistor based flip-flop) according to the present invention.

2 is a circuit diagram of an Indirect precharge Flip-Flop according to the present invention.

3 is a table comparing a level shifted flip-flop and a conventional level shifted flip-flop according to the present invention.

The present invention relates to level converting flip-flops that can be used in a multiple supply system.

Level converting Flip-Flops (hereinafter referred to as LC flip-flops) means flip-flops with level converting in systems with different voltage levels. LC flip-flops require the ability to speed up the system and reduce power consumption.

In order to satisfy the above functions, the present invention proposes two improved LC flip-flops. One is a CP flip-flop (Complementary Pass transistor based Flip-Flop), the other is an IP flip-flop (Indirect precharge Flip-Flop).

An object of the present invention is to provide a CP (Flementary Pass transistor based Flip-Flop) with low power consumption.

Another technical problem of the present invention is to provide an indirect precharge flip-flop with a high operating speed.

In order to achieve the above technical problem, a flip-flop used in a multi supply system according to an embodiment of the present invention is driven by a low supply voltage and inverts a clock signal to delay an output signal. A clock delay unit configured to generate a plurality of switches, a switch unit configured to switch input data in response to the clock signal and an output signal of the clock delay unit, and a latch unit configured to store at least one output signal of the switch unit; do.

The flip-flop according to the exemplary embodiment of the present invention may further include an input buffer unit driven by a low power supply voltage and configured to invert buffer and reinvert buffer the input data.

The flip-flop used in the multiple power supply voltage system according to the embodiment of the present invention for achieving the above technical problem is a clock that is driven by a low power supply voltage and inverts and delays a clock signal to generate a first delay signal and an output signal. A preliminary charge including a delay unit and a plurality of switches, the switch unit switching to ground power in response to input data, the clock signal, and an output signal of the clock delay unit, and a precharge charged in response to a first delay signal of the clock delay unit Generating a signal, and switching a pre-charge unit in which the pre-charge signal is discharged by the ground power switched to the switch unit, a pre-charge signal and a low signal by the ground power in response to the clock signal in response to the clock signal; High signal connected to the latch control unit and the latch control unit by the power supply voltage of the latch control unit Or a latch unit for storing a low signal by a ground power source.

Accordingly, the CP flip-flop according to the present invention has a low power consumption, and the IP flip-flop according to the present invention has a fast operation speed.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings that describe exemplary embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

The present invention proposes a level converting flip-flops (LC flip-flops) that can be used in a multiple supply system. LC flip-flops are flip-flops that have level converting in systems with different voltage levels. The present invention proposes two LC flip-flops. One is a CP flip-flop (Complementary Pass transistor based Flip-Flop), the other is an IP flip-flop (Indirect precharge Flip-Flop).

1 is a circuit diagram of a CP flip-flop (Complementary Pass transistor based flip-flop) according to the present invention. Referring to FIG. 1, the CP flip-flop 100 according to the present invention may include a clock delay unit 110, a switch unit 120, a latch unit 130, and an input butter unit 150. have. A low supply voltage (VDDL) is connected to the clock delay unit 110 and the input buffer unit 150, and a high supply voltage (VDDH) is connected to the remaining components. The underlined clk , ckb , data , dt , and dtb signals refer to the VDDL signal, and the remaining signals q represent VDDH Means signal.

The input buffer unit 150 includes a first inverter 151 for inverting the input data signal data and a second inverter 152 for reversing the output of the first inverter.

The clock delay unit 110 includes three inverters 111, 112, 113 connected in series to invert the clock signal clk .

The switch unit 120 may include a first switch M1 for switching the data signal dt in response to the output signal ckb of the clock delay unit 110, and a first switch M1 in response to the clock signal clk . In response to the second switch M2 for switching the output signal of the control signal, the third switch M3 for switching the data signal dtb and the clock signal clk in response to the output signal ckb of the clock delay unit 110. In response, a fourth switch M4 for switching the output signal of the third switch M3 is provided. The first, second, third and fourth switches M1, M2, M3, and M4 may be configured as NMOS transistors.

The latch unit 130 has a first inverter 131 having an input terminal connected to a second switch M2 of the switch unit 120 and an output terminal thereof connected to a fourth switch M4 of the switch unit 120. And a second inverter 132 having an input terminal connected to the fourth switch M4 of the switch unit 120 and an output terminal thereof connected to the second switch M2 of the switch unit 120.

The input terminal of the output buffer 140 is connected between the second switch M2 of the switch unit 120 and the input terminal of the first inverter 311 of the latch unit 130. The output buffer 140 inverts and buffers the output signal of the latch unit 130.

The operation of the CP flip-flop 100 according to the present invention of FIG. 1 is as follows. The CP flip-flop of the present invention is a CP flip-flop triggered on the rising edge. First, when the clock signal clk is at the logic level low before the rising edge is input, the output signal ckb of the clock delay unit 110 is the inversion signal, and therefore becomes the logic level high. The first switch M1 and the third switch M3 are turned on, and the second switch M2 and the second switch M2 are turned off. In this case, the data of the flip-flop does not change.

After that, when the clock signal clk rises and the clock signal clk becomes logic level high, the output signal ckb of the clock delay unit 110 maintains the logic level high for a short period. Is the switch for a short period (M1, M2, M3, M4 ) of all the turn-on flip-flop 100 is a cross coupling (Cross-couple) of the latch unit 130 by accepting input data (data) drive (131 132). At this time, the VDDL signal levels dt and dtb are converted to the VDDH signal level by the cross-coupled inverters 131 and 132. After a short period of time, when the output signal ckb of the clock delay unit 110 becomes a logic level low, the first switch M1 and the third switch M3 are turned off to output the output data q of the flip-flop. Does not change By this operation, the CP flip-flop can reduce power consumption.

In addition, in the structure of the CP flip-flop 100 according to the present invention, the clock signal clk is connected to the second switch M2 and the fourth switch M4, and the output signal ckb of the clock delay unit 110 is provided . Is connected to the first switch M1 and the third switch M3. In this case, even before the clock signal clk is triggered as the rising edge, the nodes N1 and N2 are determined by the data input signals dt and dtb . Therefore, even before the clock signal clk is triggered as the rising edge, the values of the nodes N1 and N2 can be predetermined, and in order to store data, the clock signal clk as the rising edge is triggered. After that, only the value of the latch unit 130 needs to be changed. For this reason, the CP flip-flop structure proposed by the present invention not only reduces power consumption but also increases the robustness against power supply voltage noise.

2 is a circuit diagram of an Indirect precharge Flip-Flop according to the present invention. Referring to FIG. 2, the IP flip-flop 200 according to the present invention includes a clock delay unit 210, a switch unit 220, a preliminary charging unit 230, a latch control unit 240, and a latch unit 250. .

A low supply voltage VDDL is connected to the clock delay unit 210, and a high supply voltage VDDH is connected to the remaining components. The underlined clk , clk1 , ckb , and data signals represent the VDDL signal, and the remaining signals q and x represent the VDDH. Means signal.

The clock delay unit 210 includes three inverters 111, 112, 113 connected in series to invert the clock signal clk . The first inverter 211 first inverts the clock signal clk to generate the first delay signal clk1 . The first delay signal clk1 gates the NMOS transistor 231 of the preliminary charging unit 230.

The switch unit 220 is positioned between the preliminary charging signal x and the ground voltage Ground, and includes the first NMOS transistor 221, the second NMOS transistor 222, and the third NMOS transistor 223. It is provided. The input data data is input to the gate terminal of the first NMOS transistor 221, the clock signal clk is input to the gate terminal of the second NMOS transistor 222, and the output signal ckb of the clock delay unit . ) Is input to the gate terminal of the third NMOS transistor 223. When all of the first, second, and third NMOS transistors 211, 212, and 213 are turned on by the respective signals, the charge of the preliminary charging signal x charged by the preliminary charging unit 230 is discharged.

The preliminary charging unit 230 includes the NMOS transistor 231 and the first and second inverters 232 and 233 formed of a cross couple. The first delay signal clk1 generated by the first inverter 211 of the clock delay unit is input to the gate terminal of the NMOS transistor 231. The NMOS transistor 231 generates a preliminary charging signal x by switching a ground power source to the first and second inverters 232 and 233 configured as cross couples. When all of the first, second, and third NMOS transistors 211, 212, and 213 of the switch unit 220 are turned on, the preliminary charging signal x of the first and second inverters 232 and 233 configured as cross couples (x). ) Is discharged.

The latch control unit 240 includes a PMOS transistor 241, a first NMOS transistor 242, and a second NMOS transistor 243. The preliminary charging signal x is input to the gate terminal of the PMOS transistor 241 and the gate terminal of the second NMOS transistor 243. The clock signal clk is connected to the gate terminal of the first NMOS transistor 242. In response to the signals x and clk , the logic high signal by the power supply voltage VDDH or the logic low signal by the ground power supply is switched to the latch unit 250.

The latch unit 250 includes a first inverter 251 and a second inverter 252 formed of a cross couple. The first and second inverters 251 and 252 configured as cross couples are connected between the PMOS transistor 241 and the first NMOS transistor 242 of the latch control unit, and are connected to the logic high signal by the power supply voltage VDDH. Stores a logic low signal by ground supply.

The overall operation of the IP flip-flop 200 according to the present invention of FIG. 2 is as follows. When the clock signal clk is logic level low, the preliminary charging signal x of the preliminary charging unit 230 becomes a logic level high as a high power supply voltage VDDH signal so that the PMOS transistor 241 is turned off.

When the clock signal clk rises, the output signal ckb of the clock delay unit 110 maintains a logic level high for a short period. During this period, the preliminary charging signal x is selectively charged or discharged according to the logic level of the input data data , and the latch unit 250 receives and stores the value of the preliminary charging signal x. After this short period, when the output signal ckb of the clock delay unit 110 becomes a logic level low, the preliminary charging signal x is no longer affected by the input data data and is formed of a cross couple. And the value is maintained by the second inverters 251 and 252.

When the clock signal clk becomes a logic level low again, the preliminary charging signal x of the preliminary charging unit 230 becomes a logic level high as a high power supply voltage VDDH signal so that the PMOS transistor 241 is turned off.

As described in the above operation, the IP flip-flop according to the present invention of FIG. 2 uses the clock signal clk , which is the low power supply voltage VDDL, to convert the preliminary charging signal x of the preliminary charging unit 230 into a high power supply voltage ( Since the output q of the flip-flop is determined by preliminary charging with VDDH and turning on or off the PMOS transistor 241 by the preliminary charging signal x, the operation speed is high.

3 is a table comparing the LC flip-flop according to the present invention and the conventional LC flip-flop. Table 300 compares the performance, such as the operating speed. The IP flip-flop has the fastest operating speed, the smallest PDP, the smallest transistors, and the smallest footprint. CP flip-flops have the lowest power consumption and use the fewest transistors. Thus, IP flip-flops are suitable for high-speed systems and CP flip-flops are suitable for low-power systems.

In the above described the present invention with reference to the specific embodiment shown in the drawings, but this is only exemplary, those of ordinary skill in the art to which the present invention pertains will be various modifications and variations therefrom. Therefore, the protection scope of the present invention should be interpreted by the claims to be described later, and all technical ideas within the equivalent and equivalent ranges should be construed as being included in the protection scope of the present invention.

As described above, the CP flip-flop according to the present invention has an effect of low power consumption.

Indirect precharge flip-flop according to the present invention has an effect of fast operation speed.

Claims (10)

In a flip-flop used in a multi supply system, A clock delay unit driven by a low supply voltage and generating an output signal by inverting and delaying a clock signal; A switch unit including a plurality of switches and switching input data in response to an output signal of the clock signal and the clock delay unit; And And a latch unit configured to store at least one output signal of the switch unit. The method of claim 1, wherein the flip-flop, And an input buffer unit driven by a low power supply voltage and configured to invert buffer and reinvert buffer the input data. The method of claim 1, The switch unit, A first switch for switching input data in response to an output signal of the clock delay unit; A second switch for switching the output signal of the first switch in response to the clock signal; A third switch for switching input data in response to an output signal of the clock delay unit; And And a fourth switch for switching the output signal of the third switch in response to the clock signal. The method of claim 3, And the first, second, third and fourth switches are NMOS transistors. The method of claim 3, The latch unit, And a second inverter configured as a cross couple, the second inverter receiving the output of the third switch of the switch unit and the second inverter receiving the output of the fourth switch of the switch unit. For flip-flops used in multiple power supply voltage systems, A clock delay unit driven by a low power supply voltage and inverting a delay of the clock signal to generate a first delay signal and an output signal; A switch unit including a plurality of switches and switching to ground power in response to input data, the clock signal, and an output signal of the clock delay unit; A precharge unit generating a precharge signal charged in response to the first delay signal of the clock delay unit and discharging the precharge signal by a ground power source switched to the switch unit; A latch controller for switching a high signal by a power supply voltage or a low signal by a ground power supply in response to the preliminary charging signal and the clock signal; And And a latch unit connected to the latch control unit for storing a high signal by a power supply voltage of the latch control unit or a low signal by a ground power source. The method of claim 6, The switch unit, A first NMOS transistor having a gate terminal connected to the input data; A second NMOS transistor having a gate terminal connected to the clock signal; And And a third NMOS transistor having a gate terminal connected to an output signal of the clock delay unit. The method of claim 6, The precharge unit, An NMOS transistor connected to a gate terminal of the first delay signal of the clock delay unit to switch ground power; A first inverter configured to receive a output of the NMOS transistor and generating the preliminary charging signal, and a second inverter configured to receive the preliminary charging signal and output the preliminary charging signal to the first inverter; Flip-flop, characterized in that. The method of claim 6, The latch control unit, A PMOS transistor having a gate terminal connected to the preliminary charging signal; A first NMOS transistor having a gate terminal connected to the clock signal; And And a second NMOS transistor having a gate terminal connected to the preliminary charging signal. The method of claim 6, The latch unit, A second inverter configured as a cross couple, a first inverter connected between the PMOS transistor and the first NMOS transistor of the latch control unit, and a second inverter receiving an output of the first inverter and inputting the output to the first inverter again Flip-flop, characterized in that it comprises a.

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