KR100670820B1 - On-Chip Network Interface Device and Method - Google Patents

Abstract

The present invention relates to an on-chip network interface device and method, comprising: a plurality of on-chip network ports; A switch for transmitting data received from one of the on-chip network ports to another on-chip network port; And an interface unit for interfacing an AMBA signal received from an IP module designed with an AMBA on-chip bus protocol to the on-chip network port, and for outputting the on-chip network signal from the on-chip network port to the IP module. Therefore, communication with a faster transmission rate can be achieved through an apparatus and method for interfacing a signal conforming to the AMBA 2.0 on-chip bus protocol and a signal conforming to the on-chip network protocol.

Description

On-chip network interface device and method {Apparatus and method for interfacing of on chip network}

1 is an AMBA 2.0 on-chip bus architecture designed with a conventional AMBA 2.0 on-chip bus protocol.

2 is a schematic diagram of an on-chip network device designed by a conventional on-chip network protocol.

3 is a structural diagram illustrating the switch in FIG. 2 in more detail.

4 is a structural diagram of an on-chip network device having an interface according to an embodiment of the present invention.

5 is a flowchart illustrating a forward direction interface operation in a master interface unit according to an exemplary embodiment of the present invention.

6 is a flowchart illustrating a backward direction interface operation in a master interface unit according to an exemplary embodiment of the present invention.

7 is a flowchart illustrating operation of a forward direction interface in a slave interface unit according to an exemplary embodiment of the present invention.

8 is a flowchart illustrating a backward direction interface operation in a slave interface unit according to an exemplary embodiment of the present invention.

The present invention relates to an on-chip network interface device and method, and more particularly, to an on-chip network in which an interface circuit is added to perform communication between IP modules designed with an AMBA 2.0 on-chip bus protocol and an on-chip network device designed with an on-chip network protocol. An interface device and method are provided.

A popular protocol for on-chip communication between circuits is the AMBA 2.0 on-chip bus protocol. In FIG. 1, an AMBA 2.0 on-chip bus structure designed with the AMBA 2.0 on-chip bus protocol will be described.

1 is an AMBA 2.0 on-chip bus architecture designed with a conventional AMBA 2.0 on-chip bus protocol. Referring to FIG. 1, the master IP module 110 (in FIG. 1, the master IP module 110 is connected to the first master IP module 111, the second master IP module 112, and the third master IP module 113). Is configured), the slave IP module 120 (in FIG. 1, the slave IP module 120 includes the first slave IP module 121, the second slave IP module 122, the third slave IP module 123, and the first slave IP module 120). AMBA 2.0 on-chip bus structure capable of communicating with the four slave IP module 124. Here, the master IP module 110 is a module for requesting data necessary for performing communication, the slave IP module ( 120) is a module that receives only a request for data necessary for performing communication. Thus, the master IP module 110 sends only a read / write request signal of data, and the slave IP module 120 receives a read / write request signal of data and sends read data.

The AMBA 2.0 on-chip bus structure as described above has a read data multiplexer for transmitting the read data by the arbiter 130, the decoder 140, the master IP module 110 and the slave IP module 120. Data Multiplexer 170, the Write Data Multiplexer 160 and the Master IP Module 110 for the Master IP Module 110 and the Slave IP Module 120 to transmit the write data, the Slave IP Module ( 120, an address / control multiplexer 150 for transmitting control information and address information.

The master IP module 110 sends a request to the arbiter 130 to use the AMBA 2.0 on-chip bus.

The arbiter 130 is ranked using the AMBA 2.0 on-chip bus between the master IP modules 110. The request signal of the master IP module 110 is connected to various input terminals receiving the request signal of the ranker 130 is ranked. When a request comes in at each input, it accepts the request signal in a predetermined order. The arbiter 130 compares AMBA 2.0 on-chip bus usage rankings and gives bus usage priority to the master IP module 110 which has made an AMBA 2.0 on-chip bus request. The master IP module 110 granted with the bus license is assigned a slave IP module (through the address / control multiplexer 150 and the read data multiplexer 170 or the address / control multiplexer 150 and the write data multiplexer 160). The slave IP module 120 to communicate with is determined by the decoder 140.

The AMBA 2.0 on-chip bus does not solve bandwidth constraints in data transmission between the master IP module 110 and the slave IP module 120 due to the physical sharing of wires. In the conventional AMBA 2.0 on-chip bus, if one master IP module occupies one physical bus, other master IP modules cannot communicate.

In order to solve the problems of the AMBA 2.0 on-chip bus as described above, there is a method of bringing the characteristics of the network as on-chip. This will be described in detail with reference to FIG. 2 below.

2 is a schematic diagram of an on-chip network device designed by a conventional on-chip network protocol. Referring to FIG. 2, an on-chip network device designed as an on-chip network protocol includes a plurality of on-chip network ports 210 and switches 220. The on-chip network port 210 receives the on-chip network signal input from the switch 220 and the up-sampler 212 and the on-chip network signal sequentially input from the IP module 250 designed as an on-chip network protocol to the switch 220. It consists of a down sampler 214 sent back to the IP module 250 in reverse order. The on-chip network device designed with the on-chip network protocol of FIG. 2 is intended to improve the fact that another master IP module had to wait for bus usage when one master IP module on the bus was licensed. In other words, if there are many master IP modules that need to use the simultaneous bus and want to communicate with other slave IP modules, the master IP modules can communicate simultaneously without waiting for the bus license and even if they want to communicate with the same slave IP module, they can be divided by certain data. God was able to do it. This is to eliminate waiting for the IP module to use the bus.

The switch 220 is a physical medium for transmitting a signal received by the on-chip network port 210 from the IP module 250 to another on-chip network port 210 '.

In an on-chip network device designed with an on-chip network protocol, while one IP module 250 uses the network, the other IP module 250 'uses the network at the same time instead of waiting for the next request to use the network. The reason why the network can be used at the same time is that a packet is used as a unit for transmitting data. That is, the switch 220, which collects packets and sends them to a desired destination, is connected to different media so that no matter how much or little data is sent by one IP module 250, it is transmitted to the network in units of packets. Because. Each transmitted packet has a tag containing a destination, a source, and characteristics of the packet, so that even if packets made in different systems are mixed with each other, the tags can be decoded and sequentially sent to a desired destination. The switch 220 is responsible for the function of decoding these tags and sequentially sending them to the desired destination.

The structure of the switch 220 will be described in more detail with reference to FIG. 3 below.

3 is a structural diagram illustrating the switch in FIG. 2 in more detail. Referring to FIG. 3, the switch 220 is composed of a plurality of inlets 222, a plurality of arbiters 224, and a switch fabric 226.

The port 222 queues the incoming data and sends a use request signal to the arbiter 224 which makes a request for use of the switch fabric 226. The arbiter 224 receives the switch fabric 226 use request signal from the inport 222 and transmits a use request allowance signal to the port 222. The switch fabric 226 serves to output data coming in through the port 222.

In more detail with respect to the operation of the switch 220, the switch 220 receives the packets having a plurality of destinations through the port 222. The packets entered in this way are sent to the desired destination through the switch fabric 226. Each port 222 connects to all destinations via the switch fabric 226. The port 222 decodes the tag and sends a use request signal to the arbiter 224. The arbiter 224 accepts the request for use if the switch fabric 226 is empty and sends a packet at the port 222 to the switch fabric 226. Therefore, as many packets as the arbiter 224 can be sent to the destination at the same time. However, if the arbiter 224 is busy, packets will wait on the inport 222, causing queuing, such that on a bus, a small number of packets will wait, rather than waiting for an acknowledgment of use of the bus while one master finishes all the desired work. do.

However, many conventional IP modules are designed for the AMBA 2.0 on-chip bus protocol. In order to communicate with IP modules designed for the AMBA 2.0 on-chip bus protocol using an on-chip network, an interface circuit is required between the conventional IP modules and the on-chip network.

SUMMARY OF THE INVENTION The present invention provides an on-chip network interface device and method for adding an interface circuit to perform communication between IP modules designed with an AMBA 2.0 on-chip bus protocol and an on-chip network device designed with an on-chip network protocol.

On-chip network interface device of the present invention for solving the above technical problem, a plurality of on-chip network port; A switch for transmitting data received from one of the on-chip network ports to another on-chip network port; And an interface unit for interfacing an AMBA signal received from an IP module designed with an AMBA on-chip bus protocol to the on-chip network port, and for outputting the on-chip network signal received from the on-chip network port to the IP module. Have as characteristic.

In the on-chip network interface method of the present invention for solving the above technical problem, in the method of performing communication between the master IP module and the on-chip network designed by the AMBA on-chip bus protocol and requests data required for performing the communication, a forward signal control step of receiving an AMBA signal from the master IP module and interfacing it with an on-chip network signal to output the on-chip network; And (b) receiving an on-chip network signal from the on-chip network and interfacing it with an AMBA signal to output the signal to the master IP module.

In addition, the on-chip network interface method of the present invention for solving the above technical problem, a method for performing communication between the on-chip network and the slave IP module designed for the AMBA on-chip bus protocol and receives data required when performing the communication (A) a forward signal control step of receiving an on-chip network signal from the on-chip network and interfacing it with an AMBA signal to output to the slave IP module; And (b) receiving an AMBA signal from the slave IP module and interfacing it to an on-chip network signal to output the signal to the on-chip network.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

4 is a structural diagram of an on-chip network device having an interface according to an embodiment of the present invention. Referring to FIG. 4, the on-chip network device having an interface includes a master interface unit 410, an on-chip network port 420 connected to the master interface unit 410, a switch 430, a slave interface unit 450, and a slave interface unit. On-chip network port 440 connected to the 450 is configured.

The master interface unit 410 performs an interface function between an on chip network (OCN) port 420 and a master IP module 460 designed with an AMBA 2.0 on-chip bus protocol. That is, the master interface unit 410 interfaces the AMBA signal received from the master IP module 460 to the on-chip network signal and outputs the on-chip network port 420 to output the on-chip network signal received from the on-chip network port 420. It interfaces with the AMBA signal and outputs it to the master IP module 460.

For the on-chip network signal and the AMBA signal at the master interface unit 410 that performs the interface function between the on chip network (OCN) port 420 and the master IP module 460 designed with the AMBA 2.0 on-chip bus protocol It is shown through the following Table 1. Table 1 shows an example of an on-chip network signal and an AMBA signal according to an embodiment of the present invention, but various modifications are possible for each signal without being limited to Table 1.

In Table 1, the on-chip network signals are forward direction signals input to the on-chip network port 420 starting with F except for the FHOLDMS signal, and the backwards output from the on-chip network port 420 starting with B. ) Direction signals and FHOLDMS It consists of a signal. When the AMBA signal is viewed based on the master IP module 460, only the HREADY signal and the HRDATA signal are input to the master IP module 460, and the remaining signals are output from the master IP module 460.

  Signal name           Description of the signal     On-Chip Network Signal FHOLDMS A signal that stops the master IP module from sending signals and prevents sending additional data to the on-chip network port FAEN Signal to indicate that signal of FA [31: 0] is ready FA [31: 0] Address to write or read data to forward direction address FDEN Signal that signal of FD [31: 0] is ready FD [31: 0] Forward direction data FWRITE Signal indicating whether current data communication is write or read FBST [1: 0] Signal to send burst mode and burst length information FSEN Signal that signal of FS [31: 0] is ready FS [31: 0] For data communication, various control signals according to the characteristics of the IP module are required, and communication signals for transmitting them (specifically, signals for sending burst length information and read / write operations). BDEN Signal that signal of BD [31: 0] is ready BD [31: 0] Backward direction data   AMBA signal HBURSREQ Bus License Request HTRANS [1: 0] Transmission mode HWRITE Signal indicating whether current data communication is write or read HBURST [2: 0] Signal to send burst mode and burst length information HADDR [31: 0] address HWDATA [31: 0] Write data to be saved from the master IP module to slave IP module through on-chip network HREADY Signal sent from the master IP module through the on-chip network port to signal that it is ready to transmit from the slave IP module. HRDATA [31: 0] Read data transferred from slave IP module through on-chip network port as data read from slave IP module

The slave interface unit 450 performs an interface function between the on-chip network port 440 and the slave IP module 470 designed with the AMBA 2.0 on-chip bus protocol. That is, the slave interface unit 450 interfaces the on-chip network signal received from the on-chip network port 440 with an AMBA signal, outputs the signal to the slave IP module 470, and outputs the AMBA signal received from the slave IP module 470 on-chip. It interfaces with the network signal and outputs it to the on-chip network port 440.

The on-chip on-chip network signal and AMBA signal at the slave interface unit 410 performing an interface function between the on-chip network port 440 and the slave IP module 470 designed with the AMBA 2.0 on-chip bus protocol are shown in Table 2 below. . Table 1 shows an example of an on-chip network signal and an AMBA signal according to an embodiment of the present invention, but various modifications are possible for each signal without being limited to Table 2.

Here, the on-chip network signals are forward direction signals starting with F except for the FHOLDMSNI signal, which are signals input to the on-chip network port and backward direction output from the on-chip network port starting with B. Signals and FHOLDMSNI It is a signal. When the AMBA signal is viewed based on the slave IP module 470, only the HREADY signal and the HRDATA signal are input to the slave IP module 470, and the remaining signals are output from the slave IP module 470.

  Signal name           Description of the signal     On-chip network signal FHOLDMSNI Signal to prevent the on-chip network port from sending any more data when data input to the slave IP module cannot be processed FAEN Signal to indicate that signal of FA [31: 0] is ready FA [31: 0] Address to write or read data to forward direction address FDEN Signal that signal of FD [31: 0] is ready FD [31: 0] Forward direction data FSEN Signal that signal is ready for FS [3: 0] FS [3: 0] For data communication, various control signals are required according to the characteristics of the IP, and a communication signal for sending them (in a specific embodiment, a signal for sending burst length information and a read / write operation). FTEN Signal that signal of FT [12: 0] is ready FT [12: 0] As a forward direction tag signal, a tag contains the packet's destination, source, and packet characteristics that the interface module should know. The on-chip network port receives tag information using BT [12: 0] to make a packet for transmitting BD [32: 0]. The slave interface module stores the value of the FT [12: 0] signal and sends it as a BT [12: 0] signal when sending the BD [32: 0] signal to the on-chip network port. BHOLDSL Signal to prevent the slave IP module from sending data when the on-chip network port can no longer handle the signal from the slave IP module BDEN Signal that signal of BD [31: 0] is ready BD [31: 0] Backward direction data BTEN Signal that signal of BT [12: 0] is ready BT [12: 0] As a backward direction tag signal, a tag contains the destination, origin, and characteristics of the packet, which the interface module must know. On-chip network port receives tag information using BT [12: 0] to make a packet for transmitting D [32: 0]. The slave interface module stores the value of the FT [12: 0] signal and sends it as a BT [12: 0] signal when sending the BD [32: 0] signal to the on-chip network port.  AMBA signal HSEL It operates when this signal is applied as slave IP module operation signal. HWRITE Signals for Read and Write Operations HADDR [31: 0] address HWDATA [31: 0] Write data transferred from master IP module to slave IP module via on-chip network HREADY Signal from slave IP module to inform when slave IP module is not able to process data input to slave IP module HRDATA [31: 0] Read data to be transferred from master IP module through on-chip network as data read from slave IP module

The switch 430 is a physical medium that transmits the signals received from each chip network port 420 and the on chip network port 440 to the other on chip network port 420 and the on chip network port 440.

The on-chip network port 420 connected to the master interface unit 410 serializes the data received from the master interface unit 410 to the upsampler 422 and the data received from the switch 430. And a down sampler 424 sent to the master master interface unit 410.

In addition, the on-chip network port 440 connected to the slave interface unit 450 sequentially receives the data received from the switch 430 and the up-sampler 442 which sequentially transfers the data received from the slave interface unit 450 to the switch 430. And a down sampler 444 sent to the slave interface unit 450 in reverse order.

5 is a flowchart illustrating a forward direction interface operation in a master interface unit according to an exemplary embodiment of the present invention. The various signals described in FIG. 5 will be referred to Table 1.

Referring to FIG. 5, first, an FSEN signal, a FAEN signal, a FDEN signal, and an AMBA signal, which are forward direction signals, are initialized (S500). Here, the FSEN signal, the FAEN signal, and the FDEN signal are initialized to '0', and the HREADY signal is initialized to '1'.

Next, it is determined whether the master IP module has requested the on-chip bus right (S510). Herein, whether the master IP module requests the on-chip bus right is determined by whether the HBUSREQ signal is '1'.

If it is determined in step S510 that the master IP module has not requested the on-chip bus right to use, that is, if the HBUSREQ signal is '0', step S510 is repeated. On the other hand, if it is determined in step S510 that the master IP module requests the on-chip bus right to use, that is, when the HBUSREQ signal is '1', the process proceeds to step S520.

In step S520 it is determined whether the on-chip network can process additional data transmission (S520). Here, whether the on-chip network can handle additional data transmission is determined based on whether the FHOLDMS signal is '0'.

If it is determined in step S520 that the on-chip network is unable to process additional data transmission, that is, the FHOLDMS signal is '1', step S520 is repeated. On the other hand, if it is determined in step S520 that the on-chip network can process additional data transmission, that is, if the FHOLDMS signal is '0', the process proceeds to step S530.

In step S530, the HTRANS signal is received from the master IP module to determine a corresponding transmission mode. Here, the HTRANS signal is composed of four transmission modes. If the transmission mode is the IDLE mode or the BUSY mode, step S530 is repeated. On the other hand, if the transmission mode is a non-sequential transmission mode (NON-SEQUENTIAL MODE) in step S530, and proceeds to step S540, and proceeds to step S545 if the transmission mode is a sequential transmission mode (SEQUENTIAL MODE). In the non-sequential transmission mode, the HBURST signal and the HWRITE signal, which are transmission method signals, must be input. In the sequential transmission mode, the HWRITE signal must be input.

In step S540, the HBURST signal and the HWRITE signal input from the master IP module are interfaced with the FS signal, which is an on-chip network signal, and output to the on-chip network.

In step S545, the HWRITE signal received from the master IP module is input and interfaced with the FS signal, which is an on-chip network signal, to output the on-chip network.

Next, in step S540 and step S545, it is determined whether the read transmission or the write transmission is performed through the received HWRITE signal (S550). Here, whether the read transfer or the write transfer is determined based on whether the HWRITE signal is '0' or '1', respectively.

As a result of the determination in step S550, in the case of write transfer, i.e., when the HWRITE signal is '1', the flow advances to step S560. On the other hand, when the determination result in step S550 is a read transmission, that is, when the HWRITE signal is '0', the process proceeds to step S565.

In step S560, the HWDATA signal is received from the master IP module and interfaced with the FD signal, which is an on-chip network signal, to be output on the on-chip network (S560). In step S560, the HREADY signal is set to '1'.

In step S565, the HREADY signal is set to '0' until the read request data is returned.

Next, in step S560 and step S565, the HADDR signal is received from the master IP module and interfaced with the FA signal, which is an on-chip network signal, to output the on-chip network (S570).

A portion not described in FIG. 5 will be referred to FIG. 4.

6 is a flowchart illustrating a backward direction interface operation in a master interface unit according to an exemplary embodiment of the present invention. Referring to FIG. 6, it is determined whether a BD signal which is a backward direction data signal is input (S600).

If it is determined in step S600 that the BD signal as the backward direction data signal is input, the BD signal is interfaced with the HWDATA signal as the AMBA signal and transmitted to the master IP module (S610). In operation S610, the HREADY signal is set to '1'.

On the other hand, if it is determined in step S600 that the BD signal is not input, step S600 is repeated.

Parts not described in FIG. 6 will be referred to FIG. 4.

7 is a flowchart illustrating operation of a forward direction interface in a slave interface unit according to an exemplary embodiment of the present invention. Referring to FIG. 7, first, an HWRITE signal, an HWDATA signal, a HADDR signal, an HBURST signal, and an FT_TEMP signal are initialized (S700).

Next, it is determined whether the on-chip network can transmit additional data (S710). Here, whether the on-chip network can transmit additional data is determined based on whether the BHOLDSL signal is '1'.

If the BHOLDSL signal is '1' as a result of the determination in step S710, the slave interface unit repeats step S710 without sending additional data to the on-chip network. On the other hand, if the BHOLDSL signal is '0' as the determination result in step S710, the slave interface unit proceeds to step S720.

In step S720, it is determined whether the slave IP module can receive and process additional data (S720). Here, whether the slave IP module can receive and process additional data is determined based on whether the signal of HREADY is '1'.

If the HREADY signal is '0' as a result of the determination in step S720, the slave IP module cannot receive and process additional data and repeats step S720. On the other hand, if the HREADY signal is '1' as the determination result in step S720, the slave interface unit proceeds to step S730.

In step S730, it is determined whether or not an address signal is written or read from the on-chip network to the forward direction address. Here, it is determined whether the FAEN signal is '1' whether the address signal is written or read from the on-chip network to the forward direction address. That is, if the FAEN signal is '1', it means that an address signal to write or read data to the direction address is input. If the FAEN signal is '0', it means that an address signal to write or read data to the direction address is not input.

If the FAEN signal is '0' as a result of the determination in step S730, step S730 is repeated. On the other hand, if the FAEN signal is '1' as a result of the determination in step S730, the flow proceeds to step S740.

In step S740, the FA signal received from the on-chip network is interfaced with the HADDR signal, which is an AMBA signal, and transmitted to the slave IP module.

Next, it is determined whether a control signal other than an address and data is input from the on-chip network (S750). Here, whether the control signal is input from the on-chip network is determined based on whether the FSEN signal is '1'. That is, if the FSEN signal is '1', it means that there is an HWRITE signal and / or an HBURST signal.

If the determination result in step S750 is that the FSEN signal is '1', the flow proceeds to step S755. On the other hand, if the FSEN signal is '0' as the determination result in step S750, the process proceeds to step S760.

In step S755, the lowest 1 bit of the FS signal is interfaced with the HWRITE signal and the next higher 2 bits are interfaced with the HBURST signal in a preset manner. This is just one example, and various modifications are possible.

In step S755, it is determined whether a forward direction data signal is input from the on-chip network (S760). Here, whether the forward direction data signal is input or not is determined based on whether the FDEN signal is '1' or '0'.

As a result of the determination in step S760, when the FDEN signal is '1', the forward direction data received from the on-chip network is interfaced with the HWDATA signal and transmitted to the slave IP module (S765). On the other hand, if the FDEN signal is '0' as a result of the determination in step S760, the flow proceeds to step S770.

Next, in step S760 and step S765, it is determined whether a forward direction tag signal is input (S770). Here, whether the forward direction tag signal is input or not is determined based on whether the FTEN signal is '1' or '0'.

As a result of the determination in step S770, when the FTEN signal is '1', the FT signal received from the on-chip network is interfaced with the FT-TEMP signal and transmitted to the slave IP module (S775). On the other hand, if it is determined in step S770 that the FTEN signal is '0', the process ends. Here, the FT_TEMP signal is an internal signal that is not visible to the slave interface module and is used as a temporary storage space when the FT signal is retransmitted as a BT signal.

Parts not described in FIG. 7 will be referred to FIG. 4.

8 is a flowchart illustrating a backward direction interface operation in a slave interface unit according to an exemplary embodiment of the present invention. Referring to FIG. 8, first, an FHOLDSNI signal, a BDEN signal, and a BTEN signal are initialized (S800).

Next, it is determined whether the slave IP module can process additional data (S810). Here, whether the slave IP module can process additional data is determined based on whether the HREADY signal is '1' or '0'. That is, if the HREADY signal is '0', the slave IP module may not process additional data. If the HREADY signal is '1', the slave IP module may process additional data.

If the HREADY signal is '0' as the determination result in step S810, the FHOLDSNI signal is set to '1' so as not to transmit additional data in the on-chip network (S820). If the HREADY signal is '1', the FHOLDSNI signal is set to '0' to transmit additional data in the on-chip network (S825).

Next, in step S820 and step S825, it is determined whether the backward direction data is input (S830). Here, whether the backward direction data is input is determined based on whether the BDEN signal is '1' or '0'.

When it is determined in step S830 that the backward direction data is input, that is, when the BDEN signal is '1', the HRDATA received from the slave IP module is interfaced with the BD signal and transmitted to the on-chip network (S840). In addition, in step S840, the BTEN signal is set to '1' and the FT-TEMP signal is interfaced with the BT signal to be transmitted to the on-chip network. On the other hand, when it is determined in step S830 that the backward direction data is not input, that is, when the BDEN signal is '0', the process ends.

A portion not described in FIG. 8 will be referred to FIG. 4.

The invention can also be embodied as computer readable code on a computer readable recording medium. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage, and the like, and may also be implemented in the form of a carrier wave (for example, transmission over the Internet). Include. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

So far I looked at the center of the preferred embodiment for the present invention. Those skilled in the art will appreciate that the present invention can be implemented in a modified form without departing from the essential features of the present invention. Therefore, the disclosed embodiments should be considered in descriptive sense only and not for purposes of limitation. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the scope will be construed as being included in the present invention.

The on-chip network interface apparatus and method according to the present invention not only improves the communication speed between circuits in a chip, but also uses an on-chip network using an interface circuit without redesigning an IP module designed with a conventional AMBA 2.0 on-chip bus protocol. The effect is that signals can be exchanged with each other.

Claims (23)

A plurality of on-chip network ports; A switch for transmitting data received from one of the on-chip network ports to another on-chip network port; And And an interface unit for interfacing the AMBA signal received from an IP module designed with an AMBA on-chip bus protocol to the on-chip network port, and for outputting the on-chip network signal received from the on-chip network port to the IP module. On-Chip Network Protocol Communication Device. The method of claim 1, wherein the IP module A master IP module for requesting data required for performing communication through the on-chip network protocol communication device; or On-chip network protocol communication device comprising a slave IP module for receiving data required by the master IP module when performing the communication through the on-chip network protocol communication device. The method of claim 2, wherein the interface unit The master interface unit converts the AMBA signal received from the master IP module into an on-chip network signal and outputs it to the on-chip network port, and converts the on-chip network signal received from the on-chip network port into an AMBA signal and outputs it to the master IP module. ; or The slave interface unit converts the on-chip network signal received from the on-chip network port into an AMBA signal and outputs the signal to the slave IP module, and converts the AMBA signal received from the slave IP module into an on-chip network signal and outputs it to the on-chip network port. On-chip network protocol communication device, characterized in that consisting of. The method of claim 1, wherein the on-chip network port An upsampler which orders the signals received from the interface unit and sends them to the switch; And On-chip network protocol communication device comprising a downsampler to reverse the signal received from the switch to the interface unit. A method of performing communication between an on-chip network and a master IP module designed with AMBA on-chip bus protocol and requesting data required for communication, a forward signal control step of receiving an AMBA signal from the master IP module and interfacing it with an on-chip network signal to output the on-chip network; And and (b) receiving an on-chip network signal from the on-chip network and interfacing it with an AMBA signal to output the signal to the master IP module. The method of claim 5, wherein step (a) (a1) receiving a transmission mode signal (HTRANS) from the master IP module; (a2) determining whether transmission processing is necessary based on the received transmission mode signal; And (a3) If it is determined in step (a2) that transmission processing is necessary, the master IP module receives the write / read signal HWRITE, which is an AMBA signal, and interfaces it with a control signal FS, which is an on-chip network signal. Outputting the on-chip network; on-chip network protocol communication method comprising a. The method of claim 6, When the write / read signal received in step (a3) is a write signal, the master IP module receives a data signal HWDATA to be stored as an AMBA signal and forwards it to an on-chip network signal. The on-chip network protocol communication method characterized in that it further comprises the step of outputting to the on-chip network. The method of claim 7, wherein And receiving an address signal HADDR, which is an AMBA signal, from the master IP module and interfacing it to an address signal FA for writing or reading data, which is an on-chip network signal, and outputting the on-chip network to the on-chip network. Protocol communication method. The method of claim 6, When the state of the write / read signal received in step (a3) is a read signal, the address signal FA receives the address signal HADDR, which is an AMBA signal, from the master IP module, and writes or reads data, which is an on-chip network signal, FA And outputting to the on-chip network by interfacing to the on-chip network protocol. The method of claim 6, wherein before step (a1) An on-chip bus license request determination step of determining whether the master IP module requests an on-chip bus license; And If it is determined that the on-chip bus license request request in the on-chip bus license request determination step, a data transmission processing determination step of confirming whether the on-chip network can process additional data transmission; And in step (a1), if it is determined that additional data transmission can be processed in the data transmission processing determination step. The method of claim 6, The on-chip network protocol communication method, characterized in that in step (a2) of the transmission mode signal is determined that the transmission process is necessary for the transmission mode signal. The method of claim 6, In step (a2), a signal determined to be necessary for transmission processing among the transmission mode signals may be a non-sequential transmission mode signal. In step (a3), a burst transfer method signal HBURST is received from the master IP module along with a write / read signal HWRITE, which is an AMBA signal, and the write / read signal and the burst transfer method signal are on-chip network signals. And interfacing with a control signal (FS) and outputting the data on the on-chip network. The method of claim 5, wherein step (b) determining whether a backward direction signal BD, which is an on-chip network signal, is input from the on-chip network; And and (b2) when the backward direction signal is input in step (b1), interfacing the backward direction signal to a read data signal HRDATA which is an AMBA signal and outputting the same to the master IP module. On-Chip Network Protocol Communication Method. In a method for performing communication between an on-chip network and a slave IP module designed for the AMBA on-chip bus protocol and receiving data required for performing the communication, a forward signal control step of receiving an on-chip network signal from the on-chip network and interfacing it with an AMBA signal and outputting the signal to the slave IP module; And and (b) a reverse signal control step of receiving an AMBA signal from the slave IP module and interfacing it as an on-chip network signal to output the on-chip network. The method of claim 14, wherein step (a) (a1) determining whether a control signal FS, which is an on-chip network signal, is input from the on-chip network; And (a2) When the control signal is input in the step (a1), the on-chip network protocol communication method comprising the step of interfacing the control signal to the AMBA signal in a preset manner to the slave IP module. The method of claim 15, The preset method may further include interfacing the least significant bit of the control signal to a write / read signal (HWRITE) which is an AMBA signal and output the same to the slave IP module. The method according to claim 15 or 16, The preset method is to interface the least significant bit of the control signal to the write / read signal (HWRITE), which is an AMBA signal, and the next two bits of the least significant bit of the control signal, to the burst transfer mode signal (HBURST), an AMBA signal. On-chip network protocol communication method characterized in that. The method of claim 15, It is determined whether a forward direction data signal FD, which is an on-chip network signal, is input from the on-chip network, and when it is determined that the forward direction data signal is input, the forward direction data signal is interfaced as a data signal HWDATA to be stored as an AMBA signal. On chip network protocol communication method characterized in that it further comprises. The method according to claim 15 or 18, It is determined whether a forward direction tag signal FT, which is an on-chip network signal, is input from the on-chip network, and when it is determined that the forward direction tag signal is input, the forward direction tag signal is stored as forward direction tag temporary storage data (FT-TEMP). An on-chip network protocol communication method further comprising the step of interface. 17. The method of claim 16, wherein the step (a1) A data transmission determining step of determining whether the on-chip network can transmit additional data; And If it is determined that the on-chip network can transmit additional data in the data transmission determination step, determining whether the slave IP module can receive and process the additional data; If it is determined that the slave IP module can receive and process additional data, performing the step (a1). The method of claim 15, wherein step (b) determining whether a read data signal HRDATA, which is an AMBA signal, is input from the slave IP module; And (b2) if it is determined that the data read in step (b1) is input, interfacing the read data signal to a backward direction data signal BD, which is an on-chip network signal, and transmitting the data to the on-chip network. On-Chip Network Protocol Communication Method. The method of claim 21, before step (b1), And determining whether a transmission ready signal (HREADY), which is an AMBA signal, is input from the slave IP module. The method of claim 22, wherein before step (b1), And setting the FHOLDSNI signal in a predetermined manner so that the SNI circuit no longer sends data when the transmission ready signal (HREADY) is input.

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