KR100665006B1 - Phase locked loop device - Google Patents

Abstract

The present invention relates to a phase locked loop device capable of optimizing the synchronous speed by optimizing the stability of the loop and the bandwidth of the loop by adjusting the amount of current of the charge pump according to the rate of change of the oscillation frequency, the technical configuration of which is proportional to the input voltage. A voltage controlled oscillator for outputting a frequency; A reference signal generator for generating a reference signal as a reference for phase synchronization; An output divider for varying the division ratio according to the division ratio control signal and for dividing the output signal of the voltage controlled oscillator into the set division ratio and converting it into a low frequency signal; A phase detector for comparing a phase of an output signal divided by the output divider with a phase of a reference signal output from the reference signal generator and outputting a pulse signal corresponding to a phase difference; A lock detector for comparing synchronization with an output signal divided by the output divider and a phase of a reference signal output from the reference signal generator to determine whether to synchronize; A division ratio detector configured to receive a division ratio control signal applied to the output divider and detect a division ratio change rate corresponding to a change rate of an oscillation frequency; A charge pump for converting the phase difference signal of the phase detector into a current signal by adjusting the amount of current in accordance with the phase difference detected by the phase detector, whether or not synchronization is detected by the lock detector, and the rate of change of the oscillation frequency detected by the frequency division detector; And a loop filter converting the current signal converted by the charge pump into a voltage signal and applying the frequency control voltage of the voltage controlled oscillator to remove noise mixed in the loop.

Voltage controlled oscillators, phase locked loops, loop bandwidth, sync speed, noise

Description

Phase lock loop device {Apparatus for phase lock loop}

1 is a block diagram showing the basic configuration of a phase locked loop.

2 is a block diagram illustrating an improved structure of a conventional phase locked loop.

3 is a block diagram showing a phase locked loop device according to the present invention.

4 is a logic circuit diagram showing a detailed configuration of a frequency division detection unit in a phase locked loop according to the present invention.

5 is a circuit diagram showing a circuit configuration of an improved charge pump in a phase locked loop according to the present invention.

Explanation of symbols on the main parts of the drawings

30: voltage controlled oscillator 31: reference signal generator

32: output divider 33: phase detector

34: lock detector 35: dividing ratio detector

36: charge pump 37: loop filter

The present invention relates to a phase-locked loop, and more particularly, to a phase-locked loop device capable of optimizing the synchronous speed by optimizing the stability of the loop and the bandwidth of the loop by adjusting the current amount of the charge pump according to the rate of change of the oscillation frequency. will be.

A phase locked loop generates an oscillation frequency of a predetermined frequency, and compares the phase of the oscillation frequency of the voltage controlled oscillator with the phase of the reference frequency to synchronize the phase of the oscillation frequency with the reference clock to perform frequency variation. It outputs a stable oscillation frequency with a fixed phase.

Such a phase locked loop device basically includes a voltage controlled oscillator (VCO) 10 that outputs a frequency proportional to an input voltage and a reference frequency (for example, 4 MHz) as shown in FIG. 1. A reference signal generator 11 for generating a reference clock, and an output ratio for dividing the output signal fo of the voltage controlled oscillator 10 into the set division ratio by converting the output signal fo of the voltage controlled oscillator 10 into the divided frequency ratio and converting it into a low frequency signal; Phase detector for comparing the phase of the period 12, the output signal divided by the output divider 12 and the phase of the reference signal output from the reference signal generator 11 to output a pulse signal corresponding to the phase difference (Phase Detector) PD (13) and a charge pump (14) for generating a current signal proportional to the phase difference by adjusting the amount of current in accordance with the pulse signal corresponding to the phase difference output from the phase detector (13), A loop filter (LP) 15 removes a noise signal included in a loop and applies a current signal of the charge pump 14 to the VCO 10 as a frequency control voltage.

In the above, the reference signal generator 11 is connected to a crystal resonator 11a exhibiting stable operation characteristics to generate a stable reference clock signal, and an oscillator 11b for generating a predetermined frequency signal, and the oscillator 11b. And a frequency divider 11c for dividing the frequency signal generated by the multiplier at a predetermined frequency division ratio and outputting a clock signal having a reference frequency.

In addition, the output divider 12 divides the high output frequency fo of the voltage controlled oscillator 10 to have the same frequency as the reference signal in order to enable phase comparison, and the division ratio is adjusted according to the division ratio control signal. As a programmable divider, for example, a pulse swirl dispenser is used. The division ratio control signal applied to the output divider 12 is changed according to the variation of the oscillation frequency.

In such a phase locked loop, it is necessary to appropriately adjust the phase locked speed in order to change the oscillation frequency quickly.

Figure 2 shows the configuration of the conventional phase-locked loop device improved for this.

Referring to FIG. 2, the improved phase locked loop includes a VCO 20, a reference signal generator 21, an output divider 22, a phase detector 23, and a charge pump operating as described above. (25) and a phase synchronous loop device comprising a loop filter (26), further comprising a lock detector (24) for determining whether or not synchronization is achieved from the phase detection result of the phase detector (23), and The total bandwidth of the loop is adjusted by adjusting the amount of current in the charge pump 25 and the filter bandwidth of the loop filter 26 according to the synchronization detected by the lock detector 24.

In the above configuration, the synchronous speed is adjusted in two ways. First, if the detection of the lock detector 24 is not in the phase synchronous state, the amount of current applied to the charge pump 25 is increased to increase the bandwidth of the entire loop. As a result, the synchronizing time is increased, and conversely, in the case of phase synchronizing, the amount of current flowing through the charge pump 25 is reduced to slow the synchronizing time. Second, by adjusting the filter bandwidth of the loop filter 26 according to the detection result of the lock detector 24, the bandwidth of the entire loop is adjusted, and as a result, the synchronous speed is adjusted.

By the way, since the above-described conventional structure adjusts the synchronous speed only according to synchronization, it is possible to increase the synchronous speed in the unsynchronized state so that faster synchronization can be achieved, but in all oscillation frequency bands. There is no optimal sync time.

For example, in the high frequency band, in order to have an optimal synchronizing time, the charge pump 25 should have a high current gain. If this high current gain is set, the loop gain becomes too large during low frequency oscillation so that the stability of the loop is improved. And as a result, motivation can be out of sync.

Therefore, conventionally, the loop bandwidth without phase synchronization is set to an average value of the loop bandwidth required at each of the low frequency and the high frequency so as not to deviate from the loop stability, but in this case, the optimum synchronization speed is not obtained. There is a problem.

The present invention has been proposed to solve the above-mentioned problems, and its object is to optimize the synchronous speed by optimizing the stability of the loop and the bandwidth of the loop by adjusting the current amount of the charge pump according to the rate of change of the oscillation frequency. It is to provide a phase locked loop device.

As a construction means for achieving the above object of the present invention, the phase locked loop device according to the present invention

A voltage controlled oscillator for outputting a frequency proportional to the input voltage;

A reference signal generator for generating a reference signal as a reference for phase synchronization;

An output divider for varying the division ratio according to the division ratio control signal and for dividing the output signal of the voltage controlled oscillator into the set division ratio and converting it into a low frequency signal;

A phase detector for comparing a phase of an output signal divided by the output divider with a phase of a reference signal output from the reference signal generator and outputting a pulse signal corresponding to a phase difference;

A lock detector for comparing synchronization with an output signal divided by the output divider and a phase of a reference signal output from the reference signal generator to determine whether to synchronize;

A division ratio detector configured to receive a division ratio control signal applied to the output divider and detect a division ratio change rate corresponding to a change rate of an oscillation frequency;

A charge pump for converting the phase difference signal of the phase detector into a current signal by adjusting the amount of current in accordance with the phase difference detected by the phase detector, whether or not synchronization is detected by the lock detector, and the rate of change of the oscillation frequency detected by the frequency division detector;

And a loop filter converting the current signal converted by the charge pump into a voltage signal and applying the frequency control voltage of the voltage controlled oscillator to remove noise mixed in the loop.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description and the annexed drawings, detailed descriptions of well-known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

3 is a block diagram showing the configuration of the phase-locked loop device according to the present invention.

Referring to FIG. 3, the phase locked loop device of the present invention includes a voltage controlled oscillator 30 for outputting a frequency proportional to an input voltage and a reference frequency (for example, 4 MHz) as a reference for phase synchronization. The frequency division ratio is varied according to the reference signal generator 31 for generating a clock and the division ratio control signal, and an output divider for dividing the output signal fo of the voltage controlled oscillator 30 at the set division ratio and converting it into a low frequency signal. (32), and a phase detector (33) for outputting a pulse signal corresponding to a phase difference by comparing the phase of the output signal divided by the output divider (32) and the reference signal output from the reference signal generator (31); And a lock detector 34 for comparing synchronization with the phase of the output signal divided by the output divider 32 and the reference signal output from the reference signal generator 31, and the output divider 32. Dispensing costs authorized by A division ratio detector 35 that detects a division ratio change rate corresponding to the rate of change of the oscillation frequency by receiving the input signal, and whether the phase difference detected by the phase detector 33 and the synchronization detected by the lock detector 34 are equal to the division rate; The non-detector 35 adjusts the amount of current according to the division ratio change rate, converts a phase difference into a current signal, and converts the current signal converted by the charge pump 36 into a voltage signal to control the voltage. Loop filter 37 is applied to the frequency control voltage of the oscillator 30 to remove noise mixed in the loop.

That is, the configured phase-locked loop device varies the oscillation frequency and performs the operation of fixing the phase of the oscillation frequency, and maintains loop stability while optimally adjusting the synchronizing speed according to synchronization and the rate of change of the oscillation frequency.

To this end, the lock detector 34 detects whether the phase of the oscillation frequency output is synchronized, and the divider ratio detector 35 detects the division ratio of the output divider 32 corresponding to the output oscillation frequency. The charge pump 36 is configured to adjust the amount of current according to the phase difference, synchronization, and rate of change of the oscillation frequency.

The configuration of the phase-locked loop device will be described in more detail. The voltage controlled oscillator 30 is provided with a capacitance variable element corresponding to a voltage such as a varactor diode to adjust the oscillation frequency according to the voltage control signal.

The reference signal generator 31 generates a reference clock of a predetermined frequency as a reference for comparing phase synchronization. As described above, the reference signal generator 31 generates a predetermined frequency signal through the crystal resonator 31a having stable characteristics. An oscillator 31b and a reference divider 31c for dividing the frequency signal output from the oscillator 31b to output a reference clock signal of a predetermined frequency (for example, 4 MHz).

Since the lock detector 34 compares the phases of the reference signal fr with the divided output signal fvco in the same manner as in the conventional art, the lock detector 34 detects synchronization, and thus the detailed configuration thereof is omitted.

Next, the division ratio detector 35 detects the elevation of the oscillation frequency to be output from the phase synchronization loop device from the control signal applied to the output divider 32, that is, the division ratio control signal, and corresponds to the charge pump corresponding thereto. For outputting the current gain control signal Ndiff at 36, the configuration can be configured as shown in FIG.

Referring to FIG. 4, the division ratio detector 35 includes a plurality of D flip-flops 41 to which bit signals of the division ratio control signal N [2: 0] of a predetermined bit (for example, three bits) are input. 43) and a plurality of exclusive orgates 44 to 46 which logically combine the bit signals of the division ratio control signal N [2: 0] and the output signals of the D flip-flops 41 to 43 of the corresponding bits. .

The division ratio detector 35 varies according to the number of bits of the division ratio control signal N and the number of cases where the charge pump 36 is variable.

5 is a circuit diagram showing an embodiment of the charge pump 36.

Referring to this, the charge pump 36 is composed of a plurality of current sources connected in parallel, a plurality of switching elements for switching the current source on / off, respectively, the charge pump circuit unit 52 and the phase difference between the phase detector 33 The charge pump circuit part in accordance with the signals UPb and DN, a signal indicating a synchronous state (lock state or unlock state) of the lock detector 34, and an output signal Ndiff of the frequency division detector 35. A switching control unit 51 for controlling the amount of current by controlling the switching element of (52) on / off.

)와 위상검출기(33)의 다운 위상차신호(DN)을 논리곱하는 복수의 앤드게이트(517~519)와, 상기 복수의 앤드게이트(517~519)의 출력신호와 상기 분주비검출기(35)의 출력신호를 비트단위로 논리곱하는 복수의 앤드게이트(520~522)로 이루어진다.More specifically, the switching control unit 51 of the charge pump 36 includes a plurality of NOR gates 511 to invert and invert the synchronization state signal lock and the up phase difference signal UPb of the phase detector 33. 513 and a plurality of NAND gates 514 for inverting the bit signals Ndiff [2: 0] of the output signals of the NOR gates 511 to 513 and the output signal of the frequency division detector 35. 516) and an inverse signal of the synchronization state signal (

) And a plurality of AND gates 517 to 519 for ANDing the down phase difference signal DN of the phase detector 33, output signals of the plurality of AND gates 517 to 519, and the frequency division detector 35. It consists of a plurality of AND gates 520 to 522 that logically multiply the output signal bit by bit.

The charge pump circuit 52 includes a plurality of first current sources I1 to I4 connected to the power supply terminal VDD at the same time, and a plurality of second currents provided between the plurality of current sources I1 to I4 and the ground terminal. The current source I5 to I8 and the plurality of first current sources I1 to I4 and the power supply terminal VDD, and between the second current source I5 to I8 and the ground terminal to control the switching controller 51. It consists of a plurality of switching elements M1 to M8 that operate on / off in response to a signal.

The configuration of the switching control unit 51 of the charge pump 36 varies depending on the output bit of the frequency division detector 35 and the number of current sources to be controlled by the charge pump circuit unit 52.

4 and 5 have the simplest structure, and the division ratio control signal is a 3-bit signal, and a configuration example in which a plurality of current sources of the charge pump 36 are controlled in one-to-one correspondence with each bit is shown. It is seen.

The operation of the phase locked loop device configured as described above is as follows.

In the following description, it is assumed that the reference frequency fr is 10 MHz.

At this time, in the first case, the oscillation frequency fvco is 10 MHz (in this case, the division ratio N of the output divider 32 is 1, and the division ratio control signal is 3 bits '001') and 70 MHz (the division ratio N is 7). And the division ratio control signal is 111. In the second case, the division ratio is varied from 10 MHz to 20 MHz (the division ratio N is 2 and the division ratio control signal is 010).

In the case of varying from 10MHz to 70MHz, since the frequency change is greater than 10MHz to 20MHz, the synchronous speed should be further improved, and for this purpose, the current amount of the charge pump 36 must be flowed more. Is done.

First, when varying from 10 MHz to 70 MHz, the division ratio control signal is changed from 001 to 111. Therefore, the plurality of D flip-flops 41 to 43 output the divided ratio control signal by one period in the division ratio detector 35, so that in the exclusive or gates 44 to 46, 001 and 111 are bits. Not logically combined. Accordingly, the output signal Ndiff of the frequency division detector 35 is 110. On the contrary, in the case of varying from 10 MHz to 20 MHz, the division ratio control signal is changed from 001 to 101, so that the output signal Ndiff of the division ratio detector 25 becomes 100.

In the telephone pump 36, the switching elements M1 and M5 operate on / off oppositely to each other by the phase difference signals UPb and DN, respectively, to connect the current source I1 or I5 to the loop filter 37. That is, the charge pump 36 basically converts the phase difference signal into a current signal by the current gain by the current sources I1 and I5. At the same time, when the telephone pump 36 is not synchronized (lock = 0), and the output signal of the frequency division detector 35 is 1 and the phase difference signal (UP = 1 or DN = 1) is generated at the same time, it is satisfied. The switching control signals (Isourcing, Isinking) are at a low level to turn on the corresponding switching elements M2 to M4 and M6 to M8. That is, when phase synchronization is not achieved, the amount of current is further increased according to the division ratio detected by the division ratio detector 35.

For example, when the division ratio detection signal Ndiff is 110, when phase synchronization is not performed, the switching control signal (Isourcing or Isinking) becomes 001, and the switching elements M2, M3 or M6, M7 are turned on, The amount of current in the charge pump 36 is increased to I1 + I2 + I3 or I5 + I6 + I7. On the contrary, when the division ratio detection signal Ndiff is 100, when phase synchronization is not achieved, the switching control signal (Isourcing or Isinking) becomes 011, the switching element M2 or M6 is turned on, and the charge pump 36 is turned on. The amount of current is I1 + I2 or I5 + I6. In comparison, when the oscillation frequency is changed from 10 MHz to 70 MHz, the current amount of the charge pump 36 is greater when the oscillation frequency is changed from 10 MHz to 20 MHz. Therefore, when the oscillation frequency is changed larger, the loop bandwidth can be increased to make the synchronization speed faster, and when the oscillation frequency is changed smaller, the loop bandwidth is reduced and the synchronization speed is reduced, the loop Stability can be prevented from deteriorating.

In addition, when the charge pump 36 has a phase synchronization, the minimum basic current (I1 or I5) flows, thereby improving the noise characteristics.

On the other hand, in the above description of the present invention has been described with respect to specific embodiments, various modifications and applications can be made without departing from the scope of the present invention is not limited to the above embodiments and the configuration of the present invention.

As described above, the present invention can increase the amount of current of the charge pump in proportion to the rate of change of the oscillation frequency in the phase-locked loop. As a result, when the oscillation frequency is varied greatly, the loop bandwidth is increased to increase the high speed synchronization. When the oscillation frequency change is small, by reducing the loop bandwidth to improve the noise characteristic, there is an excellent effect of providing the optimum synchronous speed according to the rate of change of the oscillation frequency.

Claims (4)

A voltage controlled oscillator for outputting a frequency proportional to the input voltage; A reference signal generator for generating a reference signal as a reference for phase synchronization; An output divider for varying the division ratio according to the division ratio control signal and for dividing the output signal of the voltage controlled oscillator into the set division ratio and converting it into a low frequency signal; A phase detector for comparing a phase of an output signal divided by the output divider with a phase of a reference signal output from the reference signal generator and outputting a pulse signal corresponding to a phase difference; A lock detector for comparing synchronization with an output signal divided by the output divider and a phase of a reference signal output from the reference signal generator to determine whether to synchronize; A division ratio detector configured to receive a division ratio control signal applied to the output divider and detect a division ratio change rate corresponding to a change rate of an oscillation frequency; A charge pump for converting the phase difference signal of the phase detector into a current signal by adjusting the amount of current in accordance with the phase difference detected by the phase detector, whether or not synchronization is detected by the lock detector, and the rate of change of the oscillation frequency detected by the frequency division detector; And a loop filter converting the current signal converted by the charge pump into a voltage signal and applying a frequency control voltage of the voltage controlled oscillator to remove noise mixed in the loop. The method of claim 1, wherein the division ratio detector A plurality of D flip-flops 41 to 43 that receive each bit signal of the division ratio control signal of a predetermined bit and delay by one clock period, A phase synchronization characterized in that it comprises a plurality of exclusive or gates (44 to 46) for comparing the current division ratio control signal and the previous division ratio control signal output from the D flip-flops (41 to 43) by bit unit and logically combine them. Loop device. The method of claim 2, wherein the charge pump A charge pump circuit unit 52 including a plurality of current sources connected in parallel, and a plurality of switching elements for switching the current sources on and off, respectively; The phase difference signals UPb and DN of the phase detector 33, the synchronous state of the lock detector 34 (a signal indicating the locked state or the unlocked state), and the rate of change of the division ratio of the frequency division detector 35 ( And a switching control unit (51) for controlling the amount of current by turning on / off each switching element of the charge pump circuit unit (52) so that the amount of current increases in proportion to Ndiff. 4. The switching controller 51 of the charge pump according to claim 3, A plurality of NOR gates 511 to 513 for logically inverting the synchronization state signal lock and the up phase difference signal UPb of the phase detector 33; Inverts the bit signals Ndiff [2: 0] of the output signals of the NOR gates 511 to 513 and the output signal of the frequency division detector 35, and inverts the plurality of NAND gates 514 to 516. , An inverse signal of the synchronization state signal (

) And a plurality of AND gates 517 to 519 for ANDing the down phase difference signal DN of the phase detector 33, A plurality of AND gates 520 to 522 logically multiplying output signals of the plurality of AND gates 517 to 519 and output signals of the frequency division detector 35 bit by bit, The charge pump circuit unit 52 includes a plurality of first current sources I1 to I4 connected to a power supply terminal VDD at the same time, and a plurality of second current sources provided between the plurality of current sources I1 to I4 and a ground terminal. (I5 to I8) and the plurality of first current sources (I1 to I4) and the power supply terminal (VDD) and between the second current source (I5 to I8) and the ground terminal are provided for the control signal of the switching control unit 51 In accordance with the configuration of the plurality of switching elements (M1 ~ M8) to turn on / off, The switching elements M1 and M5 are controlled according to the up / down phase difference signals Pb and DN, and the switching elements M2 to M4 are controlled according to the output signals of the plurality of NAND gates 514 to 516. And the switching elements M6 to M8 are controlled to be controlled according to the output signals of the AND gates 520 to 522.

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