KR100662694B1 - Thin film semiconductor structure including heat dissipation layer - Google Patents

Abstract

The present invention relates to a thin film semiconductor structure comprising a semiconductor surface layer (2) separated from a support substrate (1) by an intermediate region (3), wherein the intermediate region (3) electrically insulates the semiconductor surface layer from the support substrate. It is a multilayer. The intermediate region has at least one first layer having an electrical interface characteristic deemed sufficiently good with the semiconductor surface layer and having an appropriate thermal conductivity to ensure correct operation of the electronic device (s) to be formed from the semiconductor surface layer 2. And the intermediate region further comprises an insulating second layer located between the first layer and the support substrate and having a low dielectric constant.

Description

Thin-layered semiconductor structure comprising a heat distribution layer

The present invention relates to thin film semiconductor structures and methods of realizing such structures.

A thin film semiconductor structure is understood as a structure having a substrate and a fine semiconductor layer on its surface, in which electronic devices are manufactured (these layers are called active layers), and the substrate serves as a mechanical support. In general, the substrate is electrically insulated from the surface layer. The substrate may be made of a solid insulating material (dielectric in the case of SOS), or of a conductor or semiconductor material. When the substrate is made of a semiconductor material, the substrate may be made of the same material as the surface layer (in the case of SOI) and is generally insulated from the surface layer by an insulating layer. In the case of SOI, the mechanical substrate generally consists of a silicon substrate having a layer of silica on its surface, but may consist of a solid substrate of fused silica (silicon on quartz). Other thin film semiconductor structures are also known as structures such as AsGa on silicon, SiC on silicon, GaN on sapphire, and the like. Such structures are formed by a technique known as "wafer bonding" or by a heteroepitaxy technique.

For example, the use of thin film semiconductor structures, such as SOI structures, in the manufacture of electronic devices is increasing. SOI structures are particularly used to fabricate VLSI logic and analog circuits or power devices. SOI structures (or substrates) have several advantages relative to solid silicon substrates. One of these advantages is that the insulator under the silicon layer allows to reduce the stray capacitance of the devices made in the silicon layer, and the thicker this insulator is, the more it is reduced.

The current common process for making SOI substrates is the Separation by IMplanted OXygen (SIMOX) process. According to this process, the insulator is a buried silicon oxide (SiO ₂ ) layer obtained by uniform injection of oxygen into the silicon substrate. This technology is currently being challenged by other processes known as "wafer bonding" (hereinafter referred to as "molecular adhesion") in the English-language license, for example, the BSOI process (J. HAISMA et al., 1989, published in the Journal of Applied Physics in Japan, Vol. 28, L 725) or UNIBOND process (by M. BRUEL, 1995, Vol. 31, 1201). And so on.

SIMOX technology is still widely used. This technique is based on a very high dose of oxygen injection. This technique makes it possible to produce silicon buried layers only 100-400 nm thick. The disadvantage of this technique is the high cost due to high dose ion implantation and the need to rely on unstandardized micro-electronic equipment. Techniques in the form of molecular adhesion do not have this weakness and, fundamentally, it is possible to further control the thickness of the layers and the properties of the insulator material. The UNIBOND process further enables lower cost and improved homogeneity of the silicon layer.

All current SOI substrates use amorphous silica (SiO ₂ ) as the base material for the buried insulation layer. This material is a good insulator, easy to manufacture, and has very limited fixed charges and interface levels at the interface with silicon to provide a very good interface with silicon. Moreover, this material has a low dielectric constant, which is a useful factor for the fast speed of devices due to the reduction in stray capacitance.

Nevertheless, silica has one major weakness: silica has very low thermal conductivity on the order of 0.2 W m ⁻¹ .K ⁻¹ . This causes a substantial transient and localized temperature rise, which is a problem for the proper operation of the devices. One way to reduce this temperature rise is to reduce the thickness of the buried silica layer. However, one side of the weaknesses due to the reduction in thickness is an increase in stray capacitance (thereby decreasing the speed of the elements), and the other side is a decrease in electrical strength. Moreover, the reduction in the thickness of the insulating layer makes it difficult to realize the realization of processes in the form of molecular adhesion, in which good adhesion is more easily obtained in layers of thicknesses greater than 300 nm.

Therefore, the concept of replacing silica with another insulating material having better thermal conductivity has been conceived. The patents of EP-A-O 707 338, EP-A-O 570 321, EP-A-O 317 445 and WO-A-91 / 11822 can be references on this subject. Proposed materials (eg diamond) do not have a good interface with silicon from an electrical point of view. For this reason, a thin silica film is added to obtain an interface with the surface silicon. These solutions are rather effective from a thermal point of view, but are not easy to apply in the context of bonding techniques by molecular adhesion. It is practically very difficult to bond materials with very high thermal conductivity that have been implanted.

Also, there are generally structures in the form of SiC on silicon or AsGa on silicon with an intermediate insulating layer. Such structures are often used to fabricate very high frequency power devices. Because of this, heat dissipation in the device is inevitable, but the thermal conductivity of silicon or / and the dielectrics used is insufficient to provide sufficient junction temperature without the occurrence of damage.
Document US-A-5 773 151 discloses a semiconductor structure comprising a silicon surface layer separated from a support substrate by an intermediate region. The middle region is in particular a multilayer comprising layers of sufficient thermal conductivity.
Document EP-AO 553 854 discloses a thin film semiconductor structure comprising a semiconductor surface layer separated from a support substrate by an intermediate region, and discloses that the intermediate region is a multilayer which electrically insulates the semiconductor surface layer from the support substrate. This intermediate region may comprise an insulating layer, for example SiO 2, in contact with the support substrate.
Document WO-A-94 / 15 359 discloses that a device is formed by a substrate of silicon which successfully supports a layer of polycrystalline diamond, a layer of polycrystalline silicon and a layer of monocrystalline silicon, in the form of islands. An integrated circuit structure is disclosed.

In order to overcome this problem, according to the present invention, in order to separate the thermal conductivity function and the electrical insulation function, a semiconductor structure having a plurality of layers between the semiconductor surface layer and the supporting substrate on which the electronic device is to be made is provided. It will be appreciated that such separation can optimize these two functions through the selection of appropriate materials, and that these materials must allow for good interfacial properties (mechanical strength). The material in contact with the semiconductor layer should additionally have good electrical interface properties. Thus, the layer in contact with the semiconductor surface layer may be formed of an insulating layer that provides good electrical insulation and provides good electrical interface properties. A layer of material with thermal conductivity can be used to overcome the temperature rise problem caused by electronic devices. If the layer with good thermal conductivity does not provide a connection property with the support substrate, another layer can be used. This other layer may be a layer having low thermal conductivity. If this layer is an insulator, the role of this layer is to provide a sufficient thickness of a low permittivity insulator under the semiconductor surface layer to maintain low stray capacitance and facilitate bonding when using molecular bonding techniques. To be maintained.

Therefore, the object of the present invention is a semiconductor thin film semiconductor structure comprising a semiconductor surface layer separated from a support substrate by an intermediate region, the intermediate region being a multi-layer that electrically insulates the semiconductor surface layer from the support substrate. At least one agent having a thermal conductivity sufficient to provide an accurate operation of an electronic device or devices that may be capable of, and having an electrically characteristic interface deemed sufficiently good, to be made from the semiconductor surface layer. And an intermediate region, wherein the intermediate region is additionally present between the first layer and the support substrate and comprises a second dielectric layer of low dielectric constant.

Advantageously, the thickness of the first layer is selected as a function of the dimensions of the heat dissipation regions of the electronic elements. For example, the thickness for the first layer can be advantageously chosen to be on the order of or larger than the dimensions of the largest heat dissipation region. If a third layer is used, the third layer should be as thin as possible to optimize the role of the first layer.

The second layer should be able to provide a sufficient degree of adhesion between the intermediate region and the support substrate. Good adhesion may be understood as mechanical adhesion with few possible macroscopic defects (ie, local adhesion failures).

The intermediate region may comprise a third layer, the third layer insulates between the first layer and the semiconductor surface layer, and the third layer imparts the aforementioned electrical properties to the intermediate region. If the semiconductor structure is an SOI structure, the third layer is advantageously a silicon oxide layer obtained by, for example, thermal oxidation.

If the semiconductor structure is an SOI structure, the second layer may be silicon oxide.

The first layer may not be an insulator. The thickness of the first layer is adjusted as a function of the heat generating regions of the semiconductor layer. The first layer may in particular be a multilayer.

More precisely, in order for the layer of good thermal conductivity to serve as the layer that effectively diffuses the heat generated in the devices, the thickness of the layer of good thermal conductivity must be sufficient. Conversely, the possible thickness of the relatively low thermal conductivity intermediate layers between this layer and the semiconductor layer should be minimized. Indeed, the thicknesses of each of these layers for good thermal action depend on the thickness of the devices and their operation (size of the thermal dissipation areas) and the thermal conductivity of different materials (semiconductor layer, dissipation layer, sublayers and substrate). something to do. The first layer may be made of any material selected from polycrystalline silicon, diamond, alumina, silicon nitride, aluminum nitride, boron nitride or silicon carbide.

The first layer may be in contact with the semiconductor surface layer, and may provide an interface of the electrical characteristics. If the semiconductor structure is an SOI structure, the first layer may be a cubic silicon carbide layer.

Advantageously, in order to sufficiently lower the stray capacitance present between the semiconductor surface layer and the supporting substrate in order to provide an operation which is considered to be the correct operation of the electronic device or elements made from the semiconductor surface layer, the second layer of the intermediate region has a low It may have an insulator of sufficient thickness with a constant.

Another object of the present invention is a method of manufacturing a semiconductor structure as defined above, which method provides a support substrate of the structure and / or on one side of a first substrate intended to provide a semiconductor surface layer. Fabricating layers of an intermediate region on one side of a second substrate intended to bond, bonding the first substrate on the second substrate with the surfaces facing each other, and forming the semiconductor surface layer. It is characterized by.

Forming the semiconductor surface layer may include reducing the thickness of the first substrate.

Bonding the first substrate onto the second substrate may be implemented by molecular adhesion. In this case, manufacturing the layers of the intermediate region may include depositing at least one bonding layer that allows molecular adhesion. Preferably, the bonding layer is a silicon oxide layer.

The first layer is polycrystalline silicon deposited by LPCVD, diamond deposited by PECVD, alumina deposited by reactive cathode sputtering, silicon nitride deposited by CVD, aluminum nitride deposited by CVD, It may be a layer of any one material selected from boron nitride deposited by CVD and silicon carbide deposited by CVD.

The thickness reduction of the first layer can be obtained using any one or multiple techniques of separation involving thermal treatment along the cleavage surface induced by rectification, chemical attack, polishing, and ion implantation. have.

The present invention will be better understood and other advantages and features will become apparent by reading the following description, which is not to be taken as a limiting example and accompanying the accompanying drawings in which:

1 shows a cross-sectional view of a semiconductor structure with a heat dissipation layer according to the invention.

2A-2D show respective process steps of a semiconductor structure according to the first embodiment of the present invention.

3A to 3B show respective process steps of a semiconductor structure according to the second embodiment of the present invention.

1 shows a first example of a semiconductor structure according to the present invention. This structure comprises, for example, a support substrate 1 of silicon, a surface layer 2 of silicon and an intermediate region 3. The intermediate region 3 is adhered to at least one layer of good thermal conductivity 4, an insulating layer 5 and a supporting substrate 1 which give a good electrical property interface with the semiconductor surface layer 2, and low thermal An insulating layer 6 which may have conductivity.

In the case of an SOI structure realized by a molecular adhesion process, the layer 6 may in particular consist of silica. This layer 6 may of course be multiple layers.

When the layer 4 of good thermal conductivity can have a good electrical interface directly with the semiconductor layer 2 of silicon, the layer 5 can be omitted.

The structure according to the invention makes it possible to possess materials and thicknesses that allow for both good operation and ease of manufacture of electronic devices to be formed in or on the semiconductor surface layer.

The layer 4 or layers 4 acts as a heat spreader and makes it possible to retain a layer or layers of low thermal conductivity adjacent to the bottom and having a relatively significant thickness, which reduces the temperature rise in the heat dissipating element. Makes it possible.

The insulating layer 5 may also be multiple layers of insulating material.

The advantages of the present invention from a thermal standpoint can be seen by the following example relative to the SOI structure. Localized temperature rises of 0.2 [mu] m diameter are presumed to approximate the temperature rises generated by advanced generation transistors. The resulting temperature rise was calculated by fixing the finish (silica) and thickness (0.1 μm and 0.3 μm, respectively) of the materials of layers 5 and 6 and changing the type and thickness of layer 4. To do this, a very simple model was used that made the structure similar to a hemispheric structure. The addition of a dispersion layer 4 of moderate thickness (approximately the order of the dimensions of the electronic device) made of various materials which are different but nevertheless always have a large thermal conductivity relative to the thermal conductivity of silica, is a single silica of 0.1 μm thickness It should be noted that very quickly the temperature rise corresponding to the presence of layer 5 can be approached.

From the point of view of the rapidity of the electronic device, it is advantageous to select an insulating material for the layer 4, and if possible an insulating material of low dielectric constant is advantageous. This makes it possible to substantially reduce dielectric capacitances and losses.

Now, a first method of manufacturing a semiconductor structure according to the present invention is described with reference to FIGS. 2A-2D.

FIG. 2A shows, on one side, a first substrate 10 made of, for example, silicon or SiC, with a layer 15 of insulating material having an electrical interface characteristic that is considered sufficiently good with the substrate 10. Preferably, the layer 15 is a silica layer obtained by thermal oxidation. Afterwards, a layer 14 having sufficient thermal conductivity is deposited on layer 15. Among the materials that can be used, polycrystalline silicon deposited by LPCVD, diamond deposited by PECVD, alumina deposited by reactive cathode sputtering from an aluminum target, silicon nitride deposited by CVD, aluminum nitride, Mention may be made of boron nitride and silicon carbide deposited by CVD. Except where the layer 14 allows direct bonding with the second substrate 11, an insulating layer 16 ′ which also facilitates bonding on the layer 14 is preferably deposited, for example by CVD. It is possible for the silica layer to be deposited.

The silicon substrate 10 has a layer 17 of micro-cavities arranged parallel to the substrate plane on which the insulating layers 15, 14 and 16 ′ have been obtained. This layer of micro-cavities defines the range of layer 12 to be the semiconductor surface layer of the structure in substrate 10. Micro cavities are obtained by hydrogen ion implantation under the conditions described in patent FR-A-2 681 472 to separate into two parts of the substrate 10 along the crack surface during the subsequent thermal treatment. The ion implantation process may be performed before or after the insulating layers 15, 14 and 16 ′ are obtained or may be performed between the deposition of one of these layers and the deposition of another layer.

Figure 2b shows a second substrate 11 of silicon, for example, on which a bonding layer 16 "is fabricated on one side, serving as a support substrate. This bonding layer is preferably a silica layer made by thermal oxidation. This bonding layer 16 "is only necessary if the properties of the substrate 11 do not allow direct bonding with the layer 16 '.

2C shows bonding the two substrates by molecular adhesion, by contacting the prepared free surfaces of the bonding layers 16 'and 16 ".

Subsequent appropriate thermal treatment (see patent FR-A-2 681 472) may separate the substrate 10 into two parts along the layer 17 of micro-cavities. Thus, the structure shown in FIG. 2D is obtained, which is an SOI structure comprising a surface layer 12 of silicon separated by a support substrate 11 and an intermediate region 13. The region 13 is formed of an electrical interface layer 15, a layer 14 of sufficient thermal conductivity and a multilayer 16 (formed by layers 16 'and 16 ") that provides good adhesion to the substrate 11. Include.

Thereafter, the free surface of the surface layer 12 can be adjusted in state by polishing and cleaning.

Now, a second method of manufacturing a semiconductor structure according to the present invention is described in connection with FIGS. 3A and 3B.

FIG. 3A shows a first substrate 20 of, for example, silicon, for example, having a good thermal conductivity material formed on one side thereof, for example by epitaxy, to obtain a corresponding layer 24. The epitaxially grown material may be cubic silicon carbide made according to known techniques. Thereafter, an insulating layer 26 of, for example, a silica layer is deposited on this layer 24.

As before, the silicon substrate 20 has a layer 27 of micro-cavities arranged parallel to the surface of the substrate on which the insulating layers 24 and 26 are deposited. This layer of micro-cavities defines the range of layer 12 within the substrate 20 to be the semiconductor surface layer of the SOI structure. As before, the layer of micro cavities 27 is formed under the conditions described in patent FR-A-2 681 472.

A second substrate 21 of silicon, for example, serving as a supporting substrate is prepared.

Thereafter, the free surface of layer 26 (see FIG. 3A) is spaced in contact with the free surface of substrate 21 so that the two substrates are bonded by molecular adhesion. The result obtained is shown in Figure 3b.

Subsequent suitable thermal treatment can separate the substrate 20 into two parts along the layer 27 of micro-cavities.

In this embodiment, it is advantageous to perform an ion implantation step after epitaxy of insulating layer 24. In fact, the ion implantation of hydrogen into silicon carbide (when this material is used) makes the latter completely insulating. This gives us the essential characteristics of the SOI structure.

In this embodiment, it should also be noted that there is no specific layer for obtaining an electrical interface with the silicon surface layer. In fact, because the layer 24 of good thermal conductivity is obtained by epitaxy, the interface with the semiconductor surface layer a priori has satisfactory electrical properties.

The present invention can be used to fabricate thin film semiconductor structures used to fabricate electronic devices.

Claims (22)

A semiconductor surface layer (2, 12, 22) separated from the support substrate (1, 11, 21) by an intermediate region (3, 13, 33), the intermediate region (3, 13, 33) being the support substrate A multilayer that electrically insulates the semiconductor surface layer from and provides electrical interface properties with the semiconductor surface layer, and thermal conductivity between the semiconductor surface layer (2, 12, 22) and the support substrate (1, 11, 21). It includes a first layer to provide, The intermediate region includes an additional second layer located between the first layer and the support substrate, the second layer being formed of a low dielectric constant electrically insulating material, and a molecule between the intermediate region and the support substrate. Thin film semiconductor structure, wherein the thickness of the first layer is selected as a function of the dimensions of the heat dissipation regions of the electronic device or elements to be made from the semiconductor surface layer. delete The thin film semiconductor structure of claim 1, wherein the second layer provides adhesion between the intermediate region and the support substrate. 2. The intermediate region (3, 13) according to claim 1, wherein the intermediate region (3, 13) comprises a third layer (5, 15) electrically insulated between the first layer and the semiconductor surface layer (2, 12). And the layer provides the electrical interface property to the intermediate region. 5. The thin film semiconductor structure according to claim 4, wherein the semiconductor structure is an SOI structure, and the third layer (5, 15) is a layer of silicon oxide. 6. The thin film semiconductor structure according to claim 5, wherein said third layer (5, 15) is a layer of thermal silicon oxide. The thin film semiconductor structure according to any one of claims 1 to 6, wherein the semiconductor structure is an SOI structure, and the second layers (6, 16) are layers of silicon oxide. The method according to any one of claims 1 to 6, wherein the first layers 4, 14 are made of one material selected from polycrystalline silicon, diamond, alumina, silicon nitride, aluminum nitride, boron nitride, and silicon carbide. Thin film semiconductor structure, characterized in that. 2. The thin film semiconductor structure of claim 1 wherein said first layer (24) is in contact with a semiconductor surface layer (22) and provides said electrical interface characteristics. 10. The thin film semiconductor structure of claim 9 wherein said semiconductor structure is an SOI structure and said first layer (24) is cubic silicon carbide. delete In the method of manufacturing a semiconductor structure according to claim 1, Fabricating layers of intermediate regions on one side of the first substrate intended to provide the semiconductor surface layer and / or on one side of the second substrate intended to provide the support substrate of the structure, Bonding the first substrate onto the second substrate such that the surfaces face each other, and Forming the semiconductor surface layer. 13. The method of claim 12, wherein forming the semiconductor surface layer comprises reducing the thickness of the first substrate. The method of manufacturing a semiconductor structure according to claim 12 or 13, wherein the bonding of the first substrate on the second substrate is obtained by molecular adhesion. 15. The method of claim 14, wherein fabricating the layers of the intermediate region comprises depositing at least one bonding layer that allows bonding by molecular adhesion. 16. The method of claim 15, wherein the bonding layer is a silicon oxide layer. 17. The method of claim 12, 13, 15, or 16, wherein the first layer is deposited by polycrystalline silicon deposited by LPCVD, diamond deposited by PECVD, by reactive cathode sputtering. A layer of a material selected from alumina, silicon nitride deposited by CVD, aluminum nitride deposited by CVD, boron nitride deposited by CVD, and silicon carbide deposited by CVD. Way. The method according to any one of claims 13, 15, or 16, wherein the thickness reduction of the first substrate (10) is thermally along the cleaved surface induced by rectification, chemical etching, polishing, ion implantation. A method for producing a semiconductor structure, characterized in that it is obtained using any one or more techniques of separation involving processing. 8. The thin film semiconductor structure according to claim 7, wherein the first layer (4, 14) is made of one material selected from polycrystalline silicon, diamond, alumina, silicon nitride, aluminum nitride, boron nitride, and silicon carbide. 15. The method of claim 14, wherein the first layer comprises polycrystalline silicon deposited by LPCVD, diamond deposited by PECVD, alumina deposited by reactive cathode sputtering, silicon nitride deposited by CVD, aluminum deposited by CVD. A layer of a material selected from nitride, boron nitride deposited by CVD, and silicon carbide deposited by CVD. 15. The method of claim 14, wherein the thickness reduction of the first substrate 10 is carried out using one or more techniques of separation involving thermal treatment along the cleavage surface induced by rectification, chemical etching, polishing, and ion implantation. Obtained, The semiconductor structure manufacturing method characterized by the above-mentioned. 18. The method of claim 17, wherein the reduction in thickness of the first substrate 10 is achieved using any one or more of the following techniques: separation involving thermal treatment along the cleaved surface induced by rectification, chemical etching, polishing, and ion implantation. Obtained, The semiconductor structure manufacturing method characterized by the above-mentioned.

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