KR100661216B1 - Manufacturing Method of Flash Memory Device - Google Patents

Abstract

The present invention relates to a method of manufacturing a flash memory device, and to a method of manufacturing a flash memory device having a gate structure capable of improving the electrical characteristics of the flash memory device.

According to the present invention, in the process of manufacturing a flash memory device, a gate pattern having a symmetrical shape is formed in one gate pattern as a first conductive layer, and the second conductive layer is stacked and separated, thereby separating two split gate regions. It is possible to prevent the occurrence of stringers in the space of the circuit and improve the electrical characteristics of the flash memory device.

Description

Fabrication method for flash memory device

1A to 1E are flowcharts illustrating a method of manufacturing a flash memory device having a conventional split gate cell structure.

2A to 2G are cross-sectional views illustrating a method of manufacturing a split gate type flash memory device according to the present invention.

Figure 3 is a SEM photograph showing a split gate manufactured by a flash memory device manufacturing method according to the present invention.

<Description of Signs of Major Parts of Drawings>

200 semiconductor substrate 201 gate insulating film

203: First gate pattern 203a, 203b: First and second floating gate electrodes

209: ONO layer 213: second conductive layer

213a and 213b: first and second control gate electrodes

217: interlayer insulating film 220: photoresist

The present invention relates to a method of manufacturing a flash memory device, and to a method of manufacturing a flash memory device having a gate structure capable of improving the electrical characteristics of the flash memory device.

The flash memory device is a nonvolatile memory device capable of high-speed electrical erasing while being mounted on a circuit board as well as maintaining information stored in the memory cell even when power is not supplied. Flash memory technology has continued to evolve while improving the cell structure in various forms. Such various cell types include structures such as a stacked gate cell and a split gate cell.

1A to 1E are flowcharts illustrating a method of manufacturing a flash memory device having a conventional split gate cell structure.

First, as shown in FIG. 1A, a gate insulating film 101, a first conductive layer, and an oxide-nitride-oxide (ONO) layer 109 are sequentially stacked on the semiconductor substrate 100. Thereafter, the ONO layer 109 and the first conductive layer are selectively patterned to form a first gate pattern 103. Subsequently, the semiconductor substrate 100 is heat-treated to grow a thermal oxide film 105 on left and right sidewalls of the first gate pattern 103.

As shown in FIG. 1B, a second conductive layer is stacked on the entire surface of the substrate including the first gate pattern 103.

Subsequently, as illustrated in FIG. 1C, the second conductive layer is selectively patterned so as to remain only on the top and one side of the first gate pattern 103. Accordingly, the second gate pattern 113 is formed on one side of the first gate pattern 103 to form a split gate including the first gate pattern 103 and the second gate pattern 113. .

Next, a thermal oxide film (not shown) is formed on the surface of the second gate pattern 113. Subsequently, low concentration impurity ions are implanted into the entire surface of the substrate to form a low concentration impurity ion region n− for the LDD structure in the substrate.

Subsequently, as shown in FIG. 1D, when the spacer 115 is formed on the sidewall of the second gate pattern 113 and a high concentration of impurity ions are implanted to form the source / drain, the gate electrode of the flash memory device may be formed. have.

As described above, a split gate having a symmetrical shape is formed in the memory cell region by a conventional method of manufacturing a flash memory device, and a predetermined region on the substrate is formed when the second conductive layer is stacked to form the second gate pattern 113 of the split gate. Since the first gate pattern 103 and the ONO layer 109 of the oxide film-nitride film-oxide film are stacked in advance, the gap between two split gate regions is increased due to the step difference caused by the oxide film, the nitride film, and the first gate pattern 103. Your space will have a recessed groove (G).

Accordingly, when the second gate pattern 113 is formed by patterning the second conductive layer, the second conductive layer existing in the space between the two split gate regions is compared with the second conductive layer on the split gate region. Incomplete etching is caused by the groove.

Specifically, during the selective dry etching of the second conductive layer, a polymer which is an etch byproduct is generated, and the polymer is accumulated on the side of the first gate pattern, so that the etching gas is sufficiently transferred to the space between the two split gate regions. Incomplete etching occurs.

As a result of this incomplete etching, a stringer 113a, a etched residue of the second conductive layer, is generated in the space between the two split gate regions.

Meanwhile, as shown in FIG. 1E, the space between the two split gate regions is a portion where a contact hole h is formed to be connected to the upper wiring through a subsequent process, and thus a stringer is formed at the portion where the contact hole is formed. As (X) occurs, the electrical characteristics such as deterioration of the contact resistance are caused.

In the process of manufacturing a flash memory device, a space between two split gate regions is formed by forming a gate having a symmetrical shape as one gate pattern as a first conductive layer, and stacking and separating a second conductive layer. An object of the present invention is to provide a method of manufacturing a flash memory device capable of preventing occurrence of stringers and improving electrical characteristics of the flash memory device.

In order to achieve the above object, a method of manufacturing a flash memory device according to the present invention comprises the steps of preparing a semiconductor substrate; Sequentially forming a gate insulating film, a first conductive layer, and an insulating film on an entire surface of the semiconductor substrate; Selectively patterning the first conductive layer and the insulating film to form a first gate pattern including first and second floating gate regions; Stacking a second conductive layer on the entire surface of the first gate pattern and the insulating layer; Forming a photoresist layer exposing between the first and second floating gate regions on the second conductive layer; Etching the second conductive layer using the photoresist layer as a mask to form first and second control gate electrodes; Etching the insulating film exposed by the etched second conductive layer; And etching the first gate pattern exposed by the etched second conductive layer and the insulating layer to form first and second floating gate electrodes.

After the forming of the first and second floating gate electrodes, the method may further include implanting impurity ions into the semiconductor substrate.

The method may further include forming an interlayer insulating layer on the first and second control gate electrodes, and forming a contact hole between the first and second control gate electrodes.

And forming spacers on opposite sides of the first and second floating gate electrodes and the first and second control gate electrodes.

The insulating film is formed of an oxide film-nitride film-oxide film.

Forming the first and second control gate electrodes by etching the second conductive layer, the second conductive layer is a plasma etching equipment, the pressure condition is 2 ~ 8 mT, source power is 200 ~ 800W, bottom power is 10 ~ 60W, the etching gas is used for CF ₄ of 10 ~ 80sccm, the etching time is the first step and the etching proceeds to 20 ~ 60sec; The second conductive layer is a plasma etching equipment, the pressure conditions are 2 ~ 8 mT, source power is 300 ~ 600W, bottom power is 50 ~ 100W, etching gas is 50 ~ 100sccm CL ₂ gas, 100 ~ 200sccm HBr gas, A second step of etching with HeO ₂ gas of 5˜20 sccm; The second conductive layer is a plasma etching equipment in the pressure conditions 10-30 mT, source power 200-400W, bias power 50-100W, etching gas 50-100sccm CL ₂ gas, 100-200sccm HBr gas, 5 to 20 sccm HeO ₂ gas is characterized in that it comprises a three step of the etching proceeds.

The etching of the insulating layer exposed by the etched second conductive layer may include etching the insulating layer in a plasma etching apparatus with a pressure condition of 2 to 8 mT, a source power of 400 to 800 W, a bias power of 100 to 500 W, and an etching gas. The 50 to 150sccm CF ₄ characterized in that it comprises a step of the etching proceeds.

The first gate pattern may be etched to form first and second floating gate electrodes. The first gate pattern may include a pressure condition of 10 to 30 mT, a source power of 200 to 400 W, and a bias power of 50 in a plasma etching apparatus. ~ 100W, the etching gas is a step 1, the etching proceeds with 50 ~ 150sccm CL ₂ gas, 100 ~ 250sccm HBr gas, 10 ~ 70sccm HeO ₂ gas; The first gate pattern is etched with a pressure condition of 50 ~ 100 mT, source power of 500 ~ 800W, bias power of 50 ~ 100W, etching gas of 150 ~ 300sccm HBr, 10 ~ 30sccm HeO ₂ in the plasma etching equipment Characterized in that it comprises two steps to proceed.

The first gate pattern may be etched with a silicon oxide film at a high selectivity.

Hereinafter, a method of manufacturing a split gate type flash memory device according to the present invention will be described in detail with reference to the accompanying drawings.

2A to 2G are cross-sectional views illustrating a method of manufacturing a split gate type flash memory device according to the present invention.

First, as illustrated in FIG. 2A, an isolation process, for example, a shallow trench isolation (STI) process, is used to define an active region of a semiconductor substrate 200 made of a material such as single crystal silicon. An isolation layer (not shown) is formed in the field region of the semiconductor substrate 200. Thereafter, a gate insulating film 201 is formed on the entire surface of the substrate 200.

The gate insulating film 201 is formed by growing at about 700 ° C. by thermal oxidation in a furnace equipment.

Subsequently, a first conductive layer and an ONO layer 209 are sequentially stacked on the gate insulating film 201. Here, the first conductive layer may be formed of a polysilicon layer having a thickness of about 2000˜2500 μs, and the ONO layer 209 may be an oxide-nitride layer having a thickness of about 500˜1000 μm. It can be formed into an oxide structure.

In this state, a photoresist film is coated on the insulating film, and then a photoresist pattern (not shown) defining a region of the first gate pattern 203 is formed using a conventional photolithography process. Next, the first gate pattern 203 is formed by sequentially etching and removing the exposed gate insulating film 201 and the first conductive layer using the photoresist pattern as an etching mask.

Here, the first gate pattern 203 is integrally formed by connecting the first floating gate 203a and the second floating gate 203b.

In the state where the first gate pattern 203 is formed, the thermal oxide film 205 is grown on the left and right sidewalls of the first gate pattern 103 by heat treatment of the semiconductor substrate 200.

In this state, the second conductive layer 213 for forming the second gate pattern 213 on the entire surface of the semiconductor substrate 200 including the first gate pattern 203 may be formed by low pressure chemical vapor deposition (LPCVD). Chemical Vapor Deposition) Laminate to about 2500 ~ 3000Å thickness.

In this case, since the step is not formed on the first gate pattern 203, no groove is formed on the first gate pattern 203.

Subsequently, as shown in FIG. 2B, a photoresist layer 220 is formed on the second conductive layer 213, and the photoresist layer 220 has a second conductivity on the first gate pattern 203. A portion of the layer is exposed.

2C to 2E, the photoresist layer 220 may etch the second conductive layer 213 to form a first etching hole h1 and to form second gate patterns 213a and 213b. ), And subsequently, the second etching hole h2 and the third etching hole h3 are formed, and the ONO layer 209 and the first gate pattern 203 are split to form a first floating gate electrode 203a. ), A pattern that can be formed by the second floating gate electrode 203b is formed.

In this case, the width of the first etching hole (h1) and the second etching hole (h2) is about 4000 ~ 7000Å.

Accordingly, when the second conductive layer 213 is etched, the etching gas is sufficiently transferred to the space between the two first and second floating gate electrodes 203a and 203b to prevent the occurrence of a stringer in the corresponding region. It becomes possible.

The etching process of the second conductive layer 213, the ONO layer 209, and the first gate pattern 203 is performed in a plasma etching chamber, and the second conductive layer 213, the ONO layer 209, and the like. In order to etch the first gate pattern 203 in the same plasma etching chamber, the first gate pattern 203 is etched under different conditions over six steps.

In the plasma etching chamber, the etching gas is ionized into the plasma at low pressure to provide an etching atmosphere, and the etching gas is formed by the source power and the bottom power applied to the semiconductor substrate. ), The ONO layer 209 and the first gate pattern 203 are etched.

First, as a first step, the second conductive layer 213 exposed by the photoresist layer 220 is a BT (break through) process, the pressure condition is 2 ~ 8 mT, the source power is 200 ~ 800W, bottom power Silver 10 ~ 60W, etching gas is used CF ₄ of 10 ~ 80sccm, the etching time is 20 ~ 60sec.

In this case, the polysilicon, the second conductive layer 213, is brake-trouted for a short time to prepare a main etching thereafter.

As a second step, as the main etching process after the BT process, the pressure conditions are 2 ~ 8 mT, source power 300 ~ 600W, bottom power 50 ~ 100W, etching gas 50 ~ 100sccm CL ₂ gas, 100 ~ 200sccm The HBr gas of 5 ~ 20sccm HeO ₂ gas is used and the second conductive layer polysilicon is etched.

Thereafter, as a third step, the second conductive layer 213 is etched by the main etch and the etching is stopped using the etching selectivity of the polysilicon and the ONO layer 209 under the second conductive layer 213. Perform the process of finding (End Point).

At this time, the pressure conditions of the plasma etching process is 10 ~ 30 mT, source power is 200 ~ 400W, bias power is 50 ~ 100W, etching gas is 50 ~ 100sccm CL ₂ gas, 100 ~ 200sccm HBr gas, 5 ~ 20sccm HeO ₂ gas is used to etch the polysilicon, which is the second conductive layer.

Accordingly, the second conductive layer 213 may be etched, and an end poing may be detected and then overetched for a predetermined time, thereby replacing the BT process of the ONO layer 209.

In the etching process of the second conductive layer 209 formed in the first to third steps, the first and second control gate electrodes 203a and 203b having vertical profiles may be formed by etching under different conditions according to each step. Can be.

In the fourth step, as the main etching process of the ONO layer 209, a pressure condition of 2 to 8 mT, a source power of 400 to 800 W, a bias power of 100 to 500 W, and an etching gas of CF ₄ of 50 to 150 sccm is used. . In this case, the etching may be over-etched for a predetermined time, thereby replacing the BT process of the first gate pattern.

In the fifth step, the CL ₂ gas having a pressure condition of 10 to 30 mT, a source power of 200 to 400 W, a bias power of 50 to 100 W, and an etching gas of 50 to 150 sccm in the plasma etching process of etching the first gate pattern 203. , 100-250sccm of HBr gas and 10-70sccm of HeO ₂ gas are used to etch polysilicon which is the first gate pattern.

In the sixth step, plasma etching is performed using a high selectivity ratio (about 1: 2000) between the first gate pattern 203 and the silicon oxide film, which is the gate insulating film 201. 100 mT, source power 500-800 W, bias power 50-100 W, etching gas 150-300 sccm HBr, 10-30 sccm HeO ₂ is used.

In this case, the first gate pattern 203 is completely separated into a first floating gate electrode 203a and a second floating gate electrode 203b, and the first floating gate electrode 203a and the second floating gate electrode 203b are separated. Overetch for a predetermined time so that no residual polysilicon remains between At this time, the plasma etching process of step 6 uses a high selectivity ratio of polysilicon and silicon oxide film, and thus does not cause film damage during overetching.

Accordingly, the first floating gate electrode 203a and the second floating gate electrode 203b and the first and second floating gate electrodes 203a and 203b which are spaced apart from each other by a predetermined distance, respectively, A split gate consisting of two control gate electrodes 213a and 213b is completed.

A distance between the first floating gate electrode 203a and the second floating gate electrode 203b is about 4000 to 7000 Å.

Thereafter, the photoresist layer 220 is removed.

In this state, as shown in FIG. 2F, low concentration impurity ions are implanted onto the entire surface of the substrate 201 so that the low concentration impurity ion regions n − for the LDD structure are formed inside the semiconductor substrate 200 on the left and right sides of the split gate. To form. Subsequently, a spacer 215 is formed on the entire surface of the semiconductor substrate 200 including the split gate including the first and second floating gate electrodes 203a and 203b, the ONO layer 209, and the first and second control gate electrodes 213a and 213b. ) And an oxide film and a nitride film are sequentially stacked and then anisotropically etched to form spacers 212 on left and right sidewalls of the split gate. In the state where the spacer 212 is formed, a high concentration impurity ion implantation process for forming a source / drain is performed on the entire surface of the semiconductor substrate 200.

Thereafter, as shown in FIG. 2G, an interlayer insulating film 217 is stacked on the entire surface of the semiconductor substrate 200 including the split gate, and the substrate 200 in the space between the two split gate regions is exposed. The conventional method of manufacturing a semiconductor device, such as selectively etching the interlayer insulating film 217 to form a contact hole h4, is completed.

3 is a SEM photograph showing a split gate manufactured by a method of manufacturing a flash memory device according to the present invention.

As shown in FIG. 3, a defect such as a stringer does not occur in a space between two split gate regions, which are portions of the contact hole, to improve contact resistance and prevent defects. .

As mentioned above, the present invention has been described in detail through specific embodiments, which are intended to specifically describe the present invention, and a method of manufacturing a flash memory device according to the present invention is not limited thereto. It is apparent that modifications and improvements are possible by those skilled in the art.

The present invention improves yield by preventing defects such as stringers in a space between two split gate regions when manufacturing a flash memory semiconductor device, and improves contact resistance when forming a contact hole in the split gate region. This has the effect of improving the reliability and device characteristics of the product.

Claims (9)

Preparing a semiconductor substrate; Sequentially forming a gate insulating film, a first conductive layer, and an insulating film on an entire surface of the semiconductor substrate; Selectively patterning the first conductive layer and the insulating layer to form a first gate pattern including first and second floating gate regions; Stacking a second conductive layer on the entire surface of the first gate pattern and the insulating layer; Forming a photoresist layer exposing between the first and second floating gate regions on the second conductive layer; Etching the second conductive layer using the photoresist layer as a mask to form first and second control gate electrodes; Etching the insulating film exposed by the etched second conductive layer; And etching the first gate pattern exposed by the etched second conductive layer and the insulating layer to form first and second floating gate electrodes. The method of claim 1, And after implanting the first and second floating gate electrodes, implanting impurity ions into the semiconductor substrate. The method of claim 1, And forming an interlayer insulating film on the first and second control gate electrodes, and forming a contact hole between the first and second control gate electrodes. The method of claim 1, And forming a spacer on opposite sides of the first and second floating gate electrodes and the first and second control gate electrodes. The method of claim 1, And the insulating film is formed of an oxide film-nitride film-oxide film. The method of claim 1, Etching the second conductive layer to form first and second control gate electrodes, The second conductive layer is a plasma etching equipment using a pressure condition of 2 ~ 8 mT, source power 200 ~ 800W, bottom power 10 ~ 60W, etching gas 10 ~ 80sccm CF ₄ , the etching time is 20 ~ A first step of etching in 60sec; The second conductive layer is a plasma etching equipment, the pressure conditions are 2 ~ 8 mT, source power is 300 ~ 600W, bottom power is 50 ~ 100W, etching gas is 50 ~ 100sccm CL ₂ gas, 100 ~ 200sccm HBr gas, A second step of etching with HeO ₂ gas of 5˜20 sccm; The second conductive layer is a plasma etching equipment in the pressure conditions 10-30 mT, source power 200-400W, bias power 50-100W, etching gas 50-100sccm CL ₂ gas, 100-200sccm HBr gas, A method of manufacturing a flash memory device comprising the three steps of etching with HeO ₂ gas of 5 ~ 20sccm. The method of claim 1, Etching the insulating film exposed by the etched second conductive layer, Wherein the insulating film is plasma etching equipment, pressure conditions are 2 ~ 8 mT, source power is 400 ~ 800W, bias power is 100 ~ 500W, etching gas 50 ~ 150sccm characterized in that it comprises the step of etching to CF ₄ A method of manufacturing a flash memory device. The method of claim 1, Etching the first gate pattern to form first and second floating gate electrodes, The first gate pattern is a plasma etching equipment, the pressure condition is 10 ~ 30 mT, the source power is 200 ~ 400W, the bias power is 50 ~ 100W, the etching gas is 50 ~ 150sccm CL ₂ gas, 100 ~ 250sccm HBr gas, A first step of etching with HeO ₂ gas of 10˜70 sccm; The first gate pattern is etched with a pressure condition of 50 ~ 100 mT, source power of 500 ~ 800W, bias power of 50 ~ 100W, etching gas of 150 ~ 300sccm HBr, 10 ~ 30sccm HeO ₂ in the plasma etching equipment Method of manufacturing a flash memory device comprising the two steps to proceed. The method of claim 8, And the first gate pattern is etched with a silicon oxide film at a high selectivity ratio.

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