KR100660541B1 - Erasing Nonvolatile Memory Device with Shorter Erasing Time - Google Patents

Abstract

A method of erasing a nonvolatile memory device including a memory cell array composed of sectors arranged in rows and columns is provided. An erase method according to the present invention comprises the steps of: simultaneously erasing memory cells of the sectors; Simultaneously selecting a word line of each sector belonging to the same row in a post-program operation; And post-programming erased memory cells of the simultaneously selected word lines.

Description

Non-volatile memory device erasing method that can reduce the erase time {NON-VOLATILE MEMORY DEVICE CAPABLE OF REDUCING ERASE TIME AND ERASE METHOD THEREOF}

1 is a block diagram schematically showing a nonvolatile memory device according to the present invention;

FIG. 2 is a diagram showing the structure of the memory cell array shown in FIG. 1;

3 is a block diagram schematically showing some of the sectors of the banks of FIG. 1 belonging to the same mat; And

4 is a flowchart illustrating an erase procedure of a nonvolatile memory device according to the present invention.

Explanation of symbols on the main parts of the drawings

100: memory cell array 110: memory cell array

120: column selection circuit 130: write driver circuit

140: control logic 150: bit line voltage generation circuit

160: word line voltage generating circuit 170: address generating circuit

180: bank selection circuit 190: matte selection circuit

200: global word line selection circuit 210: local word line selection circuit

220: decoder circuit 230: sector selection circuit

The present invention relates to a semiconductor memory device, and more particularly to a method of erasing a nonvolatile memory device.

A flash memory device is a kind of EEPROM in which a plurality of memory areas are erased or programmed in one program operation. A typical EEPROM allows only one memory area to be erased or programmable at a time, which allows the flash memory device to operate at a faster and more efficient speed when systems using the flash memory device read and write to other memory areas at the same time. It means that there is. All forms of flash memory and EEPROM are worn out after a certain number of erase operations due to the wear of the insulating film surrounding the charge storage means used to store the data.

Flash memory devices store information on the silicon chip in a manner that does not require a power source to maintain the information stored on the silicon chip. This means that if the power to the chip is interrupted, the information is maintained without consuming power. In addition, flash memory devices provide physical shock resistance and fast read access times. Because of these features, flash memory devices are commonly used as storage devices for devices powered by batteries. There are two types of flash memory devices, NOR flash memory devices and NAND flash memory devices, depending on the type of logic gate used for each storage element.

Flash memory devices store information in an array of transistors called cells, with each cell storing one-bit information. Newer flash memory devices, called multi-level cell devices, can store more than one bit per cell by varying the amount of charge placed on the floating gate of the cell.

In a NOR flash memory device, each cell is similar to a standard MOSFET transistor except that it has two gates. The first gate is a control gate (CG) as in other MOS transistors, but the second gate is an insulated floating gate (FG) surrounded by an insulating film. The floating gate is between the control gate and the substrate (or bulk). Since the floating gate is insulated by the insulating film, electrons placed in the floating gate are trapped and thus store information. When the electrons lie at the floating gate, the electric field from the control gate is changed (partially canceled) by the electrons, which causes the cell's threshold voltage (Vt) to change. Thus, when a cell is read by applying a specific voltage to the control gate, current may or may not flow depending on the threshold voltage of the cell. This is controlled by the amount of charge in the floating gate. The presence or absence of a current is detected and interpreted as 1 or 0, so the stored data is reproduced. In multi-level cell devices that store more than 1-bit per cell, the amount of current flowing rather than the presence or absence of current will be sensed to determine the amount of electrons stored in the floating gate.

The NOR flash cell is programmed (set to a specific data value) by applying a program voltage on the control gate and a high voltage of 5-6V to the drain with the source grounded. According to this bias condition, a large amount of cell current flows from the drain to the source. This programming approach is called hot-electron injection. A large voltage difference is applied between the control gate and the substrate (or bulk) to erase the NOR flash cell, which causes electrons to escape from the floating gate through F-N tunneling. The components of a NOR flash memory device are divided into erase segments, commonly referred to as blocks or sectors. All memory cells in a sector are erased at the same time. NOR programming, however, may be performed in bytes or words.

The erase procedure of the NOR flash memory device is largely composed of a pre-program interval, a main erase interval, and a post-program interval. The pre-program operation is performed using the same bias condition as the normal program operation in order to prevent the occurrence of over erased memory cells during the next main erase. At this time, all of the memory cells to be erased are pre-programmed. Then, a main erase operation is performed so that all memory cells in the sector have an on-cell state. When the main erase operation starts, all memory cells in the sector are erased simultaneously. Finally, in order to heal excessively erased memory cells in the main erase period, a post-program operation is performed. The post-program operation is performed the same as the pre-program operation except for the bias condition. That is, memory cells connected to each word line (or row) are post / soft-programmed in byte or word units.

As mentioned above, NOR programming is performed in bytes or words. For that reason, a disadvantage of the NOR flash memory device using the erase procedure described above is that the time taken to perform pre-program and post-program operations takes up a significant portion of the total time required for the erase procedure.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of erasing a nonvolatile memory device capable of shortening an erase time.

According to one aspect of the present invention for achieving the above objects, there is provided an erase method of a nonvolatile memory device including a memory cell array consisting of sectors arranged in rows and columns. An erase method according to the present invention comprises the steps of: simultaneously erasing memory cells of the sectors; Simultaneously selecting a word line of each sector belonging to the same row in a post-program operation; And post-programming erased memory cells of the simultaneously selected word lines.

In this embodiment, the verify operation on the programmed memory cells is not performed during the post-program operation.

In this embodiment, erased memory cells of the simultaneously selected word lines are programmed in predetermined column units.

In this embodiment, the method further includes repeating the selection and program steps until all the memory cells of the memory cell array are programmed.

In this embodiment, the method further includes pre-programming the memory cells of each sector to be in an off state before the erase step.

In this embodiment, the verify operation on the programmed memory cells is not performed in the pre-program step.

Exemplary embodiments of the invention will be described in detail below on the basis of reference drawings.

1 is a block diagram schematically illustrating a nonvolatile memory device according to the present invention. The nonvolatile memory device according to the present invention is a NOR flash memory device. However, it will be apparent to those skilled in the art that the present invention can be applied to other memory devices (eg, MROM, PROM, FRAM, NAND type flash memory devices, etc.).

Referring to FIG. 1, a nonvolatile memory device 100 according to the present invention includes a memory cell array 110 that stores N-bit data information (N = 1 or larger integer). As shown in FIG. 2, the memory cell array 110 includes a plurality of banks BANKm (m = 0-15), and each of the banks BANKm includes a plurality of sectors SECTORm. do. Although not shown in the figure, each sector includes memory cells arranged in rows and columns. As mentioned above, memory cells belonging to one sector are erased simultaneously. The column selection circuit 120 operates in response to the control signal ACC_POST_PGM from the control logic 140, and operates the columns of sectors belonging to the selected bank (s) in preset units (for example, byte or word units). Configured to select. The control signal ACC_POST_PGM is activated during the post-program period of the erase procedure. When the control signal ACC_POST_PGM is activated, the column selection circuit 120 selects columns of each of the banks BANKm in preset units. When the control signal ACC_POST_PGM is deactivated, the column selection circuit 120 selects any one column of the banks BANKm in a predetermined unit. The selected columns are driven by the write driver circuit 130 to the bit line voltage from the bit line voltage generation circuit 150 during the pre / post-program period.

The control logic 140 is configured to control the overall operation of the memory device. The control logic 140 activates the control signal ACC_POST_PGM during the post-program period. The bit line voltage generation circuit 150 generates the bit line voltage according to the control of the control logic 140. The bit line voltage generation circuit 150 may be configured to generate the bit line voltage using an externally supplied voltage during the post-program period. Alternatively, during the post-program period, the bit line voltage may be supplied externally. The word line voltage generation circuit 160 generates a word line voltage under the control of the control logic 140. The word line voltage generation circuit 160 may be configured to generate a word line voltage using an externally supplied voltage during the post-program period. Alternatively, during the post-program period, the word line voltage may be supplied externally.

The address generation circuit 170 is controlled by the control logic 140 and generates a row address. The row address includes address information RA1 (hereinafter referred to as first row address) for selecting a bank, address information RA2 (hereinafter referred to as second row address) for selecting a mat, and a global word line. Address information RA3 for selecting (hereinafter referred to as a third row address), and address information RA4 (hereinafter referred to as a fourth row address) for selecting a local word line. In this embodiment, as shown in FIG. 2, the memory cell array 110 will consist of 16 banks, each bank consisting of 16 sectors. Each sector will be arranged with 64 global word lines and 512 word lines (or local word lines). The memory device of the present invention has a hierarchical word line structure in which one global word line corresponds to eight word lines. All sectors also constitute a plurality of mats. However, the structure of the memory cell array according to the present invention is not limited thereto. Those skilled in the art will appreciate. The bank select circuit 180 is controlled by the control signal ACC_POST_PGM and generates bank select signals BS0-BS15 corresponding to the banks in response to the first row address RA1. For example, when the control signal ACC_POST_PGM is activated (or during the post-program period), the bank select circuit 180 generates all of the bank select signals BS0-BS15 regardless of the first row address RA1. Or in response to the first row address RA1, some of the bank selection signals BS0 -BS15 (eg, two bank selection signals) are activated.

The mat select circuit 190 generates mat select signals MATm respectively corresponding to the mats in response to the second row address RA2, and the sector select circuit 230 generates the bank select signals BSm and the mat. In response to the selection signals MATm, sector selection signals SSij (i denotes the number of mats and j denotes the number of banks) are generated. For example, when the control signal ACC_POST_PGM is activated, the sector select circuit 190 generates sector select signals SSij such that all sectors of each bank belonging to the same mat are selected. When the control signal ACC_POST_PGM is deactivated, the sector select circuit 190 generates sector select signals SSij such that only one sector is selected. The global word line select circuit 200 generates global word line select signals Mm_GWL0-Mm_GWL63 respectively corresponding to the mats in response to the third row address RA3. For example, the global word line select circuit 200 activates only one of the global word line select signals Mm_GWL0-Mm_GWL63 corresponding to any mat in response to the third row address RA3. The local word line select circuit 210 activates any one of the local word line select signals S0-S7 in response to the fourth row address RA4. The decoder circuit 220 generates word line select signals Bm_PWL0-Bm_PWL7 in response to the select signals S0-S7 and BSm. For example, when the bank select signal BS0 is activated, the decoder circuit 220 activates any one of the select signals B0_PWL0-B0_PWL7 according to the select signals S0-S7. When all of the bank select signals BS0-BS15 are activated (or when the control signal ACC_POST_PGM is activated), the decoder circuit 220 according to the select signals S0-S7 select signal corresponding to each bank. Activate either of these simultaneously. This means that the selection signals B0_PWL0, B1_PWL0, ..., B15_PWL0 respectively supplied to the sectors belonging to the same mat are activated at the same time.

3 is a block diagram illustrating a portion of the array shown in FIG. 1 in accordance with an exemplary embodiment of the present invention. 3, only two sectors belonging to different banks and arranged in the same row (or mat) are shown. The sector SECTOR0 belonging to the bank BANK0 includes a word line driving circuit having driving blocks DRV0-DRV63 respectively corresponding to the selection signals M0_GWL0-M0_GWL63. The sector SECTOR0 is selected by the sector select signal SS00. Select signals B0_PWL0-B0_PWL7 are commonly applied to the driving blocks DRV0-DRV63. When the selection signals SS00, M0_GWL0 and B0_PWL0 are activated, the driving block DRV0 drives the word line WL0 to the word line voltage V _WL . A sector SECTOR0 belonging to the bank BANK1 includes a word line driving circuit having driving blocks DRV0-DRV63 respectively corresponding to the selection signals M0_GWL0-M0_GWL63. The sector SECTOR0 is selected by the sector select signal SS01. Selection signals B1_PWL0-B1_PWL7 are commonly applied to the driving blocks DRV0-DRV63. When the selection signals SS01, M0_GWL0 and B1_PWL0 are activated, the driving block DRV0 drives the word line WL0 to the word line voltage V _WL .

4 is a flowchart illustrating an erase procedure of a nonvolatile memory device according to the present invention. An erase procedure of the nonvolatile memory device according to the present invention will be described in detail with reference to the accompanying drawings below. The erase procedure of the nonvolatile memory device according to the present invention is largely composed of a pre-program section, a main erase section, and a post-program section.

In the pre-program period, memory cells of each sector are pre-programmed under the same bias condition as in a normal program operation in order to prevent generation of memory cells that are excessively erased during the next main erase (S100). According to the pre-program operation of the present invention, in each sector, memory cells of the selected word line are pre-programmed in a predetermined unit (for example, byte or word unit) with one word line selected. When all memory cells of the selected word line are pre-programmed, the next word line is selected. By repeating this process, the memory cells of each sector are all pre-programmed. The verification operation is not performed in the pre-program section. That is, all memory cells in each sector are pre-programmed to have an off state without a program verify operation. Thereafter, the memory cells of all sectors are simultaneously erased in a well known manner so as to have an on state (S110). After the erase operation is completed, the post-program operation according to the present invention will be performed through the following procedure (S160).

In step S120, the control logic 140 activates the control signal ACC_POST_PGM for post-programming after the erase operation is finished, and the address generating circuit 160 generates a row address according to the control of the control logic 140. do. When the control signal ACC_POST_PGM is activated, the bank select circuit 180 activates all of the bank select signals BS0-BS15. As another example, when the control signal ACC_POST_PGM is activated, the bank select circuit 180 selects some (2 or more) banks of the bank select signals BS0-BS15 in response to the first row address RA1. Signals). When the control signal ACC_POST_PGM is activated, the mat select circuit 190 generates mat select signals MAT0-MAT15 in response to the second row address RA2, and the sector select circuit 230 inputs the input selection. Sector select signals (e.g., SS <0> <0> -SS <15> <0>) are simultaneously generated in response to the signals MATm, BSm. The global word line selection circuit 200 activates one of the selection signals (eg, M0_GWL0-M0_GWL63) (eg, M0_GWL0) corresponding to an arbitrary mat in response to the third row address RA3. The local word line select circuit 210 activates one of the select signals S0-S7 (eg, S0) in response to the fourth row address RA4. The decoder circuit 220 simultaneously activates the selection signals B0_PWL0-B15_PWL0 in response to the input signals S0-S7 and BS0-BS15. According to this condition, the word lines WL0 of the sectors SECTOR0 each arranged in the banks BANK0-BANK15 and belonging to the same mat are selected at the same time, and the word line voltage VWL is selected for the selected word lines WL0. ) Will be supplied (S130).

Thereafter, the column selection circuit 120 selects columns of selected sectors belonging to each of all banks in preset units in response to the activation of the control signal ACC_POST_PGM. The columns of the selected sector belonging to each of all banks are driven to the bit line voltage by the write driver circuit 130 under the control of the control logic 140. That is, during the post-program operation, memory cells connected to the word lines of the selected sectors are simultaneously post-programmed in predetermined units (S140). In a next step S150, it is determined whether all the cells of the memory cell array have been post-programmed. If all cells of the memory cell array have not been post-programmed, the procedure proceeds to step S130. Thereafter, the above-described steps S130-S150 are repeated until all the memory cells are post-programmed. If all cells of the memory cell array have been post-programmed, the erase procedure is terminated. As with pre-programming, all memory cells are post-programmed without a program verify operation.

In the above, the configuration and operation of the circuit according to the present invention has been shown in accordance with the above description and drawings, but this is only an example, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Of course.

As described above, the post-program time can be shortened by performing a post-program operation in a state in which a plurality of word lines of sectors belonging to the same row (or mat) are simultaneously selected. As a result, it is possible to reduce the erase time.

Claims (6)

A method of erasing a nonvolatile memory device comprising a memory cell array consisting of sectors arranged in rows and columns: Simultaneously erasing memory cells of the sectors; Simultaneously selecting a word line of each sector belonging to the same row in a post-program operation; And Post-programming erased memory cells of the simultaneously selected word lines. The method of claim 1, And wherein the verify operation is not performed on the programmed memory cells during the post-program operation. The method of claim 1, And erased memory cells of the simultaneously selected word lines are programmed in predetermined column units. The method of claim 1, And repeating the selection and program steps until all the memory cells of the memory cell array are programmed. The method of claim 1, And pre-programming memory cells of each sector to have an off state prior to the erasing step. The method of claim 5, And the verify operation is not performed on the programmed memory cells in the pre-program step.

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