KR100657148B1 - Flash memory and its reference cell control method - Google Patents

Abstract

The flash memory of the present invention includes a main flash cell array having two-dimensional sets of flash cells for writing bit data, and a reference cell array having a reference threshold voltage recorded therein for determining a value written in the main flash cell. A flash cell array unit; A word line decoder for selecting a word line of the main flash cell array according to a first address among addresses for indicating each flash cell; A bit line decoder for selecting a bit line of the main flash cell array according to a second address among addresses for indicating each flash cell; And a sense amplifier unit for amplifying a potential difference between the bit line of the main flash cell array selected according to the bit line decoder unit and the bit line of the reference cell array.

 Implementing a flash memory according to the spirit of the present invention has the effect of reducing the possibility of failure due to the process variation and the chip size can be reduced.

Flash Memory, Reference Cells, EEPROM, Wordline Decoder

Description

Flash memory and its reference cell control method {FLASH MEMORY AND REFERENCE CELL CONTROL MERTHOD OF IT}

1 is a block diagram showing the structure of a flash memory according to the prior art;

2 is a block diagram showing the structure of a flash memory according to an embodiment of the present invention;

3 is a diagram illustrating a flash cell voltage when data is erased when the present invention is applied to a flash memory of a substrate erase method;

4 is a diagram illustrating a flash cell voltage when data is erased when the present invention is applied to a flash memory of a source-gate erase method;

5 is a circuit diagram illustrating an embodiment of a reference word line decoder of the present invention;

FIG. 6 is a circuit diagram illustrating one embodiment of the wordline switch of FIG. 5. FIG.

* Explanation of symbols for the main parts of the drawings

110: word line decoder unit 120: flash cell array unit

122: main flash cell array 124: reference cell array

140: reference word line decoder unit 150: bit line decoder unit

160: sense amplifier unit

The present invention relates to a layout structure of a reference cell of a flash memory and a control method of the reference cell.

In the case of flash memory, data is recorded by the difference of the gate threshold voltage of the flash cell MOS transistor. The logic state is assigned to the minimum and maximum values of the gate threshold voltage of the MOS transistor of the main memory flash cell. The threshold voltage of one main memory flash cell is compared with the threshold voltage of a reference cell to determine a written logic value.

1 is a block diagram of a conventional flash memory. The illustrated flash memory includes the main flash cell array 20 according to a first flash cell array 20 in which flash cells for writing 1-bit data are formed two-dimensionally and an address for indicating each flash cell. A word line decoder unit 10 for selecting a word line of the memory cell and a bit line decoder unit for selecting a bit line of the main flash cell array 20 according to a second address among addresses for indicating each flash cell. 50) a reference cell array unit 30 including a reference cell having a reference threshold voltage written therein for determining a value written in the flash cell, and a word line of the reference cell array unit 30 according to the first address A reference word line decoder unit 40 for selecting a reference, a reference bit line decoder unit 70 for selecting a bit line of the reference cell array unit 30, And a sense amplifier unit 60 for amplifying the potential difference between the bit line of the main flash cell array selected by the bit line decoder unit 50 and the bit line of the reference cell array selected by the reference bit line decoder 70. It includes.

According to a read or varify operation, the bit line current of the flash cell selected by the word line decoder unit 10 and the bit line decoder unit 50 is input to the sense amplifier 60 on the main memory cell side. The reference cell word line decoder 40 selects the reference cell, and the reference cell bit line decoder 70 opens to input the bit line current of the reference cell to the sense amplifier 60. Each sense amplifier constituting the sense amplifier unit 60 compares the bit line current by the responsible flash cell with the bit line current by the reference cell, and determines the logical value of the data written as the right rank.

As illustrated, in the conventional flash memory, the main memory flash cell array 20 and the reference cell array 30 are disposed at different positions, which is highly likely to cause a defect due to process variation. There is a problem that the chip size is also increased.

The present invention has been made to solve the above problems, and an object of the present invention is to propose a flash memory structure that can reduce the possibility of failure due to process variation.

In addition, another object of the present invention is to propose a flash memory structure capable of reducing a chip size.

In the flash memory of the present invention for achieving the above object, a main flash cell array having a two-dimensional set of flash cells for writing bit data and a reference threshold voltage for determining a value written in the main flash cell are recorded. A flash cell array unit including a reference cell array; A word line decoder for selecting a word line of the main flash cell array according to a first address among addresses for indicating each flash cell; A bit line decoder for selecting a bit line of the main flash cell array according to a second address among addresses for indicating each flash cell; And a sense amplifier unit for amplifying a potential difference between the bit line of the main flash cell array selected according to the bit line decoder unit and the bit line of the reference cell array.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, terms or words used in the specification and claims should not be construed as having a conventional or dictionary meaning, and the inventors should properly explain the concept of terms in order to best explain their own invention. Based on the principle that can be defined, it should be interpreted as meaning and concept corresponding to the technical idea of the present invention. Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiment of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.

(Example)

The flash memory of the present embodiment as shown in FIG. 2 uses a main flash cell array 122 and a value written in the main flash cell 122, in which two flash cells for writing 1-bit data are formed in a two-dimensional set. A flash cell array unit 120 including a reference cell array 124 in which a reference threshold voltage is recorded for determining; A word line decoder (110) for selecting a word line of the main flash cell array (122) according to a word line address for indicating each flash cell; A bit line decoder 150 for selecting a bit line of the main flash cell array 122 according to a bit line address for indicating each flash cell; And a sense amplifier unit 160 for amplifying a potential difference between the bit line of the main flash cell array 122 selected according to the bit line decoder unit 150 and the bit line of the reference cell array 124.

The illustrated flash cell array 120 physically implements the main flash cell array 122 and the reference cell array 124 in one region. Since it is physically implemented in one region, there is an advantage in that process deviation between the main flash cell and the reference cell used when reading data is small, but it can be formed on the same well as shown in FIG. It is simultaneously affected by the voltage applied to the (substrate) stage. In the flash memory structure of the present embodiment, both the main flash cell and the reference cell may be formed of a MOS transistor having a double gate (control gate and floating gate) layer. At this time, in order to read the data, the reference cell should maintain a state in which a predetermined charge amount (which can be variously implemented, such as a charge amount in the middle of the full-charge amount of the main flash cell, or a full-charge amount) can be stored. In addition, the source terminal of the main flash cell and the reference cell having the same word line address are connected to the common node, and the drain terminal is connected to each bit line shown in FIG. 2, and is activated by the word line decoder 110. The main word line is connected to the control gate terminal of the main flash cell, and the reference word line activated by the reference word line decoder unit 140 is connected to the control gate terminal of the reference cell.

The word line decoder 110 selects a word line address among the word lines of the main memory cell array 122 as in the prior art.

The bit line decoder 150 selects a corresponding bit line address among the bit lines of the main memory cell array 122 as in the related art. Rather than performing a selection operation on a reference bit line in which only one exists, the reference bit line is connected to each input terminal of the sense amplifier unit 160 at a time when the sense amplifier unit 160 performs a comparative amplification operation. Can be implemented to perform

The sense amplifier unit 160 includes a plurality of sense amplifiers. Each sense amplifier compares a current flowing from a bit line selected by the bit line decoder 150 with a current flowing from a reference bit line. Serves to determine a logic value that has been written to the selected flash cell as a relationship.

The number of sense amplifiers included in the sense amplifier unit 160 may be implemented so that the number of the sense amplifiers is at least one to the maximum number of bit lines, and the number of bits for the width of data for input / output may be provided externally. .

The flash memory is collectively erased in predetermined sector units. In the flash memory of the present embodiment, since the flash cell and the reference cell are formed in the same well region of the same substrate as shown in FIGS. The reference cell must be prevented from being erased.

3 illustrates a method of preventing the reference cell from being erased in the case of a flash memory in which batch erase is performed by a substrate erase method. In the substrate erasing method, a positive high potential is applied to a substrate and a negative high potential is applied to a gate while the source and the drain of the cell morph transistor are floated to perform the erase. In this case, in order to prevent erasing of the reference cell, a negative high potential may be applied to the control gate of the main memory flash cell and a positive high potential may be applied to the control gate of the reference cell.

4 illustrates a method of erasing a reference cell in the case of a flash memory in which batch erase is performed by a source-gate erase method. In the source-gate erase method, a positive high potential is applied to a source while a drain of a cell MOS transistor is floated, and a negative high potential is applied to a control gate to perform erasure. Even in this case, in order to prevent the erasing of the reference cell, a negative high potential may be applied to the control gate of the main memory flash cell and a positive high potential may be applied to the gate of the reference cell during the erase command.

The reference word line decoder of the present embodiment not only serves to enable the corresponding flash cell during the read operation of the memory, but is also applied to the control gate of the reference cell as described above so that the reference cell is not erased when data is erased. It also regulates the voltage.

That is, when the reference word line decoder 140 of the present embodiment receives an erase signal for instructing deletion of data recorded in the corresponding sector, the high-positive voltage or device higher than the power supply voltage of the general circuit module in the device. A high-negative voltage that is lower than the ground voltage of a typical circuit module (greater absolute value) is configured to be applied to the control gate of the reference cell through the reference word line of the sector.

5 and 6 illustrate only two types of voltages output by the reference word line decoder, VPPX voltage and VEEI voltage. In a practical implementation, the general power supply voltage (VDD) and the high-positive voltage are represented by the VPPX voltage. One of the voltages VPP is selected, and one of the high-negative voltage VEP and the general ground voltage VSS is selected as the VEEI voltage. Therefore, a configuration for determining the VPPX voltage and the VEEI voltage according to the read signal (VDD and VSS selection) and the write signal (VPP and VEP selection) in the device must be further included, which is according to the read / write signal. The description is omitted since it is a publicly known technology that can be implemented by selecting one of the switches to be connected to the output line. Meanwhile, the general power supply voltage VDD refers to a voltage applied to the control gate of the main flash cell selected by the word line decoder when data is read, and the general ground voltage VSS is not selected when data is read. The voltage applied to the control gate of the main flash cell. However, the general power supply voltage VDD and the general ground voltage VSS are generally used as the power supply voltage and the ground voltage in other general circuit components of the flash memory device.

Meanwhile, in the manufacturing and tuning process before the release of the flash memory device, it may be necessary to delete the reference cell. To this end, the reference word line decoder 140 of the present exemplary embodiment may be implemented to receive a reference erase signal that commands the deletion of the selected reference cell. In this case, the high-negative voltage is applied to the word line of the reference cell to which the reference erase signal is input so that the reference cell is deleted. Accordingly, the reference word line decoder 140 of FIG. 5 includes a logic circuit for processing the reference erase signal REF_ER. In some cases, only the reference cell may be deleted, but considering that the sub-strate of the main flash cell and the reference cell are shared, the main flash cell of the same sector is also deleted when the reference cell is deleted. It is economical to implement.

A process of reading data performed in the flash memory of the present embodiment will be described. The external device receives an address for reading or verifying the main memory flash cell array. The word line decoder 110 activates the corresponding word line of the main flash cell array 122 and the reference word line decoder 140 activates the reference word line according to the word line address which is a part of the received address. Choose. The bit line decoder 150 connects the corresponding bit line of the main flash cell array 122 to the sense amplifier 160 according to the bit line address which is a part of the input address. When the current of the corresponding bit line flows into the first input terminal of each sense amplifier, the current of the reference bit line also flows into the second input terminal of each sense amplifier. Each sense amplifier compares the current of the input flash cell bit line with the current of the reference bit line, converts the superiority relation into a logic value, and outputs the result.

Although the present invention has been described by way of limited embodiments and drawings, the present invention is not limited thereto, and the technical spirit of the present invention and the claims to be described below by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible within the scope of equivalents.

If the flash memory is implemented according to the spirit of the present invention, there is an effect of reducing the possibility of failure due to the deviation in the process.

In addition, the flash memory of the present invention can also reduce the chip size.

Claims (7)

delete A flash cell array unit including a main flash cell array having two-dimensional sets of flash cells for writing bit data and a reference cell array indicating a reference threshold voltage for determining a value recorded in the main flash cell; A word line decoder for selecting a word line of the main flash cell array according to a first address among addresses for indicating each flash cell; A reference word line decoder for selecting a word line of the reference cell array according to the first address; A bit line decoder for selecting a bit line of the main flash cell array according to a second address among addresses for indicating each flash cell; And A sense amplifier unit for amplifying a potential difference between the bit line of the main flash cell array selected according to the bit line decoder unit and the bit line of the reference cell array, The main flash cell and the reference cell having the same word line address correspond to each other. A flash memory formed on the same well and sharing a potential applied to the substrate stage. The method of claim 2, wherein the main flash cell and the reference cell having the same word line address correspond to each other. Flash memory, characterized in that the source terminal is connected to the same line. The method of claim 2 or 3, wherein the reference word line decoder unit, The flash characterized by applying a high-positive voltage higher than the power supply voltage applied to the selected word line to the reference word line of the sector when the erase signal for deleting data written in the sector is input. Memory. The method of claim 4, wherein the reference word line, Flash memory, characterized in that connected to the control gate terminal of the reference cell. The method of claim 5, wherein the reference word line decoder unit, When performing the operation according to the erase signal, the high-positive voltage is applied to the selected reference word line, And a logic circuit configured to apply a voltage equal to the word line of the corresponding main flash cell to each reference word line when performing a data read operation. The method of claim 6, wherein the reference word line decoder unit, Also receives a reference erase signal to delete the selected reference cell. And applying the high-negative voltage to a word line of a reference cell to which the reference erase signal is input.

Images