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KR100641954B1 - Memory Device Prevents Well Junction Latch-Up - Google Patents

Memory Device Prevents Well Junction Latch-Up Download PDF

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KR100641954B1
KR100641954B1 KR1020040054034A KR20040054034A KR100641954B1 KR 100641954 B1 KR100641954 B1 KR 100641954B1 KR 1020040054034 A KR1020040054034 A KR 1020040054034A KR 20040054034 A KR20040054034 A KR 20040054034A KR 100641954 B1 KR100641954 B1 KR 100641954B1
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well
latch
memory device
supply voltage
junction
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박강태
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191—Manufacturing their doped wells

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Abstract

본 발명은 웰 접합 부분에 이온 주입을 통해 P-N 접합 공핍 영역(depletion region)을 증가시킴으로써 웰 간에 역방향 바이어스(reverse bias)를 인가하는 것과 동일한 작용에 의해 웰 접합 부분에서 발생하는 래치 업 현상을 방지하는 메모리 장치를 나타낸다. 이를 위해, 공급전압과 접지전압 사이에 PNPN 구조가 형성되는 삼중 웰 구조의 메모리 장치에 있어서, 공급전압이 인가되는 제 1 소자가 형성된 제 1 웰과, 접지전압이 접속되는 제 2 소자가 형성된 제 2 웰 및 제 1 웰과 제 2 웰의 경계 면에 공핍 영역을 증가시키기 위해 N형 이온 또는 P형 이온을 주입하는 제 1 이온 주입 영역을 포함하는 것을 특징으로 한다.The present invention increases the PN junction depletion region through ion implantation into the well junction, thereby preventing the latch-up phenomenon occurring at the well junction by the same action as applying a reverse bias between the wells. Represents a memory device. To this end, in a memory device having a triple well structure in which a PNPN structure is formed between a supply voltage and a ground voltage, a first well having a first element to which a supply voltage is applied and a second element to which a ground voltage is connected are formed. And a first ion implantation region for implanting N-type or P-type ions to increase the depletion region at the interface between the second well and the first well and the second well.

Description

웰 접합 래치 업 현상을 방지하는 메모리 장치{Memory device for preventing a latch-up in a well junction}Memory device for preventing a latch-up in a well junction}

도 1은 일반적인 삼중 웰 구조의 회로를 나타낸 단면도.1 is a cross-sectional view showing a circuit of a typical triple well structure.

도 2는 도 1의 단면도에서 웰 저항과 기생 바이폴라 트랜지스터들에 의해 형성되는 PNPN 구조를 나타낸 회로도.FIG. 2 is a circuit diagram illustrating a PNPN structure formed by well resistances and parasitic bipolar transistors in the cross-sectional view of FIG. 1.

도 3은 본 발명에 따른 삼중 웰 구조의 회로를 나타낸 단면도.3 is a cross-sectional view showing a circuit of a triple well structure according to the present invention.

도 4는 본 발명에 따른 삼중 웰 구조의 회로의 다른 실시예를 나타낸 단면도.4 is a cross-sectional view of another embodiment of a circuit of a triple well structure according to the present invention;

본 발명은 웰 접합(well junction)에서 발생하는 래치 업(latch-up) 현상을 방지하는 방법에 관한 것으로, 보다 상세하게는 웰 접합 부분에 이온 주입을 통해 P-N 접합 공핍 영역(depletion region)을 증가시킴으로써 웰 간에 역방향 바이어스(reverse bias)를 인가하는 것과 동일한 작용에 의해 웰 접합 부분에서 발생하는 래치 업 현상을 방지하는 방법에 관한 것이다.The present invention relates to a method for preventing a latch-up phenomenon occurring at a well junction, and more particularly, to increase a PN junction depletion region through ion implantation into a well junction. The present invention relates to a method of preventing a latch up phenomenon occurring at a well junction by the same action as applying a reverse bias between wells.

도 1은 일반적인 삼중 웰 구조의 회로를 나타낸 단면도이다.1 is a cross-sectional view showing a circuit of a general triple well structure.

P 기판(2) 내에 N 웰(4)을 형성하고, N 웰(4) 내에 P 웰(6)을 형성한다. 또한, N 웰(4) 내에 PMOS 트랜지스터(PT)를 형성하고, P 웰(6) 내에 NMOS 트랜지스터(NT)를 형성한다. 여기서, P 기판(2)에 접지전압(VSS)이 인가되고, N 웰(4)에 승압전압(VPP)이 인가되고, P 웰(6)에 백바이어스 전압(VBB)이 인가된다.An N well 4 is formed in the P substrate 2, and a P well 6 is formed in the N well 4. In addition, a PMOS transistor PT is formed in the N well 4, and an NMOS transistor NT is formed in the P well 6. Here, the ground voltage VSS is applied to the P substrate 2, the boosted voltage VPP is applied to the N well 4, and the back bias voltage VBB is applied to the P well 6.

PMOS 트랜지스터(PT) 및 NMOS 트랜지스터(NT)의 공통 게이트에 입력 신호(VI)가 입력되고, 공통 드레인에서 입력신호(VI)와 위상이 반대인 출력신호(VO)가 출력된다.The input signal VI is input to the common gate of the PMOS transistor PT and the NMOS transistor NT, and an output signal VO having a phase opposite to that of the input signal VI is output from the common drain.

도 2는 도 1의 단면도에서 웰 저항(R1, R2)과 기생 바이폴라 트랜지스터들(BT1, BT2)에 의해 형성되는 PNPN 구조를 나타낸 회로도이다.FIG. 2 is a circuit diagram illustrating a PNPN structure formed by well resistances R1 and R2 and parasitic bipolar transistors BT1 and BT2 in the cross-sectional view of FIG. 1.

PNPN 구조는 각각의 베이스(base)가 서로의 이미터(emitter)에 접속되고, 콜렉터(collector)에 공급전압(VDD)이 인가되고, 이미터에 P 웰(6)의 웰 저항(R1)을 통해 백바이어스 전압(VBB)이 인가되는 기생 PNP 바이폴라 트랜지스터(BT1) 및 콜렉터가 접지전압(VSS)에 접속되고, 이미터에 N 웰(4)의 웰 저항(R2)을 통해 승압전압(VPP)이 인가되는 NPN 바이폴라 트랜지스터(BT2)를 포함한다.In the PNPN structure, each base is connected to each other emitter, a supply voltage VDD is applied to the collector, and the well resistance R1 of the P well 6 is applied to the emitter. The parasitic PNP bipolar transistor BT1 and the collector to which the back bias voltage VBB is applied are connected to the ground voltage VSS, and the boost voltage VPP is connected to the emitter through the well resistance R2 of the N well 4. This includes the applied NPN bipolar transistor BT2.

일반적으로 래치 업(latch-up) 현상은 입력단자에 펄스 신호가 인가될 때 커플링(coupling) 효과에 의한 노드 A 및 B의 전압 변동에 의해 웰 저항(R1, R2) 양단에 걸리는 전압이 커져 핫 캐리어(hot carrier)에 의한 기판 전류와 웰 저항에 의해 발생한다.In general, a latch-up phenomenon causes a voltage across the well resistors R1 and R2 to increase due to a voltage variation of nodes A and B due to a coupling effect when a pulse signal is applied to an input terminal. It is caused by substrate current and well resistance by hot carriers.

상기와 같은 래치 업 현상은 삼중 웰 구조가 적용되면 발생하지 않지만, N 웰(4)에서의 PMOS 트랜지스터(PT)의 소스에 인가되는 공급전압(VDD)과 기판 바이어 스로 인가되는 승압전압(VPP)의 DC 레벨 차이에 의해 래치 업 현상이 발생한다. 즉, N 웰(4)에서 기판 바이어스로 인가되는 승압전압(VPP)과 PMOS 트랜지스터(PT)의 소스에 인가되는 공급전압(VDD) 사이의 전압 차이가 전위장벽을 넘어서 순방향 다이오드의 턴 온 조건(일반적으로 0.7V 이상)이 되면 PNPN 구조가 래치 업 현상이 발생한다.The latch-up phenomenon as described above does not occur when the triple well structure is applied, but the supply voltage VDD applied to the source of the PMOS transistor PT in the N well 4 and the boost voltage VPP applied to the substrate bias are applied. The latch-up phenomenon occurs due to the DC level difference. That is, the voltage difference between the boosted voltage VPP applied as the substrate bias in the N well 4 and the supply voltage VDD applied to the source of the PMOS transistor PT exceeds the potential barrier and the turn-on condition of the forward diode ( In general, the PNPN structure latches up.

특히, 빠른 공급전압(VDD) 전위 램프 업 조건(ramp up condition)에서는 승압전압(VPP)을 초기화시키는 장치에 의한 공급 능력은 승압전압(VPP) 파워 라인의 저항과, 초기에 승압전압(VPP) 레벨로 충전(charge up)되어야 하는 각 노드들과 웰의 캐패시턴스(capacitance)에 의해 결정된다.In particular, in a fast supply voltage VDD potential ramp-up condition, the supply capability of the device to initialize the boost voltage VPP is determined by the resistance of the boost voltage VPP power line and the initial boost voltage VPP. It is determined by the capacitance of each node and well that should be charged up to the level.

따라서, 빠른 파워 온 조건에서 외부로부터의 강한 공급전압(VDD)의 공급 능력은 승압전압(VPP)의 공급 능력보다 빠르기 때문에 래치 업 현상이 발생하는 문제점이 있다.Therefore, in the fast power-on condition, since the supply capability of the strong supply voltage VDD from the outside is faster than the supply capability of the boosted voltage VPP, there is a problem that a latch-up phenomenon occurs.

상기한 문제점을 해결하기 위한 본 발명의 목적은 다중웰 구조에서 웰 경계에 이온 주입에 의해 공핍 영역을 증가시켜 래치 업 현상을 방지하는 것이다.An object of the present invention for solving the above problems is to increase the depletion region by ion implantation in the well boundary in the multi-well structure to prevent the latch-up phenomenon.

상기한 목적을 달성하기 위한 본 발명의 웰 접합 래치 업 현상을 방지하는 메모리 장치는 공급전압과 접지전압 사이에 PNPN 구조가 형성되는 삼중 웰 구조의 메모리 장치에 있어서, 공급전압이 인가되는 제 1 소자가 형성된 제 1 웰; 접지전압이 접속되는 제 2 소자가 형성된 제 2 웰; 및 제 1 웰과 제 2 웰의 경계 면에 공핍 영역을 증가시키기 위해 N형 이온 또는 P형 이온을 주입하는 제 1 이온 주입 영역을 포함하는 것을 특징으로 한다.A memory device for preventing the well junction latch-up phenomenon of the present invention for achieving the above object is a memory device of a triple well structure in which a PNPN structure is formed between a supply voltage and a ground voltage, the first device to which the supply voltage is applied. A first well formed with; A second well having a second element connected to a ground voltage; And a first ion implantation region for implanting N-type ions or P-type ions to increase the depletion region at the interface between the first well and the second well.

상술한 목적 및 기타의 목적과 본 발명의 특징 및 이점은 첨부도면과 관련한 다음의 상세한 설명을 통해 보다 분명해 질 것이다.The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

이하, 첨부 도면을 참조하여 본 발명의 실시예를 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3은 본 발명에 따른 삼중 웰 구조의 회로를 나타낸 단면도이다.3 is a cross-sectional view showing a circuit of a triple well structure according to the present invention.

P 기판(2) 내에 N 웰(4)을 형성하고, N 웰(4) 내에 P 웰(6)을 형성한다. 또한, N 웰(4) 내에 PMOS 트랜지스터(PT)를 형성하고, P 웰(6) 내에 NMOS 트랜지스터(NT)를 형성한다. 여기서, P 기판(2)에 접지전압(VSS)이 인가되고, N 웰(4)에 승압전압(VPP)이 인가되고, P 웰(6)에 백바이어스 전압(VBB)이 인가된다. An N well 4 is formed in the P substrate 2, and a P well 6 is formed in the N well 4. In addition, a PMOS transistor PT is formed in the N well 4, and an NMOS transistor NT is formed in the P well 6. Here, the ground voltage VSS is applied to the P substrate 2, the boosted voltage VPP is applied to the N well 4, and the back bias voltage VBB is applied to the P well 6.

PMOS 트랜지스터(PT) 및 NMOS 트랜지스터(NT)의 공통 게이트에 입력 신호(VI)가 입력되고, 공통 드레인에서 입력신호(VI)와 위상이 반대인 출력신호(VO)가 출력된다.The input signal VI is input to the common gate of the PMOS transistor PT and the NMOS transistor NT, and an output signal VO having a phase opposite to that of the input signal VI is output from the common drain.

또한, N 웰(4)과 P 웰(6)의 경계 면(8)에 P 또는 N 타입의 이온을 주입한다. 따라서, N 웰(4)과 P 웰(6)의 경계 면에는 공핍 영역(depletion region)이 증가하여 P-N 접합 상의 역방향 바이어스를 인가하는 것과 동일한 작용을 한다.Further, P or N type ions are implanted into the interface 8 between the N well 4 and the P well 6. Therefore, the depletion region increases at the interface between the N well 4 and the P well 6, which acts the same as applying a reverse bias on the P-N junction.

즉, 공급전압(VDD)으로부터 접지전압(VSS)으로 전류가 흘러서 발생하는 래치 업 현상을 방지할 수 있다.That is, the latch-up phenomenon caused by the current flowing from the supply voltage VDD to the ground voltage VSS can be prevented.

도 4는 본 발명에 따른 삼중 웰 구조의 회로의 다른 실시예를 나타낸 단면도 이다.Figure 4 is a cross-sectional view showing another embodiment of a circuit of a triple well structure according to the present invention.

P 기판(2) 내에 N 웰(4)을 형성하고, N 웰(4) 내에 P 웰(6)을 형성한다. 또한, N 웰(4) 내에 PMOS 트랜지스터(PT)를 형성하고, P 웰(6) 내에 NMOS 트랜지스터(NT)를 형성한다. 여기서, P 기판(2)에 접지전압(VSS)이 인가되고, N 웰(4)에 승압전압(VPP)이 인가되고, P 웰(6)에 백바이어스 전압(VBB)이 인가된다. An N well 4 is formed in the P substrate 2, and a P well 6 is formed in the N well 4. In addition, a PMOS transistor PT is formed in the N well 4, and an NMOS transistor NT is formed in the P well 6. Here, the ground voltage VSS is applied to the P substrate 2, the boosted voltage VPP is applied to the N well 4, and the back bias voltage VBB is applied to the P well 6.

PMOS 트랜지스터(PT) 및 NMOS 트랜지스터(NT)의 공통 게이트에 입력 신호(VI)가 입력되고, 공통 드레인에서 입력신호(VI)와 위상이 반대인 출력신호(VO)가 출력된다.The input signal VI is input to the common gate of the PMOS transistor PT and the NMOS transistor NT, and an output signal VO having a phase opposite to that of the input signal VI is output from the common drain.

또한, N 웰(4)과 P 웰(6)의 경계 면(8)에 P 또는 N 타입의 이온을 주입하고, 공급전압(VDD)이 인가되는 PMOS 트랜지스터(PT1)의 소스와 N 웰(4)의 경계 면(10) 및 접지전압(VSS)에 접속되는 NMOS 트랜지스터(NT1)의 소스와 P 웰(6)의 경계 면(12)에 P 또는 N 타입의 이온을 주입한다.In addition, the source and the N well 4 of the PMOS transistor PT1 to which P or N type ions are implanted into the interface 8 between the N well 4 and the P well 6 and to which a supply voltage VDD is applied. P or N type ions are implanted into the source 10 of the NMOS transistor NT1 and the interface 12 of the P well 6 connected to the interface 10 and the ground voltage VSS.

따라서, N 웰(4)과 P 웰(6)의 경계 면(8), 공급전압(VDD)이 인가되는 영역과 N 웰(4)의 경계 면(10) 및 접지전압(VSS)에 접속되는 영역과 P 웰(6)의 경계 면(12)의 공핍 영역(depletion region)이 증가하여 P-N 접합 상의 역방향 바이어스를 인가하는 것과 동일한 작용을 한다. Therefore, the boundary surface 8 of the N well 4 and the P well 6 is connected to the region where the supply voltage VDD is applied, the boundary surface 10 of the N well 4, and the ground voltage VSS. The depletion region of the region 12 and the interface 12 of the P well 6 increases to act the same as applying a reverse bias on the PN junction.

즉, 공급전압(VDD)으로부터 접지전압(VSS)으로 전류가 흘러서 발생하는 래치 업 현상을 방지할 수 있다.That is, the latch-up phenomenon caused by the current flowing from the supply voltage VDD to the ground voltage VSS can be prevented.

이때, 이온 농도를 조절하여 원하는 영역에 선택적으로 주입함으로써 래치 업 특성을 조절할 수 있다.In this case, the latch-up characteristic may be adjusted by selectively implanting a desired region by adjusting the ion concentration.

이상에서 살펴본 바와 같이 본 발명에 따른 웰 접합 래치 업 현상을 방지하는 메모리 장치는 웰 간 경계 면에 이온 주입에 의해 공핍 영역을 증가시켜 래치 업 현상을 방지할 수 있는 효과가 있다.As described above, the memory device for preventing the well junction latch up phenomenon according to the present invention has an effect of preventing the latch up phenomenon by increasing the depletion region by ion implantation at the interface between wells.

또한, 본 발명에 따른 웰 접합 래치 업 현상을 방지하는 메모리 장치는 공급전압과 접지전압이 인가되는 영역과 각 웰 사이의 경계 면에 이온 주입에 의해 공핍 영역을 증가시켜 래치 업 현상을 방지할 수 있는 효과가 있다.In addition, the memory device for preventing the well junction latch-up phenomenon according to the present invention can prevent the latch-up phenomenon by increasing the depletion region by ion implantation in the interface between the region where the supply voltage and the ground voltage are applied and each well. It has an effect.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (5)

공급전압과 접지전압 사이에 PNPN 구조가 형성되는 삼중 웰 구조의 메모리 장치에 있어서,A memory device having a triple well structure in which a PNPN structure is formed between a supply voltage and a ground voltage, 상기 공급전압이 인가되는 제 1 소자가 형성된 제 1 웰;A first well in which a first element to which the supply voltage is applied is formed; 상기 접지전압이 접속되는 제 2 소자가 형성된 제 2 웰; 및A second well having a second element connected to the ground voltage; And 상기 제 1 웰과 상기 제 2 웰의 경계 면에 공핍 영역을 증가시키기 위해 N형 이온 또는 P형 이온을 주입하는 제 1 이온 주입 영역을 포함하는 것을 특징으로 하는 웰 접합 래치 업 현상을 방지하는 메모리 장치.And a first ion implantation region implanting N-type ions or P-type ions to increase a depletion region at an interface between the first well and the second well. Device. 삭제delete 삭제delete 제 1 항에 있어서, The method of claim 1, 상기 제 1 소자의 공급전압이 인가되는 영역과 상기 제 1 웰의 경계 면에 공 핍 영역을 증가시키기 위한 제 2 이온 주입 영역을 더 포함하는 것을 특징으로 하는 웰 접합 래치 업 현상을 방지하는 메모리 장치.And a second ion implantation region for increasing a depletion region at an interface between the region where the supply voltage of the first element is applied and the first well. . 제 1 항 또는 제 4 항에 있어서, The method according to claim 1 or 4, 상기 제 2 소자의 접지전압이 접속되는 영역과 상기 제 2 웰의 경계 면에 공핍 영역을 증가시키기 위한 제 3 이온 주입 영역을 더 포함하는 것을 특징으로 하는 웰 접합 래치 업 현상을 방지하는 메모리 장치.And a third ion implantation region for increasing a depletion region at the interface between the ground voltage of the second element and the boundary surface of the second well.
KR1020040054034A 2004-07-12 2004-07-12 Memory Device Prevents Well Junction Latch-Up Expired - Fee Related KR100641954B1 (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63244671A (en) 1987-03-30 1988-10-12 Mitsubishi Electric Corp semiconductor equipment
JPS63252464A (en) 1987-04-09 1988-10-19 Mitsubishi Electric Corp semiconductor equipment
JPH01155654A (en) * 1987-12-11 1989-06-19 Nec Corp complementary integrated circuit
KR20010003694A (en) * 1999-06-24 2001-01-15 김영환 Method of fabricating triple well of semiconductor device using SEG
KR20010061412A (en) * 1999-12-28 2001-07-07 박종섭 Method of manufacturing a flash memory device
KR20030089866A (en) * 2002-05-20 2003-11-28 주식회사 하이닉스반도체 Method of manufacturing a semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63244671A (en) 1987-03-30 1988-10-12 Mitsubishi Electric Corp semiconductor equipment
JPS63252464A (en) 1987-04-09 1988-10-19 Mitsubishi Electric Corp semiconductor equipment
JPH01155654A (en) * 1987-12-11 1989-06-19 Nec Corp complementary integrated circuit
KR20010003694A (en) * 1999-06-24 2001-01-15 김영환 Method of fabricating triple well of semiconductor device using SEG
KR20010061412A (en) * 1999-12-28 2001-07-07 박종섭 Method of manufacturing a flash memory device
KR20030089866A (en) * 2002-05-20 2003-11-28 주식회사 하이닉스반도체 Method of manufacturing a semiconductor device

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