KR100637691B1 - Double gate device and manufacturing method thereof - Google Patents

Abstract

A dual gate device is provided to avoid a pinning phenomenon of the Fermi level of a metal electrode by forming a gate oxide layer while using two kinds of dielectric layers with different dielectric constants. A first dielectric layer made of a high dielectric layer(11a) is formed on a substrate(10). A second dielectric layer is formed on the first dielectric layer, made of a material having a lower dielectric constant than that of the first dielectric layer. A metal electrode(12) is formed on the second dielectric layer. The second dielectric layer has such a thickness as to prevent the first dielectric layer from being coupled to the metal electrode so that a gap state is not formed between the first dielectric layer and the metal electrode. The second dielectric layer is made of a SiO2 layer. The first dielectric layer has a dielectric constant of 7~30.

Description

Dual gate device and its manufacturing method {DUAL GATE DEVICE AND METHOD THEREOF}

1 is a result of comparing the capacitance (Voltage / Voltage) characteristics of the poly gate and the metal gate.

FIG. 2 is a diagram illustrating work function values according to gate oxide types for poly gates and metal gates. FIG.

3 is a diagram showing dielectric constant values of gate oxide films versus work function values of metal gates required for NMOS and PMOS devices.

4 is a cross-sectional view showing a double gate device according to a preferred embodiment of the present invention.

FIG. 5 is a gate oxide film equivalent circuit diagram of the dual gate device shown in FIG. 4. FIG.

6A and 6B are cross-sectional views illustrating a method of manufacturing the double gate device illustrated in FIG. 4.

<Explanation of symbols for the main parts of the drawings>

10: substrate

11: gate oxide film

11a: High dielectric film

11b: SiO ₂ film

12: metal electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a gate oxide film of a double gate device in which a gate electrode is made of metal, and a method of forming the same.

In general, as the integration of semiconductor devices increases, the pitch of gates decreases during the processing of a complementary metal oxide semiconductor (CMOS) device using a silicon wafer. Accordingly, when the gate electrode and the gate oxide film are formed by using the existing material as it is through the conventional CMOS process, many problems occur. Recently, a change to the new material is urgently required.

First, look at the gate electrode from the perspective as follows.

In the CMOS device manufacturing process according to the prior art, each gate electrode of the NMOS device and the PMOS device has been formed of an n-type dopant doped polysilicon film. . As a result, the NMOS device has a surface channel characteristic, whereas the PMOS device has a buried channel characteristic. The PMOS device is very weak to short channel effects unlike NMOS devices having surface channel characteristics when the width of the gate electrode is narrowed to less than a half width of 100 nm due to the buried channel characteristics. .

Accordingly, in the fabrication process of a CMOS device having a narrow gate channel length in accordance with high integration of semiconductor devices, a double gate for forming a PMOS device with a p-type doped polysilicon film to realize a PMOS device with surface channel characteristics A dual gate structure has been proposed. This double gate structure solves the problem caused by the short channel effect.

However, various problems occur in the double gate structure, one of which is a threshold voltage shift and fluctuation due to boron penetration into the channel region. In addition, there is deterioration of device characteristics due to polysilicon depletion at the gate oxide film and the gate electrode interface. These problems are fundamentally due to the use of highly doped polysilicon material rather than metal for the metal electrode of MOS structure. Therefore, the use of a metal material other than polysilicon as the metal electrode in the manufacturing process of the MOS device has a great advantage to solve the problems caused by the dopant in the polysilicon described above.

FIG. 1 is a result of comparing the CV (Capacitance / Voltage) characteristics of a poly gate having a gate electrode made of a polysilicon film and a metal gate made of a metal material. As shown in FIG. 1, in the case of the metal gate, the polysilicon depletion effect does not occur, and thus the device characteristics are improved by showing a relatively increased capacitance value per unit area. In the case of poly-gate, the doped polysilicon film is used, which increases resistance compared to other metal materials, causing RC delay during device operation. It is advantageous to use.

As described above, in order to solve the large resistance value of the poly gate used as the gate electrode of the MOSFET in the prior art and the poly silicon depletion phenomenon inevitably generated during the process, the selection of the metal gate is strongly required for the next generation CMOS device. .

On the other hand, it is as follows from the viewpoint of the gate oxide film.

The gate oxide film used in the MOSFET device must be reduced in thickness to reduce the short channel effect that increases as the gate pitch decreases. When the thickness of the gate oxide thinned by this reason is less than 25 μs, the probability of electrons in the metal region tunneling the gate oxide is increased quantum mechanically, which increases the off leakage current of the MOSFET device. Will lower.

Therefore, in order to reduce the leakage current caused by the tunneling caused by the thin gate oxide thickness due to the gate design rule reduction, a high dielectric constant having a higher dielectric constant than that of conventional SiO ₂ is used as the gate oxide material. Must be used

As described above, in the next-generation CMOS device manufacturing process, the gate electrode should be formed of a metal instead of the conventional polysilicon, and the gate oxide film should be formed of a material having a high dielectric constant instead of the conventional SiO ₂ . However, when the gate electrode is used as a metal, a large problem does not occur in the existing poly gate.

At the interface between the metal gate and the gate oxide film, electrons of the metal gate penetrate toward the gate oxide film to create an interface state. Because of this interface state, numerous free electrons exist in the conduction band of the metal gate side. Metal electrons higher than the energy of the gap state on the gate oxide side fill the vacated gap state so that the fermi level of the metal gate is pinned. As a result, a dipole is formed in the gate oxide layer, thereby changing the work function of the metal gate. Due to the Fermi level pinning phenomenon, the work function of the metal gate is moved toward the midgap of the silicon band. In this case, the threshold voltage of the CMOS device is increased. The degree of pinning of the Fermi level increases in proportion to the dielectric constant of the gate oxide film.

On the other hand, in the poly gate, the Fermi level pinning phenomenon occurring in the metal gate does not occur. The reason is that even though the gap state exists in the gate oxide film, since the poly gate is a semiconductor in nature, there are no free electrons in the forbidden gap, so there are no electrons to supply the gap state.

FIG. 2 is a diagram illustrating work function values by gate oxide film types for poly gates and metal gates. As shown in FIG. 2, the poly gate shows a constant work function value for the NMOS and PMOS devices irrespective of the dielectric constant value of the gate oxide film, but for the metal gate, the dielectric constant of the gate oxide film for the NMOS and PMOS devices is shown. As the value increases (the X-axis value is the dielectric constant), the work function value moves toward the midgap of the silicon.

In the double metal gate manufacturing process, such as the double poly gate manufacturing process, two kinds of metals having appropriate work function values are required for the NMOS and PMOS devices, respectively. In other words, electrodes having a work function of 4.1 to 4.4 eV for NMOS devices and 4.8 to 5.1 eV for PMOS devices are required.

FIG. 3 is a diagram showing dielectric constant values of gate oxide films with respect to work function values of metal gates required for such NMOS and PMOS devices. As shown in FIG. 3, the higher the Fermi level pinning phenomenon becomes, the higher the use of a high dielectric material having a high dielectric constant as the gate oxide layer, the gate electrode of the NMOS device should have a smaller work function value, and conversely, The gate electrode needs a higher work function value.

However, it is fundamentally impossible to select metal electrodes with such various values. Until now, research on the development of metal electrodes with appropriate NMOS and PMOS device work functions based on SiO ₂ gate oxides has been conducted for many years. As a result, no clear double metal gate can be selected to completely replace the double poly gate. There is a situation.

Accordingly, the present invention has been made to solve the above-described problems of the prior art, the metal electrode according to the dielectric constant value of the gate oxide film used in the manufacturing process of the double metal gate using the metal gate electrode and the high-k gate oxide film. It is an object of the present invention to provide a double gate device capable of preventing the Fermi level pinning phenomenon and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a substrate, a first dielectric film formed of a high dielectric film on the substrate, and a material having a dielectric constant lower than that of the first dielectric film on the first dielectric film. A second dielectric layer and a metal electrode formed on the second dielectric layer, wherein the second dielectric layer is coupled to the first dielectric layer and the metal electrode to prevent a gap state from being formed between the first dielectric layer and the metal electrode. Provided is a double gate element, formed to a thickness so as not to be.

According to another aspect of the present invention, there is provided a method of forming a first dielectric layer on a substrate using a high dielectric layer, and a material having a lower dielectric constant than the first dielectric layer on the first dielectric layer. Forming a second dielectric layer, forming a metal electrode on the second dielectric layer, and etching the metal electrode and the first and second dielectric layers to form a gate electrode. The dielectric layer is formed to have a thickness such that the first dielectric layer and the metal electrode are not bonded so that a gap state is not formed between the first dielectric layer and the metal electrode.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

4 is a cross-sectional view illustrating a double gate device according to an exemplary embodiment of the present invention.

As shown in FIG. 4, the double gate device according to the preferred embodiment of the present invention includes a gate oxide film 11 formed of two kinds of dielectric films 11a and 11b having different dielectric constant values. Among the dielectric films 11a and 11b of the gate oxide film 11, the upper dielectric film 11b, which is in contact with the metal electrode 12, is preferably formed of SiO ₂ to suppress the Fermi level pinning phenomenon of the metal electrode 12. In this case, the thickness of the SiO ₂ film 11b may vary depending on the material of the lower dielectric film 11a. Preferably, the thickness of the SiO ₂ film 11b is greater than or equal to the thickness at which the gap state is formed. In addition, the SiO ₂ film 11b is formed by ALD (Atomic Layer Deposition) or CVD (Chemical Vapor Deposition) method, and when using the ALD method, it is in-situ with the upper dielectric film 11a to ensure uniformity. -situ). On the other hand, the lower dielectric film 11a is formed of a material having a higher dielectric constant value than the SiO ₂ film 11b (approximately 3.8 to 4.2), but preferably a material having a dielectric constant value of about 7 to 30.

FIG. 5 is a diagram illustrating an equivalent circuit of the gate oxide film 11 shown in FIG. 4. As shown in Fig. 5, when the gate oxide film 11 is formed of two kinds of dielectric films 11a and 11b having different dielectric constant values, it can be considered as an equivalent circuit in which two types of capacitors are connected in series. Can be. That is, the dielectric film 11a may be formed of a capacitor having a dielectric constant of e2 and a thickness of d2, and the dielectric film 11b may be formed of a capacitor having a dielectric constant of e1 and a thickness of d1.

In this case, the total capacitance value C _total may be represented by Equation 1 below. Meanwhile, in Equation 1, 'C1' is the capacitance of the dielectric film 11b, 'C2' is the capacitance of the dielectric film 11a, 'A1' is the area of the dielectric film 11b, and 'A2' Is the area of the dielectric film 11a.

As in the preferred embodiment of the present invention, when the SiO ₂ film 11b is interposed between the metal electrode 12 and the high dielectric film 11a, the MOS is entirely formed of the high dielectric film 11a as shown in Equation 1 above. Although the capacitance becomes smaller than the capacitance value of the capacitor, the total capacitance is maintained larger than that of the MOS capacitor composed entirely of the SiO ₂ film 11b, so that the leakage current can be suppressed.

Hereinafter, a method of manufacturing a double gate device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 6A and 6B. 6A and 6B are cross-sectional views of a double gate device.

First, as shown in FIG. 6A, a high dielectric film 11a having a dielectric constant of about 7 to about 30 is deposited on the substrate 10.

Subsequently, an SiO ₂ film 11b having a lower dielectric constant than the high dielectric film 11a is deposited on the high dielectric film 11a. At this time, the SiO ₂ film 11b is deposited to a thickness greater than or equal to the gap state is formed using an ALD or CVD method.

Subsequently, the metal electrode 12 is deposited on the SiO ₂ film 11b.

Subsequently, as shown in FIG. 6B, a photolithography process is performed to sequentially etch the metal electrode 12, the SiO ₂ film 11b, and the high dielectric film 11a to form a gate electrode.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, a metal electrode is formed by forming a gate oxide film using two kinds of dielectric films having different dielectric constant values in a double metal gate manufacturing process using the metal gate electrode and the high-k gate oxide film. By preventing the Fermi level pinning phenomenon, the degree of change of the work function of the double gate device can be minimized.

Claims (10)

Board; A first dielectric layer formed of a high dielectric layer on the substrate; A second dielectric layer formed of a material having a lower dielectric constant than the first dielectric layer on the first dielectric layer; And Including a metal electrode formed on the second dielectric layer, The second dielectric layer is formed to have a thickness such that the first dielectric layer and the metal electrode are not bonded so that a gap state is not formed between the first dielectric layer and the metal electrode. Double gate element. delete The method of claim 1, The second dielectric layer is a double gate device consisting of a SiO ₂ film. delete The method of claim 1, The first dielectric layer is a double gate device made of a material having a dielectric constant value of about 7 ~ 30. Forming a first dielectric film on the substrate as a high dielectric film; Forming a second dielectric layer on the first dielectric layer using a material having a lower dielectric constant than the first dielectric layer; Forming a metal electrode on the second dielectric layer; And Etching the metal electrode and the first and second dielectric layers to form a gate electrode; The second dielectric layer may be formed to a thickness such that the first dielectric layer and the metal electrode are not bonded so that a gap state is not formed between the first dielectric layer and the metal electrode. Method of manufacturing a double gate device. delete The method of claim 6, The second dielectric film is a method of manufacturing a double gate device consisting of a SiO ₂ film. delete The method of claim 6, The first dielectric layer is a method of manufacturing a double gate device made of a material having a dielectric constant value of about 7 ~ 30.

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