KR100634410B1 - Flash memory where multiple bit lines share a sense amplifier - Google Patents

Abstract

The present invention relates to a flash memory in which a plurality of bit lines share a sense amplifier. The flash memory according to the present invention includes a memory cell array, a sense amplifier circuit, and a bit line sharing circuit. The memory cell array has a plurality of memory blocks arranged in a row direction or a column direction. The sense amplifier circuit senses and amplifies data stored in the memory cell array. The bit line sharing circuit allows a plurality of bit lines connected to the memory cell array to share one sense amplifier. According to the present invention, the bit line loading can be reduced and the sensing speed can be increased.

Description

FLASH MEMORY IN WHICH A PLURALITY OF BITLINES SHARE A SENSE AMPLIFIER}

1 is a block diagram schematically illustrating a flash memory according to the prior art.

FIG. 2 is a circuit diagram illustrating one sense amplifier in the sense amplifier circuit shown in FIG. 1.

3 is a block diagram illustrating an embodiment of a flash memory according to the present invention.

FIG. 4 is a circuit diagram illustrating a part of the sense amplifier circuit and the bit line sharing circuit shown in FIG. 3.

FIG. 5 is a circuit diagram illustrating a part of a sense amplifier circuit and a bit line sharing circuit when the cell array is expanded to four cells in FIG. 3.

* Description of the symbols for the main parts of the drawings *

100, 300: flash memory 110, 120, 310, 320: cell array

130, 330: decoder 140, 340: control circuit

200, 410: sense amplifier circuit 420: bit line sharing circuit

The present invention relates to a flash memory, and more particularly to a flash memory in which a plurality of bit lines share a sense amplifier.

Flash memory is a nonvolatile memory that can store data without a power source, which is called flash EEPROM (Flash Electrically Erasable Programmable Read Only Memory) or Flash E ² PROM.

Flash memory is generally divided into NAND flash memory and NOR flash memory. NOR flash memory has a structure in which memory cells are independently connected to bit lines and word lines, so that random access time is fast. The NAND flash memory has excellent characteristics in terms of integration since a plurality of memory cells are connected in series.

1 is a block diagram schematically illustrating a flash memory according to the prior art. Referring to FIG. 1, the flash memory 100 includes memory cell arrays 110 and 120, a decoder 130, a sense amplifier circuit 200, and a control circuit 140.

The memory cell array has a plurality of memory blocks that are units of erase. The memory cell array includes memory cells connected to a plurality of word lines WLi extending along rows and a plurality of bit lines BLj extending along columns. . The word lines are composed of 16, 32, 64, etc., and the bit lines are composed of 1024 bytes or 2048 bytes.

Referring back to FIG. 1, the memory cell array includes a first cell array 110 and a second cell array 120 arranged in a column direction in which bit lines BLj extend. Here, the first and second cell arrays 110 and 120 are conceptual divisions for convenience of description, and are not thus divided in the actual flash memory. The first and second cell arrays each include a plurality of memory blocks.

One side of the memory cell array is connected to the decoder 130 through a word line WLi, and the other side of the memory cell arrays 110 and 120 is connected to the sense amplifier circuit 200 through a bit line BLj. It is connected. In addition, a control circuit 140 that provides a control signal ctrl1 for controlling an operation of the sense amplifying circuit 200 is located at one side of the sense amplifying circuit 200.

FIG. 2 is a circuit diagram illustrating one sense amplifier in the sense amplifier circuit shown in FIG. 1. The sense amplifier 200 is used in a NAND flash memory and is commonly referred to as a page buffer. Referring to FIG. 2, the sensing amplifier 200 receives a control signal Ctrl1 from the control circuit 140 (see FIG. 1). Here, the control signal Ctrl1 indicates PLOAD, PBLCH, BLSLT, and the like shown in FIG. 2.

The sense amplifier 200 includes a PMOS transistor TR4 precharges the bit line BL1 in response to a PLOAD signal; A latch composed of two inverters INV1 and INV2 and storing data; A selection transistor TR1 for switching the bit line BL1 in response to the BLSLT signal; A transistor TR3 for initializing the latch in response to a latch signal PBLCH; And a transistor TR2 that is turned on when the voltage level of the bit line BL1 is 'high' to initialize the latch. Data read from the memory cell is output through the data line PB_DIO. The operating principle of the sensing amplifier 200 is omitted because it is well known to those skilled in the art.

Referring back to FIG. 1, in the conventional flash memory, the memory cell array has a structure in which the second cell array 120 is disposed on the first cell array 110. As described above, in the memory cell array structure in which the cell array or the memory blocks are arranged in the column direction, the length of the bit line may also be lengthened in the column direction. If the length of the bit line is longer, the voltage for loading the bit line must be increased, and the speed of sensing the bit line is also slowed down. In addition, when the memory capacity is increased to increase the number of cell arrays or memory blocks in the column direction, it is difficult to bring the aspect ratio of the chip on the wafer at a ratio of 1: 1, thereby reducing the yield of the chip.

The present invention has been proposed to solve the above-described problem, and an object of the present invention is to provide a flash memory in which a voltage for loading a bit line does not increase and a sensing speed does not decrease even when the number of memory blocks increases.

In order to achieve the above object, a flash memory according to the present invention includes a memory cell array having a plurality of memory blocks arranged in a row direction or a column direction; A sense amplifier circuit having a plurality of sense amplifiers for sensing and amplifying data stored in the memory cell array; And a bit line sharing circuit for allowing a plurality of bit lines connected to the memory cell array to share one sense amplifier.

In this embodiment, the memory cells connected to the plurality of bit lines have the same column address.

In the present exemplary embodiment, the bit line sharing circuit may include a MOS transistor connected to the plurality of bit lines, respectively.

In this embodiment, the flash memory is NAND flash memory.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3 is a block diagram illustrating an embodiment of a flash memory according to the present invention. Referring to FIG. 3, the flash memory 300 according to the present invention includes a memory cell array 310 and 320, a decoder 330, a control circuit 340, a sense amplifier circuit 410, and a bit line sharing circuit 420. ).

The memory cell array has a plurality of memory blocks that are units of erase. The memory cell array includes memory cells connected to a plurality of word lines WLi extending along rows and a plurality of bit lines BLj extending along columns. . The word lines are composed of 16, 32, 64, etc., and the bit lines are composed of 1024 bytes or 2048 bytes.

The memory cell array has memory blocks arranged in a row direction in which a word line WLi is extended, as well as a column direction in which a bit line BLj is extended, unlike a conventional technology. In FIG. 1, the first cell array 110 and the second cell array 120 show memory blocks arranged in a column direction. In FIG. 3, the first cell array 310 and the second cell array 320 are shown in FIG. The memory blocks are arranged in the row direction.

When the memory blocks are arranged in the row direction as in the present invention, since the length of the bit lines is reduced by that much, the voltage for loading the bit lines is reduced and the sensing speed is also increased. In addition, the size of the decoder is also reduced.

Referring back to FIG. 3, one side of the memory cell array is connected to the decoder 330 through a word line WLi, and the other side of the memory cell array shares the bit line through bit lines BL1j and BL2j. Is connected to the circuit 420. The bit line sharing circuit 420 is connected to the first cell array 310 and the second cell array 320 through a first bit line BL1j and a second bit line BLj2. The bit line sharing circuit 420 is connected to the sense amplifier circuit 410 through a bit line BLj.

Meanwhile, the control circuit 340 generates a first control signal Ctrl1 for controlling the sense amplifier circuit 410 or a second control signal Ctrl2 for controlling the bit line sharing circuit 420. The overall operation of the sense amplifier circuit 410 or the bit line sharing circuit 420 is controlled.

FIG. 4 is a circuit diagram illustrating a part of the sense amplifier circuit and the bit line sharing circuit shown in FIG. 3. The sense amplifier circuit 410 is composed of a plurality of sense amplifiers, and FIG. 4 shows only one sense amplifier. The sense amplifier is a page buffer commonly used in NAND flash memory. The sensing amplifier 410 has the same configuration and operation method as the sensing amplifier 200 illustrated in FIG. 2.

The bit line sharing circuit 420 has one sensing amplifier 410 having a first bit line BL1j connected to the first cell array 310 and a second bit line BLj2 connected to the second cell array 320. It has a configuration to share. The bit line sharing circuit 420 operates in response to the second control signal Ctrl2 generated by the control circuit 340 (see FIG. 3). Here, the second control signal Ctrl2 means the selection signals SEL1 and SEL2 shown in FIG. 4. Referring to FIG. 4, the bit line sharing circuit 420 includes NMOS transistors TR5 and TR6 connected to the first and second bit lines BL1j and BL2j, respectively.

In an embodiment, the memory cells connected to the first and second bit lines BL1j and BL2j have the same column address. This is because the first and second cell arrays 310 and 320 originally have a structure arranged in a column direction as shown in FIG. 1. A first select signal SEL1 is activated to access a memory cell in the first cell array 310, and a second select signal SEL2 is accessed to access a memory cell in the second cell array 320. Is activated.

The flash memory having the structure as shown in FIGS. 3 and 4 has half the bit line loading and the sensing speed is twice as fast as the conventional flash memory shown in FIGS. 1 and 2.

 FIG. 5 is a circuit diagram illustrating a part of a sense amplifier circuit and a bit line sharing circuit when the cell array is expanded to four cells in FIG. 3. Referring to FIG. 5, one sense amplifier shares four bit lines connected to each cell array (not shown). At this time, the bit line loading is reduced by four times and the sensing speed is increased by four times.

As described above, according to the flash memory according to the present invention, since the sense amplifier can be shared and used by several bit lines, the bit line loading can be reduced and the sensing speed can be increased. In addition, the area of the sense amplifier circuitry, which must occupy a small area for high integration, can be reduced, bringing the same aspect ratio of the chip on the wafer and increasing the number of chips produced per wafer. In addition, since the distance between the sensing nodes of the sensing amplifier increases, the noise problem due to the coupling effect generated between the sensing nodes can be naturally solved.

On the other hand, in the detailed description of the present invention has been described with respect to specific embodiments, various modifications are of course possible without departing from the scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

As described above, the flash memory according to the present invention can reduce the bit line loading and speed up the sensing speed by arranging the memory blocks in the row direction and having a bit line sharing circuit therein. In addition, the aspect ratio on the wafer can be brought about at the same rate, thereby improving chip yield. Since multiple bit lines are shared by a single sense amplifier, noise due to a coupling effect between sensing nodes of the sense amplifier may be reduced.

Claims (6)

A memory cell array including a plurality of memory blocks arranged in a row direction; A sense amplifier circuit comprising a sense amplifier for sense amplifying data stored in the plurality of memory blocks; A bit line sharing circuit for sharing the sense amplifiers with a plurality of bit lines respectively connected to the plurality of memory blocks; And A control circuit for controlling the bit line sharing circuit such that any one of the plurality of memory blocks is electrically connected to the sense amplifier, And a plurality of memory blocks arranged in the row direction are configured to be selected by the same column address. The method of claim 1, And memory cells connected to the plurality of bit lines are selected by the same column address. The method of claim 1, The bit line sharing circuit includes a MOS transistor connected to the plurality of bit lines, respectively. The method of claim 3, wherein And the MOS transistor is an NMOS transistor. The method of claim 1, And the flash memory is a NAND flash memory. (delete)

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