KR100632922B1 - Low voltage charge pump circuit - Google Patents

Abstract

A low voltage charge pump circuit for generating a negative voltage is disclosed. The charge pump circuit of the present invention can maximize charge transfer efficiency when a pumping operation for supplying negative charge to a node requiring a negative voltage is performed. The gate voltage of the transfer transistor switching to transfer the negative charge is properly boosted by the voltage bootstrap technique, so that the transfer efficiency of the negative charge is improved, and it is reached quickly and easily at the desired negative voltage. In addition, since the circuit of the present invention operates at a low voltage of 1.0 V or less, the charge pump circuit of the present invention can be incorporated into a next-generation semiconductor product using a low power supply voltage.

Charge Pumps, Low Voltage, Clock, Latch, Bootstrapping, Negative Voltage

Description

Charge pumping circuit for low voltage operation

1 is a schematic block diagram showing a negative voltage generating circuit.

2 is a conventional charge pump circuit.

3 is an operation timing diagram of a conventional charge pump circuit.

5 is an operation timing diagram of a charge pump circuit according to an embodiment of the present invention.

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6 is a graph comparing current values of the pump circuit of the present invention.

7 is a graph comparing voltage values of a pumped negative voltage node of the pump circuit of the present invention.

8 is a view showing a low voltage characteristic of the present invention.

9 is a view showing an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump circuit capable of generating a negative voltage, and more particularly to a voltage applied to a gate node of switch transistors such that the generated negative voltage can be delivered to a node requiring a negative voltage. By increasing the voltage to the bootstrap voltage instead of the voltage, the negative voltage is efficiently generated without loss when the pumping of the charge is performed.

As semiconductor manufacturing technology advances, the size of devices decreases, so that more devices are integrated on a single chip. As the size of the device is reduced, the device's ability to withstand voltage, i.e., breakdown voltage, has gradually decreased. On the other hand, as the number of devices increases, so does the power consumption. According to this trend, the power supply voltage used in the semiconductor device must be lowered to reduce the destruction of the minute device by the voltage and the power consumption. According to this trend, the power supply voltage for driving a semiconductor device has gradually decreased to 5 volts, 3.3 volts, and 2.5 volts for the last decade, but such a low voltage continues.

The voltage connected to the semiconductor chip is usually a supply voltage and a ground voltage. However, when a voltage greater or less than the power supply voltage is required in a semiconductor chip, it is usually generated and used in a circuit in the chip. In addition, in order to improve various characteristics of the semiconductor device, a negative voltage may be made and used using a circuit. In particular, when a negative voltage is used in a high-density semiconductor chip such as DRAM, the refresh period is increased by reducing the parasitic current and the sub-threshold current. There is a necessity for a circuit that makes voltage. In recent years, a negative voltage is often used to drive a word line of a semiconductor DRAM in addition to the substrate voltage.

A typical negative voltage generating circuit uses a ring oscillator and a charge pump circuit to operate the capacitor and the switch circuits of the charge pump circuit in accordance with the oscillation period of the ring oscillator to draw a voltage of a node requiring a negative voltage.

Hereinafter, a typical negative voltage generation circuit will be described with reference to the drawing shown in FIG.

The capacitor C _L is an equivalent representation of the capacitive load of the node NN requiring a negative voltage. The charge pump 10 pulls the negative voltage node NN down in the manner of charge pumping. When the negative voltage node NN reaches a predetermined voltage, the level detector 11 is operated to stop the oscillation operation of the ring oscillator 12. When the operation of the ring oscillator is stopped, the pumping operation of the charge pump 10 is also stopped, so that no further negative voltage is generated and the voltage V _NN of the negative voltage node _NN is kept constant. If V _NN rises above the predetermined voltage due to the operation of the circuit or the leakage current, the ring oscillator 12 starts the oscillation operation again by the detection operation of the level detector 11 and accordingly the charge pump 10 Starts to operate, and the voltage V _NN of the negative voltage node NN is lowered again so that V _NN always maintains the target voltage.

 2 and 3 show an embodiment of a conventional charge pump circuit and its timing diagram. The operation of the conventional charge pump circuit will be described with reference to these. The level detector 11 and the ring oscillator 12 included in the conventional negative voltage generation circuit are well known and will not be described separately.

Referring to the drawing shown in FIG. 2, a conventional charge pump circuit receives a pair of non-overlapping clock signals CLK1 and CLK2 as inputs, and a pair of latch transistors MA1 and MA2 and a pair of charges. Transfer transistors MT1 and MT2, pair of bias transistors MB1 and MB2, pair of precharge transistors MP1 and MP2, two inverters I1 and I2 and four capacitors (C1, C2, C3, C4). Among them, a pair of latch transistors MA1 and MA2 and two capacitors C3 and C4 form an auxiliary pump circuit.

The two clock input signals CLK1 and CLK2 swing between the ground voltage and the power supply voltage VDD so as not to overlap each other with a predetermined period. While clock signal CLK1 is the ground voltage and CLK2 is VDD, N1 and N4 are precharged to ground voltage by precharge transistor MP1 and latch transistor MA2, respectively, and N2 is connected to negative voltage node NN by transfer transistor MT2. Connected to maintain V _NN and node N3 maintains -VDD.

When the clock CLK1 changes from the ground voltage to VDD, the voltage of the node N3 is changed from -VDD to the ground voltage by the operation of the capacitor C3 to turn off the precharge transistor MP1 and the latch transistor MA2, respectively, and the transfer transistor MT1. Turns on. At this time, since the node N1 is connected to the negative voltage node NN by MT1, the node N1 pumps the negative voltage node NN by the pumping operation of the inverter I1 and the capacitor C1. During this period, the circuits in the left half of the circuits shown in FIG. 2 operate to pump negative voltage nodes, and the circuits in the right half do not participate in pumping.

When clock CLK2 changes from VDD to ground voltage, the voltage of node N4 is changed from ground voltage to -VDD by the operation of capacitor C4.Turn on precharge transistor MP2 to precharge node N2 to ground voltage, and MT2 turn-on. Since they remain off, the circuits in the right half of FIG. 2 have no effect on the negative voltage node.

Next, when the clock CLK2 is changed from the ground voltage to VDD, the voltage of the node N4 is changed from -VDD to the ground voltage by the operation of the capacitor C4 to turn off the precharge transistor MP2 and the latch transistor MA1, respectively. Transfer transistor MT2 is turned on. At this time, since the node N2 is connected to the negative voltage node NN by MT2, the node N2 pumps the negative voltage node NN by the pumping operation of the inverter I2 and the capacitor C2. During this period, the circuits in the right half of the circuits shown in FIG. 2 operate to pump negative voltage nodes, and the circuits in the left half do not participate in pumping.

Next, when the clock CLK1 returns to the ground voltage at VDD, the circuit of FIG. 2 returns to the initial state and two pumping operations are performed during one clock cycle.

However, such a conventional charge pump circuit has a disadvantage in that the pumping efficiency decreases as described below when the transfer transistors MT1 and MT2 are turned on to pump negative charges to the negative voltage node NN. Taking the transfer transistor MT1 as an example, since the gate voltage of the transfer transistor is grounded and the source node N1 is -VDD during pumping, the transfer transistor is turned on to transfer negative charge to the negative voltage node NN. During the transfer of negative charge, the voltage of the source node N1 is gradually raised, and as soon as the voltage between the gate and the source reaches V _TN , the threshold voltage of the transfer transistor, the transfer transistor is turned off. Therefore, there is a problem that the transfer of negative charge is performed only during the period in which the voltage of the source node N1 reaches -VDD to -V _TN .

This problem described above also applies to the transfer transistor MT2. This problem becomes more serious as the supply voltage is lowered. For example, if the threshold voltage of the transfer transistor is 1V and the power supply voltage is 3.3V, the transfer of negative charge is not performed for about 33% of the entire voltage range, but in the low voltage operation with the threshold voltage of 1V and the power supply voltage of 1.8V. Since the transfer of negative charge is not performed during the 56% of the total voltage section, the pumping efficiency of the charge pump circuit is much reduced.

Accordingly, it is an object of the present invention to solve the above-mentioned problems and to provide an efficient charge pump circuit that does not degrade efficiency even at low voltage.

It is another object of the present invention to provide a charge pump circuit that operates well under low power supply voltage environment to ensure low voltage operation reliability of various semiconductor chips that will incorporate the circuit of the present invention.

In order to achieve the above object, the negative charge pumping circuit of the present invention comprises: input clock signals; Charge transfer transistors; Bias circuits; Precharge circuits; Pumping capacitors; And bootstrap circuits.

Preferably, the input clock signal is a periodic clock signal that does not overlap with each other, and the transfer transistors are directly connected to the negative voltage node to transfer negative charge to the negative voltage node. Two pumping capacitors are connected to two of the input clock signals. The bootstrap circuit is a bootstrapping circuit using two input clock signals and is composed of two bootstrap capacitors and two transistors.

Therefore, according to the charge pump circuit of the present invention to be described later, when the negative voltage is generated inside the charge pump circuit and pumped to a node requiring the negative voltage, the gate voltages of the transfer transistors switching to transfer negative charges are increased. The sum of the voltage V _NN of the negative voltage node and the power supply voltage VDD does not cause loss transfer in the transfer of negative charges.

In order to fully understand the technical idea included in the present invention, reference should be made to the description of the exemplary embodiments of the present invention and the circuits and timing diagrams of the accompanying drawings.

Hereinafter, the present invention will be described in detail by explaining preferred embodiments of the present invention with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

9 is a view for explaining a charge pump circuit according to an embodiment of the present invention. Referring to this, four clock signals CLK11 to CLK14 are inputted, and two of them, CLK12 and CLK13, are directly coupled to two pumping capacitors C11 and C12 so that a negative voltage is specified within a circuit. To the nodes N11 and N12.

The other two clock signals CLK11 and CLK14 are connected to two bootstrap capacitors C13 and C14 to transfer a negative voltage to the negative voltage node NN together with the bootstrap transistors MN11 and MN12. Bootstrapping the gate voltages of (MT11, MT12).

The clock signals CLK11 and CLK13 have the same phase, but do not overlap each other. The same applies to the clock signals CLK12 and CLK14.

The bias circuits MB11 and MB12 bias the voltage of the bulk portion of the transfer transistors MT11 and MT12.

Each of the six precharge transistors MP13 to MP18 is divided into three and precharges the nodes N11 and N12 for each required section.

The circuits in the left half of the circuits shown in FIG. 9 perform charge pumping and bootstrapping when the clock signal CLK12 changes from VDD to ground voltage. The circuit in the right half shows charge pumping and bootstrapping when the clock signal CLK13 changes from VDD to ground voltage. This is the part that works.

Table 1 shows the voltages when the voltage of each node of the circuit shown in FIG. 9 reaches a steady-state. In circuit operation, the voltage of each node starts from this steady state value and switches to another steady state.

Table 1

CLK11, CLK13 VDD 0 CLK12, CLK14 0 VDD N11 VDD 0 N12 0 VNN N13 VNN + VDD VNN N14 VNN VNN + VDD

5 is an operation timing diagram of the circuit shown in FIG. 9. With reference to these drawings will be described in detail the operation of the circuit according to an embodiment of the present invention.

Before t1, clock signals CLK11 and CLK13 maintain VDD and CLK12 and CLK14 are connected to ground voltage.

When the clock CLK11 is changed to the ground voltage at the VDD at t1, the N13 node by the role of the bootstrap capacitor C13 is reduced as much as VDD for the swing width of the steady state clock CLK11 from a voltage of V _NN + VDD of the V _NN The bootstrap transistor MN12 and the transfer transistor MT11 are turned off.

At time t2, CLK12 changes from ground voltage to supply voltage. At this moment, node N11 tries to increase the swing width of clock CLK12 to increase from V _NN by the role of pumping capacitor C11. In addition, the voltage of the node N12 is changed from the ground voltage by turning off the MN16 by the precharge elements MN14 and MP14.

At the time t3 when the clock CLK13 falls from the VDD to the ground voltage, the node N11 is in the ground voltage state because the MP15 is turned on by the operation of the precharge transistors MP13 and MP14. At this time, the node N12 is pumped down to the negative voltage by the clock CLK13 and the pumping capacitor C12.

In summary, the voltage of the node N11 is connected to the ground state during the period where the clock CLK13 is the ground voltage, and is connected to the negative voltage node NN while the clock CLK12 is the ground state to maintain the voltage state at V _NN . On the contrary, the voltage of the node N12 is connected to the ground state during the period where the clock CLK12 is the ground voltage, and is connected to the negative voltage node NN while the clock CLK13 is the ground state, so that the voltage state is maintained at V _NN .

At the instant of t4, clock CLK14 changes from ground voltage to VDD. When the period after t5 starts, the N14 node is increased from V _NN to V _NN + VDD by the bootstrap capacitor C14 to sufficiently turn on MT12. Therefore, the negative voltage pumped to N12 is transmitted to the negative voltage node NN without loss by MT12.

Clock CLK14 changes to ground voltage at the time of t5. Accordingly, the transfer transistor MT12 is turned off to stop the pumping action to the negative voltage node NN.

At the time t6, the clock CLK13 changes to VDD. As a result, the negative charge stored in N12 disappears and N11 is floated by the action of MP13, MP14, and MP15.

At the time t7, the clock CLK12 changes from VDD to the ground voltage, so that N12 is grounded by the action of MP17, MP18 and MP16, while N11 is pumped to the negative voltage by the pumping capacitor C11.

At the moment t8, the clock CLK11 increases to VDD and at the beginning of the period after t8, the bootstrap capacitor C13 bootstraps the N13 node from V _NN to V _NN + VDD, increasing the voltage by VDD to boost the MT11. Turn on. Therefore, the negative voltage pumped to N11 is transmitted to the negative voltage node NN without loss by MT11.

Summarizing the above operation as a whole, the circuit in the right half of the circuit of FIG. 9 has a negative voltage pumped at the negative edge of CLK13 and bootstraps the transfer transistor MT12 bootstraped at the positive edge of the CLK14 signal. To the negative voltage node NN. Similarly, the circuit in the left half transfers negative charge to negative voltage node NN through transfer transistor MT11 bootstraped at the positive edge of CLK11 signal at the negative edge of CLK12. That is, two pumps are designed to occur during one clock cycle.

In order to verify the performance of the circuit of the present invention, a conventional charge pump circuit was compared with the charge pump circuit of one embodiment of the present invention using a circuit simulation program.

6 is a normalized simulation to compare the pumping currents delivered to the negative voltage node with each other. Hereinafter, the superiority of the charge pump circuit of the present invention will be described with reference to the drawings. When the absolute value of the voltage of the negative voltage node NN is large, the pumping current of the conventional circuit and the circuit of the present invention does not differ significantly. However, when the absolute value of the voltage of the negative voltage node NN is small, the pumping efficiency of the conventional charge pump circuit is lower than the pumping efficiency of the charge pump circuit of the present invention for the reasons described above, it can be seen that the difference between the two.

7 is a circuit simulation of how quickly the charge pump circuit reaches a desired level of voltage. The conditions of the simulation were set assuming that the circuit of the present invention is applied to a 256M bit synchronous DRAM fabricated in a 0.12um microfabrication process, and the power supply voltage VDD = 1V, the cycle of the ring oscillator = 10MHz, and the load capacitance = 10nF. . As shown in the figure, it can be seen that the voltage of the negative voltage node NN is set up faster in the charge pump circuit of the present invention than in the conventional charge pump circuit. This is because, as described above, the circuit of the present invention bootstraps the gate voltage of the transfer transistors properly to maximize the transfer efficiency of negative charges.

FIG. 8 shows simulation results of how low a power supply voltage the circuit of the present invention can operate. As described above, as the technology develops, the light weight, miniaturization, and low power of electronic products are required. Therefore, it can be seen that a low voltage operation is also required for semiconductor devices used as components of electronic products. As shown in FIG. 8, the charge pump circuit of the present invention operates even at a power supply voltage of about 0.7V, so there is no problem even if it is applied to a next-generation semiconductor device.

Although the present invention has been described with reference to two embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. will be. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

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According to the operation of the charge pump circuit of the present invention described above, when the negative voltage is generated and transferred to the node requiring the negative voltage, the efficiency of the transfer is maximized, thereby rapidly approaching the desired negative voltage.

According to the circuit of the present invention, the charge pumping operation is easily performed even at a low power supply voltage, so that the present invention can be applied to a variety of semiconductor products incorporating the circuit of the present invention, for example, a next generation semiconductor product using a low power supply voltage of about 1V. have.

Claims (6)

In the charge pump circuit for generating a negative voltage using the clock signals, A node requiring a negative voltage; A detector for detecting that the voltage of the node reaches a constant voltage; A ring oscillator whose oscillation state is controlled by the control of the detector; A plurality of clock signals made by the ring oscillator and having a constant period; And a transfer transistor directly connected to the node for transmitting a negative voltage generated by the clock signals to the node. The transfer transistor is a low-voltage charge pump circuit, characterized in that the gate voltage is set by the voltage bootstrap technique at turn-on (turn-on). In a charge pump circuit that generates a negative voltage, A node requiring a negative voltage; A plurality of clock signals; A plurality of capacitors; Transfer transistors; Precharge circuits configured to perform a precharge operation in synchronization with one of the clock signals; And  A negative voltage is generated by operating another one of the clock signals and one of the capacitors in combination. The bootstrapping operation is performed at the gate of the transfer transistor by combining another one of the clock signals with another one of the capacitors, and at the same time, the negative voltage generated by the switching operation of the transfer transistor is applied. Low voltage charge pump circuit characterized in that the transfer to the node requiring the negative voltage. 3. The charge pump circuit as claimed in claim 1 or 2, wherein the clock signals are non-overlapping. The low voltage charge pump circuit as claimed in claim 1 or 2, wherein the clock signals comprise first to fourth clock signals. 3. The charge pump circuit for low voltage according to claim 1 or 2, wherein the transfer transistor is composed of a plurality of transfer transistors and switched during different clock cycles. The low-voltage charge pump circuit of claim 1 or 2, wherein the negative voltage transfer is performed two or more times during a period in which one repetition cycle is completed.

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