KR100624117B1 - An emission control driver and an organic electroluminescence display including the same - Google Patents

Abstract

An organic electroluminescent display using a tiling technique is disclosed. The organic electroluminescent display has a light emission control driver used for a system on panel (SOP). The light emission control driver includes a shift register including a plurality of flip-flops and a plurality of logic gates configured to perform an OR operation upon receiving an output signal of the shift register. Two output signals of the two adjacent flip-flops and two inverted output signals control the active load of the logic gate. In addition, the logic gate outputs an emission control signal through a logical sum operation of two output signals output from the two adjacent flip-flops. The flip-flop is made of a PMOS transistor.

Organic electroluminescent display, SOP (System On Panel), emission control driver

Description

Emission control driver and organic electroluminescent display including the same {EMISSION DRIVER AND ORGANIC ELECTROLUMINESCENT DISPLAY DEVICE HAVING THE SAME}

1 is a block diagram illustrating an organic light emitting display device using a tiling technique according to an exemplary embodiment of the present invention.

FIG. 2 is a block diagram illustrating in detail the exemplary small organic electroluminescent display shown in FIG. 1.

3 is a circuit diagram illustrating a representative pixel among a plurality of pixels of the pixel unit illustrated in FIG. 2.

FIG. 4 is a timing diagram for describing an operation of the pixel circuit shown in FIG. 3.

5 is a block diagram showing a light emission control driver of an organic EL display device according to an embodiment of the present invention.

FIG. 6 is a circuit diagram illustrating a representative flip-flop constituting a shift register of the light emission control driver shown in FIG. 5.

FIG. 7 is a circuit diagram illustrating in detail the inverter structure of the flip-flop illustrated in FIG. 6.

FIG. 8 is a circuit diagram illustrating in detail a representative logic gate among a plurality of logic gates constituting a logic operation unit of the light emission control driver shown in FIG. 5.

9 is a timing diagram of signals representing an operation of a light emission control driver according to an exemplary embodiment of the present invention.

* Description of main parts of drawing *

10 EL display panel 12 pixel portion

14: scan driver 16: light emission control driver

17: shift register 18: logic operation unit

20: data driver

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emission control driver and an organic light emitting display device including the same. The present invention relates to a light emitting display device.

The flat panel display has been researched and developed due to the advantages of reducing the weight and size of the display device using a cathode ray tube, and as a result, a liquid crystal display (LCD) and a field emission display (Field Emission Display) FED), plasma display panels (PDPs), and organic electroluminescent display devices (hereinafter referred to as organic EL display devices) have been developed and put into practical use. Among them, the PDP is possible to configure a large screen, but has a problem in that power consumption is low due to low luminous efficiency and brightness, and LCD has a problem in that power consumption is large because response speed is slow and light is emitted by a backlight.

On the other hand, the organic EL display device emits light using organic materials, and has a wider viewing angle, faster response speed, better contrast as a self-luminous device, and better visibility than an LCD. In addition, since the backlight is unnecessary, power consumption is low, and thickness and weight can be reduced.

However, the size of the EL display panel per glass substrate is limited due to the limitations in the manufacturing process when the organic EL display device constitutes an enlarged screen. In addition, in the case of a large screen, the fall of the yield when a defect arises in a part of a screen cannot be avoided, and securing of in-plane uniformity is also difficult.

A technique developed as one of the solutions to the organic EL display device, which is difficult to form a large screen as described above, is a tiling technique, which is a method of forming one large panel by bonding several small EL display panels.

Each small EL display panel is made up of a plurality of pixels displaying a predetermined image as in the prior art. A scan signal is applied by a scan driver to activate the plurality of pixels, and a corresponding data signal is applied by the data driver to the selected pixel. In addition, the emission control driver applies an emission control signal to each pixel in order to precisely program the data signal and control the emission time.

As described above, the scan driver, the data driver and the light emission control driver for applying various signals for driving the small EL display panel can be electrically connected to each of the small EL display panels in various ways.

For example, it may be mounted in the form of a chip or the like on a tape carrier package (TCP) that is bonded to and electrically connected to a small EL display panel. In addition, a flexible printed circuit (FPC) or a film (film) may be mounted in the form of a chip such as a chip on flexible board (chip), which is adhered to a small EL display panel and electrically connected thereto. on film). Alternatively, it may be directly mounted on the glass substrate of the small EL display panel, which is called a COG (chip on glass) method. Such a method is expensive because it is electrically connected to each driving unit separately designed, and there is a problem that it does not comply with the simplification trend of the module.

Therefore, in recent years, efforts have been made to build all systems in one panel by designing a pixel display unit, a scan / light emission control driver or / and a data driver inside the EL display panel. This is called a system on panel (SOP).

In the case of the large panel using tiling technology, it is easy to join the small panels because it is easy to join the small panels by making SOP type. The cost and effort of designing the circuit can be reduced.

However, in order to develop an SOP type display device as described above, various environments / conditions such as data or driving frequency and electron mobility of the scan / light emission control driver must be met inside the panel. Currently, since the data driver requires a high driving frequency, it is difficult to design inside the panel. Accordingly, the data driver is externally connected in the form of an integrated circuit using CMOS technology, and the scan driver and / or the light emission control driver are formed inside the panel.

Accordingly, there is a need for a circuit design in which a scan driver and a light emission control driver designed in the SOP type can be optimally driven inside the panel.

The technical problem to be achieved by the present invention is to design a new type of light emission control driver which is designed in the SOP type inside the EL display panel to generate a light emission control signal for controlling light emission of pixels.

An organic electroluminescent display device of the present invention for achieving the above object is a pixel portion having a plurality of pixels for displaying a predetermined image; A scan driver for applying a scan signal for sequentially selecting the plurality of pixels; A data driver for applying a data signal to the pixels selected by the scan signal; And a light emission control driver for applying a light emission control signal for controlling light emission of the plurality of pixels, wherein the light emission control driver receives an initiation pulse and generates an output signal in synchronization with a clock signal and a clock signal inverted. A shift register having a plurality of flip-flops; And receiving two output signals and two inverted output signals from two adjacent flip-flops to control an active load using the four signals, and generating an emission control signal through a logical sum operation of the two output signals. And a logic operation unit having a logic gate for output.

The object may also include a first flip-flop for receiving a start pulse and generating an output signal synchronized with a clock signal inverted from the clock signal; A second flip-flop for receiving an output signal of the first flip-flop and generating an output signal synchronized with the clock signal and the inverted clock signal; And receiving an output signal of the first flip-flop, an inverted output signal, an output signal of the second flip-flop, and an inverted output signal, controlling an active load using the four signals, and controlling the first flip-flop. A light emission control driving apparatus including a logic gate for outputting a light emission control signal through a logical sum operation of the output signal of the second flip-flop and the output signal of the second flip-flop.

The flip-flop may include a first transistor for sampling an input signal at a falling edge of the inverted clock signal; A first inverter for inverting the output signal of the first transistor; A second transistor for sampling an output signal of the first inverter at a falling edge of the clock signal; And a second inverter for inverting the output signal of the second transistor.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a large organic EL display device using a tiling technique according to an exemplary embodiment of the present invention.

Referring to FIG. 1, in a large organic EL display device using a tiling technique according to an exemplary embodiment of the present invention, a plurality of small organic EL display devices 100 are bonded to each other. In the case of FIG. 1, four small organic EL display devices 100 are joined in rows to form two columns, which may be joined in various sizes according to a designer.

The small organic EL display device 100 includes an EL display panel 10 capable of displaying an image and a data driver 20 for supplying an image data signal to the EL display panel 10.

Each of the EL display panels 10 has basically the same structure, and each edge surface is bonded with an adhesive to form one combined EL display panel. The adhesive uses an ultraviolet curable resin or a thermosetting resin such as an epoxy resin.

Each EL display panel 10 can be produced through the same manufacturing process as that of an EL display panel of a small organic light emitting display device conventionally used. Therefore, one large EL display panel is formed by attaching the same several EL display panels produced through the same manufacturing process.

The scan driver, the emission control driver and the thin film transistors of the plurality of pixels formed in the EL display panel have polysilicon as a channel of the thin film transistor for fast response speed and uniformity. In this case, the polysilicon is formed on the glass substrate, and then crystallized into polysilicon through a low temperature polysilicon (LTPS) process.

A plurality of transistors are formed by using polysilicon formed by the LTPS process, and the pixel unit composed of red, green, and blue subpixels and each of the pixels are selected in the EL display panel using the plurality of transistors, and light emission is performed. A scan driver and a light emission control driver for generating a signal for control are formed. The EL display panel 10 will be described later.

The plurality of data drivers 20 are designed as external integrated circuits (ICs) using CMOS forming technology and are electrically connected to the respective EL display panels 10. Electrical connection between one EL display panel 10 and data driver 20 is achieved through a metal pattern printed on the flexible film. That is, the output terminal of the data driver 20 is electrically connected to one end of the metal pattern, and the data line provided on the EL display panel 10 is electrically connected to the other end of the metal pattern. This is called a tape carrier package (TCP) method. Each data driver 20 supplies a data signal to the pixel portion of the EL display panel 10 through a plurality of conductive lines provided on the flexible film.

FIG. 2 is a block diagram showing in detail the representative small organic EL display device shown in FIG.

Referring to FIG. 2, the small organic EL display device 100 includes an EL display panel 10 and a data driver 20.

The EL display panel 10 is composed of a pixel portion 12, a scan driver 14, and a light emission control driver 16.

The pixel portion 12 includes a plurality of data lines D1 -Dm, a plurality of scan lines S1 -Sn, a plurality of emission control lines E1 -En, and a plurality of pixels P11 formed in areas where these lines cross each other. To Pnm).

The plurality of data lines D1 to Dm are electrically connected to the data driver 20 to extend in the vertical direction, and transmit corresponding data signals to the respective pixels.

In addition, although the plurality of scan lines S1 -Sn and the plurality of emission control lines E1 -En extend in the vertical direction like the data driver 20 unlike the conventional art, the same scans are performed on the pixels arranged in the horizontal direction. And a contact hole for each scan and emission control line S1 -Sn and E1 -En to transmit the emission control signal. Therefore, the metal wiring connected through the contact hole extends in the horizontal direction to transmit the scan and emission control signals to the pixels in the horizontal direction.

In each of the pixels P11 to Pnm, three subpixels of red, green, and blue are repeatedly arranged in rows and columns. Each of the red, green, and blue subpixels differs only from the organic material of the organic light emitting layer that actually emits light. Accordingly, each pixel emits red, green, and blue light with luminance corresponding to an applied data signal, and expresses one color by a combination of these three colors. A circuit configuration of each pixel will be described with reference to FIGS. 3 and 4.

3 is a circuit diagram illustrating a representative pixel among a plurality of pixels of the pixel unit illustrated in FIG. 2.

Referring to FIG. 3, the pixel circuit 18 includes a pixel driver 19 and an organic EL element OLED.

The pixel driver 19 includes a data line Dm, a previous scan line Sn-1, a current scan line Sn, a light emission control line En, a first power voltage line VDD, and a second power voltage line ( Vsus). Therefore, a driving current corresponding to the data signal Vdata signal from the data line Dm is supplied to the organic EL element OLED.

The organic EL element OLED is composed of an anode electrode, a cathode electrode and an organic light emitting layer. An anode electrode is connected to the pixel driver 19, and a cathode electrode is connected to a reference power supply voltage line VSS. Therefore, the organic EL element OLED receives the driving current supplied from the pixel driver 19 and emits light with the luminous luminance corresponding to the current amount.

The pixel driver 19 includes five transistors M1-M5 and two capacitors Cst and Cvth. The pixel driver 19 will be described in detail as follows.

The switching transistor M4 has a data line Dm connected to a source terminal, a scan line Sn connected to a gate terminal, and is turned on to a scan signal transmitted through the scan line Sn so that the data line is turned on. The data signal Vdata from Dm is transferred.

In the driving transistor M1, the first power voltage line VDD is connected to a source terminal to generate a driving current I _OLED corresponding to a voltage applied to the gate terminal.

The threshold voltage compensating transistor M2 is connected between the gate terminal and the drain terminal of the driving transistor M1, and is turned on by a scan signal applied to a gate terminal connected to the scan line Sn- 1 so that the driving transistor ( Compensate for the moon turn voltage of M1)

The capacitor Cvth is connected between the drain terminal of the switching transistor M4 and the gate terminal of the driving transistor M1 to store a voltage corresponding to the threshold voltage Vth of the driving transistor M1.

The capacitor Cst is connected between the first power voltage line VDD and one end of the capacitor and stores the data voltage Vdata transferred to the data line Dm.

The second power supply voltage applying transistor M3 has a source terminal connected to the second power supply voltage line Vsus, a drain terminal connected to a point where the capacitor Cvth and the capacitor Cst are connected, and applied to the gate terminal. The previous scan signal Sn-1 is turned on to apply the second power supply voltage Vsus to the connection point of the capacitor Cvth and the capacitor Cst.

The emission control transistor M5 is connected between the drain terminal of the driving transistor M1 and the anode electrode of the organic EL element OLED, and is turned on / off under the control of the emission control signal En applied to the gate terminal. By performing the operation to serve or block the driving current supplied from the driving transistor (M1) to the organic EL element (OLED).

Hereinafter, the operation of the pixel circuit 18 will be described with reference to a timing diagram.

FIG. 4 is a timing diagram for describing an operation of the pixel circuit shown in FIG. 3.

3 and 4, first, a low level previous scan signal Sn- 1 is applied to the pixel circuit 18, and a high level current scan signal Sn and a light emission control signal En are applied to the pixel circuit 18. When applied, the threshold voltage compensation transistor M2 and the second power supply voltage applying transistor M3 are turned on, and the remaining transistors M4 and M5 are turned off. Therefore, the driving transistor M1 is diode-connected to apply the voltage VDD-Vth [V] to one electrode B of the first capacitor Cvth, and the second power supply voltage applying transistor M3 is turned on so that the first capacitor is turned on. The voltage Vsus [V] is applied to the wiring pole A of Cvth. Therefore, the voltage of Vsus-VDD + Vth [V] is stored in the first capacitor Cvth.

Next, when the current scan signal Sn having a low level is applied to the pixel circuit 18 and the previous scan signal Sn-1 and the light emission control signal En having a high level are applied, the switching transistor M4. Only turns on. At this time, the data voltage Vdata from the data line Dm is applied to the other electrode A of the first capacitor Cvth through the switching transistor M4. Accordingly, the other electrode A of the first capacitor Cvth generates a voltage variation ΔV = Vsus-Vdata by a predetermined voltage difference, and accordingly, one electrode B of the first capacitor Cvth has the same amount. Will cause voltage fluctuations. Accordingly, the voltage applied to the first electrode B of the first capacitor and the gate terminal of the driving transistor M1 is VDD-Vth-ΔV = VDD-Vth-Vsus + Vdata [v].

Finally, when the previous scan signal Sn-1 and the current scan signal Sn of a high level are applied to the pixel circuit 18, and the emission control signal En of a low level is applied, the emission control transistor M5. ) Is only turned on. In this case, the driving current I _OLED output from the driving transistor M1 is expressed by Equation 1 below.

I _OLED = k (Vgs-Vth) ² = k {VDD- (VDD-Vth-Vsus + Vdata) -Vth} ²

= k (Vdata-Vsus) ²

Here, Vth is the threshold voltage of the driving transistor M1, and k is a constant.

As shown in Equation 1, the pixel circuit 18 shown in FIG. 3 may compensate for threshold voltage Vth and IR-drop due to the first power voltage VDD.

Referring back to FIG. 2, the scan driver 14 is formed between the data driver 20 and the pixel unit 12. This is because a plurality of EL display panels 10 are joined to form one large panel, so that each scan driver 14 must be formed on the same side as the data driver 20 (this is called 'uniaxial drive'). . The scan driver 14 is connected to a plurality of scan lines S1 -Sn, and sequentially selects the pixels P11 -Pnm by sequentially applying a scan signal to the pixel unit 12.

The emission control driver 16 is formed between the scan driver 14 and the pixel unit 12, and is connected to the plurality of emission control lines E1 -En to sequentially emit light control signals to the pixel unit 12. Is applied to control the emission time of each pixel P11-Pnm.

As described above, the data driver 20 supplies a data signal to the pixel portion 12 of the EL display panel 10 through a plurality of conductive lines provided on the flexible film.

The small organic EL display device 100 according to the embodiment of the present invention as described above includes an EL display panel 10 and a data driver 20, and the EL display panel 10 includes a pixel unit 12 and a scan driver. 14 and a light emission control driver 16, which will be described in detail below with reference to a preferred embodiment.

5 is a block diagram showing a light emission control driver of an organic EL display device according to an embodiment of the present invention.

Referring to FIG. 5, the emission control driver 16 includes a shift register for connecting a plurality of flip-flops FF1, FF2, FF3, FF4,... To shift the input signal by one clock period to output a signal. 17) and a logic operation unit 18 including a plurality of logic gates OR1, OR2, OR3, ... that receive the four output signals of the adjacent flip-flops to generate an emission control signal through a logical sum operation. .

The shift register 17 is composed of a plurality of flip-flops FF1, FF2, FF3, FF4, .... The first flip-flop FF1 receives the start pulse Vsp, the clock signal V _CLK , and the inverted clock signal V _CLKB to receive the start pulse Vsp at the falling edge of the clock signal V _CLK . Sampling is maintained for one clock period, and the output signal OUT1 and the inverted output signal OUTB1 are output.

A second flip-flop (FF2) is the first flip-flop (FF1) the output signal (OUT1) and the clock signal (V _CLK) and receives the inverted clock signal (V _CLKB) the clock signal (V _CLK) of After shifting for one period, the input signal is sampled at the next falling edge and maintained for one period of the clock CLK, and the output signal OUT2 and the inverted output signal OUTB2 are output.

Hereinafter, the third and fourth flip-flops FF3, FF4,..., Repeat the same operations as the first and second flip-flops FF1, FF2 to output shifted signals. Each flip-flop is basically the same configuration, which will be described in detail later with reference to the drawings.

The logic operation unit 18 includes a plurality of logic gates OR1, OR2, OR3,..., And is connected to the emission control line for each logic gate to apply an emission control signal to each pixel.

The first logic gate OR1 applies two output signals OUT1 and OUTB1 of the first flip-flop FF1 and two output signals OUT2 and OUTB2 of the second flip-flop FF2 as input signals. Receive. The first logic gate OR1 performs an OR operation on four input signals OUT1, OUTB1, OUT2, and OUTB2. Unlike the general logic gate, the first logic gate OR1 according to the present invention has a low level output signal OUT1 and OUT2 of the first and second flip-flops, and is inverted of the first and second flip-flops. The low level emission control signal E1 is output only when the output signals OUTB1 and OUTB2 are high level signals, and the high level emission control signal E1 is output at other levels.

Next, the second logic gate OR2 inputs two output signals OUT2 and OUTB2 of the second flip-flop FF2 and two output signals OUT3 and OUTB3 of the third flip-flop FF3. It is applied as a signal and performs the same logical sum operation as the first logic gate OR1 to output the second emission control signal E2.

As described above, the third logic gate OR3 to the nth logic gate ORn also perform the OR operation on the four input signals like the first and second logic gates OR1 and OR2 to perform respective emission control signals E3 to En. ) Each logic gate is basically the same configuration, which will be described in detail later with reference to the drawings.

As described above, the light emission control driver according to the exemplary embodiment of the present invention includes a shift register 17 and a logic operation unit 18, and two adjacent flip-flops FF1 and FF2 of the shift register 17. The light emission control signal E1 is generated by setting the connection relationship of one logic gate OR1 of the logic operation unit 18 to the basic light emission control driving circuit 16_1. The operation principle of the light emission control driver of FIG. 5 will be described in detail later with reference to each timing diagram.

FIG. 6 is a circuit diagram illustrating a representative flip-flop constituting a shift register of the light emission control driver shown in FIG. 5.

Referring to FIG. 6, the flip-flop FF1 includes two switching transistors M6 and M7 and two inverters INV1 and INV2. In detail, the flip-flop FF1 is controlled by the inverted clock signal CLKB, and the transistor M6 and the transistor for sampling the input signal IN at the falling edge of the inverted clock signal CLKB. The transistor M7 and the transistor M7 for sampling the output signal of the first inverter INV1 at the falling edge of the first inverter INV1 and the clock signal CLK for inverting the output signal of M6). And a second inverter INV2 for inverting the output signal. Here, the transistors M6 and M7 are PMOS transistors.

Therefore, when the input signal IN is applied to the transistor M6 and the inverted clock signal CLKB is converted to the falling edge, the transistor M6 samples the input signal IN to form the first inverter INV1. To pass. When the clock signal CLK is converted to the falling edge, the transistor M7 is turned on, and the first inverter INV1 inverts and outputs the sampled signal. The output signal OUTB of the first inverter INV1 transferred from the transistor M7 is inverted again by the second inverter INV2 and output.

As described above, the flip-flop FF1 according to the embodiment of the present invention may generate an output signal having a desired size using the input signal IN, the clock signal CLK, and the inverted clock signal CLKB. The input signal OUTB and the output signal OUT of the second inverter INV2 become the two input signals of the logic gate OR1 described above. In addition, the output signal OUT of the second inverter INV2 becomes the input signal of the next flip-flop FF2 and shifts the input signal by one clock period to output the two inputs of the logic gate OR1. Applied by signal. Accordingly, the input signals OUTB1 or OUTB2 from the input signals OUT1, OUTB1, OUT2, and OUTB2 of the four input logic gates are inputted to the input terminal of the second inverter INV2 of the respective flip-flops FF1 and FF2 without additional signals. Pull out the signal to use. Therefore, power consumption can be reduced by applying all of the input signals of the logic gates in the flip-flop without additional signals.

Hereinafter, the first and second inverters INV1 and INV2 used in the flip-flop FF1 will be described.

FIG. 7 is a circuit diagram illustrating in detail the inverter structure of the flip-flop illustrated in FIG. 6.

Since the first and second inverters INV1 and INV2 have the same structure, only the first inverter INV1 will be described for convenience of description.

Referring to FIG. 7, the inverter INV1 includes three PMOS transistors M8, M9, and M10.

The transistor M8 has a source terminal connected to the first power supply voltage VDD, a gate terminal connected to the output terminal of the transistor M6 of the flip-flop FF1, and a drain terminal connected to the output terminal out. The output terminal is connected to the input terminal of the transistor M7 of the flip-flop FF1. Accordingly, the transistor M8 performs an on / off operation according to the control of the input signal in transmitted from the transistor M6 to output or block the first power voltage VDD to an output terminal (out). . Here, the first power supply voltage VDD is a positive power supply voltage, for example, a voltage of 5 [V] is supplied.

The transistor M9 has a source terminal connected to the drain terminal and the output terminal out of the transistor M8, a drain terminal connected to the second power supply voltage VSS, and acts as an active load according to a voltage applied to the gate terminal. Play a role.

In addition, the transistor M10 is connected between the gate terminal and the drain terminal of the transistor M9, the gate terminal and the drain terminal are connected to act as a diode, and controls the gate voltage of the transistor M9. Here, the second power supply voltage VSS is a negative power supply voltage, for example, a voltage of −7 [V] is supplied. Accordingly, the transistor M9 is an active load and is always turned on according to the difference between the voltage applied to the source terminal and the voltage applied to the gate terminal. Here, the channel length L9 of the transistor M9 is greater than the channel length L8 of the transistor M8, and the channel width W9 of the transistor M9 is the transistor ( It is preferable to be smaller than the channel width W8 of M8). That is, when the transistor M8 is turned on, the turn-on resistance of the transistor M9 is much larger than the turn-on resistance of the transistor M8.

In addition, the inverter INV1 is connected between the source terminal and the gate terminal of the transistor M9, and when the transistor M10 is turned off, the voltage Vgs between the source and gate of the transistor M9 is turned off. It may further include a capacitor (Cst) for holding.

An operation principle of the inverter INV1 having the above configuration will be described.

First, when the input signal in of the low level (-7 [V]) is applied to the gate terminal of the transistor M8, the transistor M8 is turned on, and the transistors M9 and M10 are also turned on. However, the transistor M9 has a larger ON resistance than the transistor M8 so that the voltage at the output terminal is substantially the first power supply voltage VDD, that is, the high level voltage 5 [V]. Is output.

Next, when the input signal in of the high level 5 [V] is applied to the gate terminal of the transistor M8, the transistor M8 is turned off, and the transistors M9 and M10 are already turned on. It is in a state. Accordingly, the voltage at the output terminal (out) is gradually shifted from the previously outputted high level voltage 5 [V] to the low level. At this time, the transistor M10 is turned off so that the gate terminal of the transistor M9 is turned off. Float. Accordingly, the source-gate voltage Vgs of the transistor M9 maintains a constant voltage, and the output terminal out connected to the source terminal has a voltage of the second power supply voltage VSS, that is, a low level voltage (-7). [V]). At this time, the gate voltage of the transistor M9 also decreases from -7 [V] to -15 [V] as the voltage at the output terminal (out) is converted.

As described above, the flip-flop according to the present invention may output an output signal having a desired size by controlling the input signal sampled according to the state change of the clock signal CLK and the inverted clock signal CLKB. Accordingly, four output signals OUT1, OUTB1, OUT2, and OUTB2 of the neighboring flip-flops FF1 and FF2 are applied to the input terminal of the logic gate OR1, which will be described later.

Hereinafter, the logic gate OR1 to which the four output signals OUT1, OUTB1, OUT2, and OUTB2 of the neighboring flip-flops FF1 and FF2 are applied will be described in detail.

FIG. 8 is a circuit diagram illustrating in detail a representative logic gate among a plurality of logic gates constituting a logic operation unit of the light emission control driver shown in FIG. 5.

Referring to FIG. 8, the logic gate is connected to an input unit 31 that performs on / off operation according to two input signals IN1 and IN2 and the input unit 31, and two inverted input signals INB1. Output transistor for receiving the output of the first active load 32 having the transistor (M13) selectively diode-connected according to INB2 and the output of the input unit 31, and performing the on / off operation according to the received level ( And a second active load 33 having a transistor M17 connected to M18 and the output transistor M18 and selectively diode-connected according to two input signals IN1 and IN2.

In addition, the logic gate performs an on / off operation according to the two input signals IN1 and IN2 so that the current flowing through the first active load 32 when the two input signals IN1 and IN2 are low. The first capacitor C1 for maintaining the voltage between the switching unit 34 and the source of the transistor M13 and the gate to be cut off, and the second capacitor C2 for maintaining the voltage between the source and the gate of the transistor M17. More).

Furthermore, the logic gate is connected to both ends of the second capacitor C2 and performs an on / off operation according to an output signal of the input unit 31 so that the second active load when the output signal is low. The transistor M19 further includes a transistor M19 for blocking a current flowing in the current 33.

Here, the input signal IN1 and the inverted input signal INB1 are the output signal OUT1 and the inverted output signal OUTB1 of the flip-flop FF1, respectively, and the input signal IN2 and the inverted input signal ( INB2 is an output signal OUT2 and an inverted output signal OUTB2 of the flip-flop FF2, respectively.

In detail, the input unit 31 is connected to the positive power supply voltage Vpos, and is connected to the transistor M11 and the transistor M11 which perform on / off operations according to the level of the input signal IN1. The transistor M12 performs an on / off operation according to the level of the input signal IN2. Therefore, the input unit 31 is turned on only when the two input signals IN1 and IN2 are at the low level, and outputs the positive power supply voltage Vpos, and is turned off at other levels.

The first active load 32 is connected between the transistor M12 and a negative power supply voltage Vneg and diode-connected according to the level state of two inverted input signals INB1 and INB2. And two transistors M15_1 and M15_2 connected between the gate and the drain of the transistor M13 and performing on / off operations according to the level states of the two inverted input signals INB1 and INB2, respectively. . Accordingly, except when the level state of the two inverted input signals INB1 and INB2 is high level, the transistor M13 is diode-connected to sum the negative power supply voltage Vneg and the threshold voltage Vth _M13 . The voltage corresponding to is applied to the output terminal of the input unit 31.

The output transistor M18 is connected between the positive power supply voltage Vpos and the light emission control line E1, and a gate terminal is connected to an output terminal of the input unit 31 and the first active load 32 to gate the gate. The on / off operation is performed according to the voltage applied to the terminal. Therefore, when the voltage applied to the gate terminal is at the low level, the transistor M18 is turned on to transfer the positive power supply voltage Vpos to the light emission control line E1.

The second active load 33 is connected between the transistor M18 and a negative power supply voltage Vneg, and diode-connected transistor M17 according to the level state of two input signals IN1 and IN2. Two transistors M16_1 and M16_2 connected between the gate and the drain of the transistor M17 and performing on / off operations according to the level states of the two input signals IN1 and IN2, respectively. Therefore, only when the level of the two input signals IN1 and IN2 is at the low level, the transistor M17 is diode-connected to obtain a voltage corresponding to the sum of the negative power supply voltage Vneg and the threshold voltage Vth _M17 . It is applied to the light emission control line E1.

In addition, the switching unit 34 is connected between the source and the gate of the transistor M13 of the first active load 32 and performs an on / off operation according to the two input signals IN1 and IN2, respectively. The two transistors M14_1 and M14_2 are connected in series. The switching unit 34 makes the voltage difference Vgs _M13 between the source and the gate of the transistor _M13 to 0 [V] when the two input signals IN1 and IN2 are all at the low level. Cut off the current flowing at M13. Therefore, when the input unit 31 is turned on, the static current flowing through the first active load 32 may be blocked.

Further, the transistor M19 is connected between the source and the gate of the transistor M17 of the second active load 33 and performs an on / off operation according to the output signal of the first input unit 31. Accordingly, the transistor M19 makes the voltage difference Vgs _M17 between the source and the gate of the transistor M17 equal to 0 [V] when the output signal of the first input unit 31 is at a low level. Cut off the current flowing in M17). Therefore, when the transistor M18 is turned on, the static current flowing through the second active load 33 may be blocked.

Here, all the transistors constituting the logic gate are all composed of PMOS transistors. However, it will be apparent to those skilled in the art that the logic gate is configured as an NMOS transistor. In other words, if the PMOS transistor is replaced with an NMOS transistor, and the positive power supply voltage and the negative power supply voltage are changed, a logic gate composed of the NMOS transistor is designed.

The light emitting control signal E1 will be described according to the logic gate of the above configuration according to the level of the two input signals IN1 and IN2 and the two inverted input signals INB1 and INB2.

First, when the two input signals IN1 and IN2 are low level signals, and the two inverted input signals INB1 and INB2 are high level signals, the two transistors M11 and M11 of the input unit 31 are input. M12 is all turned on, and both transistors M14_1 and M14_2 of the switching unit 34 are also turned on. In addition, both transistors M16_1 and M16_2 of the second active load 33 are also turned on. However, the two transistors M15_1 and M15_2 of the first active load 32 are both turned off.

Therefore, the positive power supply voltage Vpos from the input unit 31 is applied to the gate terminal of the output transistor M18 and the transistor M19. At this time, the switching unit 34 is turned on to make the source-gate voltage Vgs _M13 of the transistor M13 of the first active load 32 to 0 [V]. Accordingly, the transistor M13 is turned off so that no static current flows through the active load 32. On the other hand, the output transistor M18 and the transistor M19 applied with the positive power supply voltage Vpos are turned off, and the light emission control signal is negative by the transistor M17 connected to the diode of the second active load 33. The low level signal is output as much as the sum of the threshold voltage Vth _M17 and the power supply voltage Vneg.

Next, when the input signal IN1 is high level, the input signal IN2 is low level, or the input signal IN1 is low level, and the input signal IN2 is high level, the state of the logic gate is as follows. same.

One of the two transistors M11 or M12 of the two transistors M11 and M12 of the input unit 31 is turned off and one of the two transistors M14_1 and M14_2 of the switching unit 34 is turned off. M14_1 or M14_2 are also turned off. In addition, one of the two transistors M16_1 and M16_2 of the second active load 33 is also turned off. However, one of the transistors M15_1 or M15_2 of the two transistors M15_1 and M15_2 connected in parallel with the first active load 32 is turned on.

Accordingly, the input unit 31 and the switching unit 34 are turned off, and the transistor M13 of the first active load 32 is diode-connected so that the voltage at the gate terminal of the output transistor M18 is a negative power supply voltage. It drops to the low level by adding the threshold voltage Vth _M13 to (Vpos). The output transistor M18 receiving the low level voltage is turned on and outputs a positive power supply voltage Vpos to the light emission control line E1. At this time, the transistor M19 is turned on to bring the source-gate voltage Vgs _M17 of the transistor M17 of the second active load 33 to 0 [V]. Accordingly, the transistor M17 is turned off so that no static current flows through the active load 33. As a result, a high level signal corresponding to the positive power supply voltage Vpos is output to the light emission control line E1.

In addition, it can be seen that when the two input signals IN1 and IN2 are both at the high level, the emission control signal E1 maintains the high level.

As described above, the logic gates constituting the logic operation unit 18 according to the embodiment of the present invention are four signals OUT1, OUTB1, OUT2, and OUTB2 output from the neighboring flip-flops FF1 and FF2 without additional signals. Is applied to control the active load of the logic gate using these four signals, and receives the two output signals OUT1 and OUT2 to perform a logical sum operation to generate a light emission control signal E1 of a desired type. can do. In this case, when the two input signals IN1 and IN2 are at the low level, static current flowing through the active loads 32 and 33 of the logic gate may be blocked, and the output signal of the input unit 31 may be When the level is low, the static current flowing through the second active load 33 may be blocked.

9 is a timing diagram of signals indicating an operation of a light emission control driver according to an exemplary embodiment of the present invention.

Referring to FIG. 9, a shift register composed of a plurality of flip-flops FF1-FFn + 1 receives a clock signal CLK and an inverted clock signal CLKB in common, and receives an output signal of a previous flip-flop as an input signal. Licensed as

First, when the start pulse SP is applied to the input of the first flip-flop FF1, the first flip-flop FF1 is at the low level of the output signal OUT1 and the low level at the falling edge of the clock signal CLK. The inverted output signal OUTB1 of is outputted for one clock cycle.

Next, when the output signal OUT1 of the first flip-flop FF1 is applied to the input of the second flip-flop FF2, the second flip-flop FF2 at the second falling edge of the clock signal CLK. Outputs the high level output signal OUT2 and the low level inverted output signal OUTB2 for one clock period.

By repeating the above operation, when the output signal OUTn of the first flip-flop FFn is applied to the input of the n + 1 flip-flop FFn + 1, n + 1 of the clock signal CLK. At the first falling edge, the n + 1th flip-flop FFn + 1 outputs the high level output signal OUTn + 1 and the low level inverted output signal OUTBn + 1 for one clock cycle.

As described above, the shift register according to the present invention outputs two signals OUT and OUTB which are shifted every one clock cycle.

In addition, a logic operation unit including a plurality of logic gates OR1-ORn receives the output signals of the flip-flops FF1-FFn + 1 to perform a logical sum operation to output an emission control signal.

First, the first logic gate OR1 receives two output signals OUT1 and OUTB1 of the first flip-flop FF1 and two output signals OUT2 and OUTB2 of the second flip-flop FF2 as inputs. Licensed. Therefore, only when the first output signal OUT1 and the second output signal OUT2 are at the low level, and the inverted first output signal OUTB1 and the inverted second output signal OUTB2 are at the high level. The logic gate OR1 outputs a low level light emission control signal E1, and in other levels, the logic gate OR1 outputs a high level light emission control signal E1.

Next, the second logic gate OR2 inputs two output signals OUT2 and OUTB2 of the second flip-flop FF2 and two output signals OUT3 and OUTB3 of the third flip-flop FF3. Licensed as Therefore, only when the second output signal OUT2 and the third output signal OUT3 are low level, and the inverted second output signal OUTB2 and the inverted third output signal OUTB3 are high level. The logic gate OR2 outputs a low level light emission control signal E2, and in other levels, the logic gate OR2 outputs a high level light emission control signal E2. The second emission control signal E2 is shifted and output by a clock cycle from the first emission control signal E1.

By repeating the above operation, the n-th logic gate ORn finally receives two output signals OUTn and OUTBn of the nth flip-flop FFn and 2 of the n + 1th flip-flop FFn + 1. Output signals OUTn + 1 and OUTBn + 1 are applied as inputs. Accordingly, the nth output signal OUTn and the n + 1th output signal OUTn + 1 are at a low level, and the inverted nth output signal OUTBn and the inverted n + 1th output signal OUTBn + 1 are Only at a high level, the nth logic gate ORn outputs a low level light emission control signal En, and in other levels, the nth logic gate ORn outputs a high level light emission control signal En.

The light emission control driver of the organic EL display device according to the embodiment of the present invention implements a system on panel (SOP) by forming a plurality of flip-flops and a plurality of logic gates directly composed of PMOS transistors inside the panel. There is an advantage of being easy.

In addition, by using four outputs of adjacent flip-flops of the present invention as inputs of a logic gate, power consumption can be reduced by using the outputs of the flip-flops without additional signals.

Furthermore, by using the four-input logic gate of the present invention, it is possible to cut off the static current generated when the input signal is low, thereby reducing the power consumption according to the leakage current.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

As described above, according to the present invention, it is advantageous to implement a system on panel (SOP) by forming a plurality of flip-flops and a plurality of logic gates composed of PMOS transistors directly inside the panel.

In addition, by using four outputs of adjacent flip-flops of the present invention as inputs of a logic gate, power consumption can be reduced by using the outputs of the flip-flops without additional signals.

Furthermore, by using the four-input logic gate of the present invention, it is possible to cut off the static current generated when the input signal is low, thereby reducing the power consumption according to the leakage current.

Accordingly, the present invention has an effect of providing an organic light emitting display device that can provide an optimal light emission control driver for SOPs, thereby minimizing power consumption.

Claims (17)

A pixel unit having a plurality of pixels for displaying a predetermined image; A scan driver for applying a scan signal for sequentially selecting the plurality of pixels; A data driver for applying a data signal to the pixels selected by the scan signal; And A light emission control driver configured to apply a light emission control signal for controlling light emission of the plurality of pixels, The light emission control driver, A shift register which receives a start pulse and has a plurality of flip-flops for generating an output signal in synchronization with a clock signal and an inverted clock signal; And Receives two output signals and two inverted output signals from two adjacent flip-flops to control an active load using the four signals, and outputs a light emission control signal through a logical sum operation of the two output signals. An organic electroluminescent display device comprising a logic operation unit having a logic gate for controlling the same. The method of claim 1, Each of the flip-flops, A first transistor for sampling an input signal at a falling edge of the inverted clock signal; A first inverter for inverting the output signal of the first transistor; A second transistor for sampling an output signal of the first inverter at a falling edge of the clock signal; And And a second inverter for inverting the output signal of the second transistor. The method of claim 2, And wherein each adjacent flip-flop applies an output signal of the second transistor and an output signal of the second inverter to the logic gate. The method of claim 3, wherein Each said inverter, A third transistor coupled between a positive power supply voltage and an output terminal and configured to perform an on / off operation according to a signal transmitted through the first or second transistor of the flip-flop; And And a fourth transistor connected between a negative power supply voltage and the output terminal and configured to control an output current amount according to on / off of the third transistor. The method of claim 4, wherein Each said inverter, And a fifth transistor connected between the gate terminal and the drain terminal of the fourth transistor and controlling the gate voltage of the fourth transistor. The method of claim 5, wherein The turn-on resistance of the third transistor is less than the turn-on resistance of the fourth transistor. The method of claim 6, Each said inverter, And a capacitor connected between the source terminal and the gate terminal of the fourth transistor and maintaining a voltage between the source and gate of the fourth transistor when the fifth transistor is turned off. Electroluminescent display. The method of claim 7, wherein And the first to fifth transistors are PMOS transistors. The method of claim 1, And the pixel portion, the scan driver, the data driver, and the light emission control driver are formed on one substrate. The method of claim 1, The organic electroluminescent display device is characterized in that a plurality of organic electroluminescent display devices are combined in a tile form to display a single image. A first flip-flop for receiving a start pulse and generating an output signal synchronized with a clock signal inverted from the clock signal; A second flip-flop for receiving an output signal of the first flip-flop and generating an output signal synchronized with the clock signal and the inverted clock signal; And The output signal of the first flip-flop and the inverted output signal, the output signal of the second flip-flop and the inverted output signal are input, and an active load is controlled using the four signals. And a logic gate for outputting a light emission control signal through a logical sum operation of an output signal and an output signal of the second flip-flop. The method of claim 11, Each of the flip-flops, A first transistor for sampling an input signal at a falling edge of the inverted clock signal; A first inverter for inverting the output signal of the first transistor; A second transistor for sampling an output signal of the first inverter at a falling edge of the clock signal; And And a second inverter for inverting the output signal of the second transistor. The method of claim 12, Each said inverter, A third transistor coupled between a positive power supply voltage and an output terminal and configured to perform an on / off operation according to a signal transmitted through the first or second transistor of the flip-flop; And And a fourth transistor connected between a negative power supply voltage and the output terminal and configured to control an output current amount according to on / off of the third transistor. The method of claim 13, Each said inverter, And a fifth transistor connected between the gate terminal and the drain terminal of the fourth transistor and configured to control the gate voltage of the fourth transistor. The method of claim 14, And a turn-on resistance of the third transistor is less than that of the fourth transistor. The method of claim 15, Each said inverter, And a capacitor connected between the source terminal and the gate terminal of the fourth transistor, and configured to maintain a voltage between the source and gate of the fourth transistor when the fifth transistor is turned off. Control drive. The method of claim 16, And the first to fifth transistors are PMOS transistors.

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