KR100620891B1 - Light emitting device and manufacturing method - Google Patents

Abstract

The present invention relates to a light emitting device in which a plurality of cells are arrayed and a method of manufacturing the same. A thermally conductive substrate, a buffer layer formed on the substrate, a plurality of light emitting cells formed on the buffer layer, and a plurality of light emitting cells are connected in series. Provided are a light emitting device including a plurality of metal wires and a method of manufacturing the same. By using a substrate having excellent thermal conductivity, a high output can be achieved, and an insulating buffer layer can be formed on the substrate to easily insulate the substrate from the light emitting cells, so that a high voltage light emitting cell array insulated from each other without leakage of current between the cells can be obtained. It can be easily formed.

Light emitting cell, light emitting element, series connection, buffer layer, metallization, rectifying bridge, light emitting device for lighting

Description

Light-Emitting Device and Manufacturing Method Thereof {LUMINOUS ELEMENT AND METHOD OF MANUFACTURING THE SAME}

1 is a cross-sectional view illustrating a light emitting device according to an embodiment of the present invention.

2A to 2E are cross-sectional views illustrating a method of manufacturing a light emitting device according to an embodiment of the present invention.

3 is a cross-sectional view for describing a method of manufacturing a light emitting device according to another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

110 substrate 120 buffer layer

130 and 150: semiconductor layer 140: active layer

160, 165: ohmic metal layer 170: metal wiring

The present invention relates to a light emitting device and a method of manufacturing the same, and a light emitting device capable of operating under a high current by a plurality of light emitting cells are arranged on a thermally conductive substrate and a method for manufacturing the same.

A light emitting diode refers to a device that generates a small number of carriers (electrons or holes) by using a p-n junction structure of a semiconductor, and emits predetermined light by recombination thereof. Such light emitting diodes are used as display devices and backlights, and active research is being conducted to apply them to general lighting applications.

Light emitting diodes consume less power and have a longer lifetime than conventional light bulbs or fluorescent lamps. That is, the power consumption of the light emitting diode is only a few to tens of times compared to the conventional lighting device, the lifetime is several to several tens of times, superior to the conventional bulb or fluorescent lamp in terms of power consumption and durability.

Such light emitting diodes are generally formed by epitaxially growing and patterning a nitride semiconductor on a sapphire substrate and then electrically connecting them. However, since the sapphire substrate has a relatively low thermal conductivity, when the current is increased to obtain a high output, heat emission is not smooth and the maximum light output level is inferior. In order to overcome this problem, a flip chip structure is applied. A flip chip is a light emitting chip that can bond an epi layer portion onto a substrate of a material having excellent thermal conductivity, such as a submount, and is die bonded on the submount. However, when die-bonding flip chips, defects occur in the bonding portion due to the difference in thermal expansion between the adhesive material used for bonding and the epi layer and the submount, and the flip chips are separated from the submount substrate. There is a problem.

Accordingly, it is an object of the present invention to provide a light emitting device capable of achieving high output by effectively dissipating heat generated when high current is applied and a method of manufacturing the same.

Another object of the present invention is to provide a light emitting device in which a plurality of light emitting cells are connected in series in a single chip, and a method of manufacturing the light emitting device and a method of manufacturing the light emitting device capable of preventing leakage current that may occur in the plurality of light emitting cells. To provide.

Still another object of the present invention is to provide a light emitting device capable of electrically connecting a plurality of light emitting cells at a wafer level, and to simplify a manufacturing process of a light emitting lamp and the like and a method of manufacturing the same.

In order to achieve the above object, the present invention provides a light emitting device and a manufacturing method of a plurality of light emitting cells are arranged. A light emitting device according to an aspect of the present invention includes a thermally conductive substrate, a buffer layer formed on the substrate, a plurality of light emitting cells formed on the buffer layer, and a plurality of metal wirings connecting the plurality of light emitting cells in series. Accordingly, the light emitting device according to the present invention can promote heat release through the thermally conductive substrate, thereby achieving high output.

The thermally conductive substrate may be silicon carbide (SiC), and the buffer layer may be a semi-insulating (SI) gallium nitride (GaN) layer having excellent insulation and excellent thermal conductivity. In addition, a semi-insulating SiC layer may be positioned between the SiC substrate and the semi-insulating GaN layer to reinforce the insulation of the buffer layer.

According to another aspect of the present invention, a method of manufacturing a light emitting device includes preparing a thermally conductive substrate. An insulating buffer layer is formed on the thermally conductive substrate, and an N-type semiconductor layer, an active layer, and a P-type semiconductor layer are sequentially formed on the buffer layer. Thereafter, the N-type semiconductor layer, the active layer and the P-type semiconductor layer are patterned to form a plurality of light emitting cells. At this time, a portion of the N-type semiconductor layer of each light emitting cell is exposed. Thereafter, a plurality of metal wires are formed to connect the exposed N-type semiconductor layers of each light emitting cell and the P-type semiconductor layers of adjacent light emitting cells in series.

After a portion of the N-type semiconductor layer is exposed, an ohmic metal layer may be formed on the P-type semiconductor layer and the exposed N-type semiconductor layer.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various forms, and the present embodiments are only provided to make the disclosure of the present invention complete and to those skilled in the art. It is provided for complete information. Like numbers refer to like elements in the figures.

1 is a cross-sectional view for describing a light emitting device in which light emitting cells are arranged according to an embodiment of the present invention.

Referring to FIG. 1, the light emitting device of the present invention includes a substrate 110 having excellent thermal conductivity, a buffer layer 120 formed on the substrate 110, and a plurality of light emitting cells 100-patterned on the buffer layer 120. 1 to 100-n) and a plurality of metal wires 170-1 to 170-n for connecting the plurality of light emitting cells 100-1 to 100-n in series.

As the substrate 110, a material film having a relatively excellent thermal conductivity is used as the sapphire substrate. In this embodiment, in particular, a SiC single crystal substrate is used as the substrate 110.

The buffer layer 120 is formed of an insulating material film to insulate the upper light emitting cell from the lower substrate 110. In this embodiment, a semi-insulating gallium nitride (GaN) layer is used as the buffer layer 120. In addition, as shown in FIG. 3, a semi-insulating SiC layer (115 in FIG. 3) may be added between the substrate and the buffer layer to reinforce the insulation of the buffer layer.

In the case of using an N-type SiC substrate, a semi-insulating GaN substrate is grown on the substrate 110 to block conductivity through the semi-insulating GaN layer, which is an insulating buffer layer, so that the conductivity of the substrate does not fall over the light emitting cell structure. In the case of using a semi-insulating SiC substrate, since the substrate 110 itself is insulating, a separate insulating buffer layer is not required, but a semi-insulating GaN layer may be used as the buffer layer 120 for the purpose of reinforcing the insulating performance of the substrate.

Each of the plurality of light emitting cells 100-1 to 100-n includes a nitride semiconductor layer PN bonded. The light emitting cell 100 includes an N-type semiconductor layer 130, an active layer 140, and a P-type semiconductor layer 150. The PN junction region of the light emitting cell 100 may be vertically exposed or horizontally exposed.

In this embodiment, the N-type semiconductor layer 130, an active layer 140 formed in a predetermined region on the N-type semiconductor layer 130, and a P-type semiconductor layer 150 formed on the active layer 140 are included. In addition, the ohmic metal layers 160 and 165 formed on the N-type semiconductor layer 130 and the P-type semiconductor layer 150 may be further included. Further, N-type semiconductor layer 130 or the P-type semiconductor layer on the N ⁺⁺ 150 type ^{1x 10 19 ~ 1 x 10 22} / cm high-concentration semiconductor layer tunneling or semi-metal (semi-metal) of the ^third layer is the concentration And a transparent electrode layer (not shown) may be further formed thereon.

The N-type semiconductor layer 130 is a layer in which electrons are generated, and includes an N-type compound semiconductor layer and an N-type cladding layer. In this case, the N-type semiconductor layer 130 uses a gallium nitride (GaN) film into which N-type impurities are implanted, but is not limited thereto. A material layer having various semiconductor properties may be used. In this embodiment, an N-type semiconductor layer 130 including an N _- type Al _x Ga _1-x N (0 ≦ _x ≦ 1) film is formed.

The P-type semiconductor layer 150 is a layer in which holes are generated, and includes a P-type cladding layer and a P-type compound semiconductor layer. At this time, the P-type semiconductor layer 150 also uses a gallium nitride film implanted with P-type impurities. In this embodiment, a P-type semiconductor layer 150 including a P _- type Al _x Ga _1-x N (0 ≦ _x ≦ 1) film is formed. In addition, an InGaN film may be used as the semiconductor layer film. In addition, the N-type semiconductor layer 130 and the P-type semiconductor layer 150 may be formed of a multilayer film. In the above, silicon (Si) is used as the N-type impurity, zinc (Zn) is used in the case of InGaAlP, and magnesium (Mg) is used in the case of nitride.

The active layer 140 is a region where a predetermined band gap and a quantum well are made to recombine electrons and holes, and includes InGaN. In addition, the emission wavelength generated by the combination of electrons and holes is changed according to the type of material constituting the active layer 140. Therefore, it is preferable to adjust the semiconductor material included in the active layer 140 according to the target wavelength. In this embodiment, a multilayer film in which a quantum well layer and a barrier layer are repeatedly formed on an N-type Al _x Ga _1-x N (0 ≦ _x ≦ ₁ ) layer is used as the active layer 140. As the barrier layer and the well layer, binary compounds such as GaN, InN, and AlN may be used, and ternary compounds In _x Ga _1-x N (0 ≦ _x ≦ ₁ ) and Al _x Ga _1-x N (0 ≤ _x ≤ 1) may be used, and the quaternary compound Al _x In _y Ga _1-xy N (0 ≦ x + y ≦ 1) may be used. Of course, the N-type semiconductor layer 130 and the P-type semiconductor layer 150 may be formed by injecting predetermined impurities into the two- to four-membered compounds.

In the present invention, the light emitting cells of the above-described structure are connected in series via metal wiring on the buffer layer.

At this time, in this embodiment, the number of light emitting cells 100-1 to 100-n in which AC driving (lighting voltage) can be connected is connected in series. That is, according to the present invention, the number of light emitting cells 100 connected in series may vary according to the voltage / current for driving the single light emitting cell 100 and the AC driving voltage applied to the light emitting device. Preferably, 10 to 1000 cells are connected in series. More preferably, it is effective to connect 30 to 70 cells in series. For example, in a 220V AC drive, a light emitting device is manufactured by connecting 66 to 67 unit light emitting diode cells for 3.3V in series with a constant driving current. In addition, in the 110V AC driving, 33 to 34 unit light emitting diode cells for 3.3V are connected in series to a constant driving current to manufacture a light emitting device.

For example, as shown in FIG. 1, in the light emitting device in which the first to nth light emitting cells 100-1 to 100-n are connected in series, the P-type semiconductor layer 150 of the first light emitting cell 100-1 is provided. A P-type pad (not shown) is formed on the N-type semiconductor layer 130 of the first light emitting cell 100-1 and the P-type semiconductor layer 150 of the second light emitting cell 100-2. 1 is connected via the metal wire 170-1.

In addition, the N-type semiconductor layer 130 of the second light emitting cell 100-2 and the P-type semiconductor layer (not shown) of the third light emitting cell (not shown) are connected through the second metal wiring 170-2. do. The n-type semiconductor layer (not shown) of the n-2 th light emitting cell (not shown) and the P-type semiconductor layer 150 of the n-1 th light emitting cell (100-n-1) are n-th metal wiring. An N-type semiconductor layer 130 of the n-th light emitting cell 100-n-1 and a P-type semiconductor layer of the n-th light emitting cell 100-n 150 is connected via an n-th metal wiring 170-n-1. In addition, an N-type pad (not shown) is formed on the N-type semiconductor layer 130 of the n-th light emitting cell 100-n.

In addition, the above-described light emitting device may be formed with a rectifying first to fourth diode (not shown) for rectifying the external AC voltage. The first to fourth diodes are arranged in the form of a rectifying bridge. Rectifying nodes between the first to fourth diodes may be connected to the N-type pads and the P-type pads of the light emitting cells, respectively. Light emitting cells may be used as the first to fourth diodes.

Hereinafter, a method of manufacturing a light emitting device in which the aforementioned plurality of light emitting cells are connected in series will be described.

2A to 2E are cross-sectional views illustrating a method of manufacturing a light emitting device according to the present invention.

Referring to FIG. 2A, the buffer layer 120 is formed on the substrate 110 having excellent thermal conductivity. The buffer layer 120 is formed through chemical vapor deposition (CVD) and physical vapor deposition (PVD) methods and various epitaxy layer forming methods using the same.

A semi-insulating GaN layer is used as the buffer layer 120. In addition, to reinforce the insulation of the buffer layer, as shown in FIG. 3, a semi-insulating SiC layer 115 may be positioned between the substrate 110 and the semi-insulating GaN 120 layer. In the case of using an N-type SiC substrate, a semi-insulating GaN layer is grown thereon to block conductivity with the semi-insulating GaN layer, which is an insulating buffer layer, so that the conductive characteristics of the substrate 110 do not fall below the light emitting cell structure. In the case of using a semi-insulating SiC substrate, since the substrate itself is insulative, a separate insulating buffer layer is not required, but a semi-insulating GaN layer may be added to reinforce the insulating performance of the substrate.

At this time, the buffer layer 120 is formed to a thickness of 0.001 to 50㎛.

Referring to FIG. 2B, the N-type semiconductor layer 130, the active layer 140, and the P-type semiconductor layer 150 are sequentially formed on the buffer layer 120. The layer is also formed through various thin film formation methods similar to those of the buffer layer 120. The N-type semiconductor layer 130, the active layer 140, and the P-type semiconductor layer 150 may be formed in multiple layers. On the N-type semiconductor layer 130 or the P-type semiconductor layer 150, a high-concentration semiconductor tunneling layer or a semimetal layer having a concentration of N ⁺⁺ type 1x 10 ¹⁹ to 1 x 10 ²² / cm ³ is formed, and a transparent electrode layer May be further formed.

Referring to FIG. 2C, a portion of the P-type semiconductor layer 150, the active layer 140, and the N-type semiconductor layer 130 is removed through a patterning process to form individual light emitting cells.

To this end, a photoresist film is coated on the P-type semiconductor layer 150 and then a photoresist pattern (not shown) is formed through a photolithography process. The photoresist pattern is formed in a shape of opening a region between the light emitting cells. The P-type semiconductor layer 150, the active layer 140, and the N-type semiconductor layer 130 are etched by performing an etching process using the photoresist pattern as an etching mask. n). Thereafter, the photoresist pattern is removed through a predetermined strip process. Instead of the photosensitive film pattern, various barrier films are possible.

 In the present exemplary embodiment, since the lower buffer layer 120 acts as an etch stop layer during the etching of the P-type semiconductor layer 150, the active layer 140, and the N-type semiconductor layer 130, effective etching may be performed. In this case, a portion of the lower buffer layer 120 may also be removed. In addition, the buffer layer 120 may be etched. As a result, the individual light emitting cells 100-1 to 100-n can be electrically isolated from each other. In addition, since the distance between the light emitting cells 100-1 to 100-n can be reduced, the size of the device can be reduced.

Referring to FIG. 2D, a portion of the N-type semiconductor layer 130 is exposed by removing a portion of the P-type semiconductor layer 150 and the active layer 140 of each of the light emitting cells 100-1 to 100-n.

To this end, a photoresist pattern (not shown) is formed on the entire structure to open a portion of the patterned P-type semiconductor layer 150. An etching process using the photoresist pattern as an etching mask is performed to etch the P-type semiconductor layer 150 and the active layer 140. Thereafter, the photoresist pattern is removed.

The etching process used in the patterning process may be performed by a wet or dry etching process, for example, it is effective to perform dry etching using plasma.

Referring to FIG. 2E, the P-type ohmic metal layer 160 and the N-type ohmic metal layer 165 are formed on the P-type semiconductor layer 150 and the N-type semiconductor layer 130, respectively. Thereafter, the N-type ohmic metal layer 165 and the P-type ohmic metal layer 160 of the adjacent light emitting cells are connected by metal wires 170-1 to 170-n-1.

The ohmic metal layers 160 and 165 may also be formed by performing a metal deposition process after opening only the region where the ohmic metal layers 160 and 165 are to be formed using the photoresist pattern (not shown). In addition, the P-type ohmic metal layer 160 and the N-type ohmic metal layer 165 may be formed at the same time, or may be formed separately. At least one of Pb, Sn, Au, Ge, Cu, Bi, Cd, Zn, Ag, Ni, and Ti is used as the ohmic metal layers 160 and 165.

Subsequently, the N-type ohmic metal layer 165 and the P-type ohmic metal layer 160 of the adjacent light emitting cells 100-1 to 100-n are formed through a predetermined bridge process or step cover process. Conductive metal wirings 170-1 to 170-n-1 for electrically connecting are formed.

 The bridge process is also called an air bridge process, and this process will be briefly described. First, after forming a photoresist film on a substrate on which the light emitting cells are formed, a first photoresist film having an opening for exposing the ohmic metal layers 160 and 165 on the N-type semiconductor layer and the P-type semiconductor layer exposed using an exposure technique. Form a pattern. Thereafter, the metal material layer is thinly formed by using an electron beam evaporation technique. The metal material layer is formed on the entire surface of the opening and the photoresist pattern. Subsequently, a second photoresist pattern is formed on the photoresist pattern to expose regions between adjacent light emitting cells to be connected and the metal layer of the openings. Thereafter, gold and the like are formed using a plating technique, and then the first and second photoresist patterns are removed with a solution such as a solvent. As a result, only wires connecting adjacent light emitting cells remain, and all other metal material layers and photoresist patterns are removed, so that the wires connect the light emitting cells in a bridge form.

Meanwhile, the step cover process includes forming an insulating layer on a substrate having light emitting cells. The insulating layer is patterned using photolithography and etching techniques to form openings that expose the ohmic metal layers 160 and 165 on the P-type semiconductor layer and the N-type semiconductor layer. Subsequently, an electron beam deposition technique or the like is used to form a metal layer filling the opening and covering the insulating layer. Thereafter, the metal layer is patterned using photolithography and etching techniques to form interconnects that connect adjacent light emitting cells. Such a step cover process is possible in various modifications. Using the step cover process, the wiring is supported by the insulating layer, thereby increasing the reliability of the wiring.

Meanwhile, P-type pads and N-type pads are formed in the light emitting cells 100-1 and 100-n positioned at both ends, respectively, for electrical connection with the outside. The rectifier bridge diode can be connected to the P-type pad and the N-type pad, respectively, or a separate conductive wiring can be connected to the P-type pad and the N-type pad.

The manufacturing of the light emitting device of the present invention described above is not limited thereto, and may be changed or added according to various processes and manufacturing method characteristics and convenience of the process.

In the above-described embodiment, although the light emitting cells are illustrated as being arranged in a row, they may be arranged in a matrix form on a plane, and in this case, the light emitting cells are connected to each other in series.

As described above, the present invention can provide a light emitting device in which a plurality of light emitting cells are connected in series in a single chip, thereby manufacturing a light emitting device that can be used for general lighting, and effectively High output can be achieved.

In addition, it is possible to provide a light emitting device capable of effectively blocking the conductive characteristics of the substrate at the wafer level through the insulating buffer layer to emit light without leakage of current at high voltage.

In addition, since a plurality of light emitting cells are formed in a batch semiconductor process on the substrate at the wafer level, it is possible to simplify the manufacturing process of the light emitting device for lighting, to reduce the defect rate generated when manufacturing the light emitting device for lighting, and to mass produce the light emitting device for lighting. Can be.

Claims (7)

A thermally conductive substrate having a higher thermal conductivity than the sapphire substrate; An insulating buffer layer formed on the substrate; A plurality of light emitting cells formed on the buffer layer; And A light emitting device comprising a plurality of metal wires for connecting the plurality of light emitting cells in series. The method according to claim 1, Wherein the thermally conductive substrate is N-type silicon carbide or semi-insulated silicon carbide. The method according to claim 2, And the buffer layer is a semi-insulating gallium nitride layer. The method according to claim 3, The thermally conductive substrate is N-type silicon carbide, And a semi-insulating silicon carbide layer interposed between the N-type silicon carbide substrate and the semi-insulating buffer layer. The method according to claim 1, The thickness of the buffer layer is a light emitting device, characterized in that 0.001㎛ 50㎛. Prepare a thermally conductive substrate having a higher thermal conductivity than the sapphire substrate, Forming an insulating buffer layer on the thermally conductive substrate, Sequentially forming an N-type semiconductor layer, an active layer, and a P-type semiconductor layer on the buffer layer, Patterning the N-type semiconductor layer, the active layer, and the P-type semiconductor layer to form a plurality of light emitting cells each of which a portion of the N-type semiconductor layer is exposed; And forming a plurality of metal wirings connected in series between the exposed N-type semiconductor layers of each light emitting cell and the P-type semiconductor layers of adjacent light emitting cells. The method according to claim 6, The thermally conductive substrate is a light emitting device, characterized in that the N-type silicon carbide or semi-insulating silicon carbide.

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