KR100618706B1 - Well Bias Voltage Generators for Transistors - Google Patents

Abstract

There is provided a well bias voltage generator for a transistor that outputs a well bias voltage that varies with ambient temperature changes.

The provided well bias voltage generator for a transistor includes a reference voltage generator for generating a reference voltage as a function of temperature, a level detector for receiving a reference voltage generated from the reference voltage generator, and a pulse of a predetermined period by receiving an output signal of the level detector. An oscillator for generating a; and a pump for receiving the pulse generated from the oscillator to generate a well bias voltage applied to the well of the transistor.

Description

Well bias voltage generator for transistors

1A and 1B illustrate threshold voltages of transistors.

2A illustrates a back bias voltage generator capable of adjusting the back bias voltage of a transistor in response to temperature variations.

FIG. 2B is an example of the reference voltage generator shown in FIG. 2A.

2C is a graph of temperature characteristics of FIG. 2B.

3A, 3B, 3C, and 3D are diagrams showing threshold voltage characteristics of transistors.

4 is an experimental result using the circuit proposed in the present invention.

The present invention relates to a well bias voltage generator for a transistor, and more particularly, to a well bias voltage generator for a transistor for outputting a well bias voltage that varies with ambient temperature change.

Recently, due to the development of the manufacturing technology of semiconductor devices, the size of semiconductor devices is decreasing and the speed is increasing. Therefore, operating characteristics of the semiconductor device are more sensitively affected by changes in voltage, temperature, and process variables.

In general, changes in process parameters can be minimized by careful control of applied equipment, applied process recipes, and photomasks.

However, the operating characteristics of the semiconductor device according to the voltage and the temperature change are greatly affected by the specification of the product and the type of circuit implemented in the semiconductor device.

For example, when the size of the transistor integrated in the semiconductor device is reduced due to the high integration of the semiconductor device, the operating characteristics of the transistor are greatly affected by changes in the ambient temperature. Among them, the change of the threshold voltage which is directly related to the operation of the transistor is very important.

The general characteristics of these threshold voltages are as follows.

First, the threshold voltage of the transistor increases as the temperature decreases. This is because the lower the temperature, the smaller the intrinsic carrier density of the transistor. In other words, as the temperature decreases, the diffusion current decreases, so the subthreshold current also decreases. Thus, the gate voltage applied to turn on the transistor rises (i.e., the threshold voltage rises).

Second, the threshold voltage of the transistor increases as the absolute value of the well bias voltage increases. This is because as the well bias voltage increases, the inversion charge formed in the channel is depleted, and thus a higher gate voltage is required to turn on the channel.

However, a threshold voltage of a cell transistor used in a volatile memory device among semiconductor devices should be higher than a predetermined value (lower limit value) in order to secure a punch-through margin of the cell transistor. However, if the threshold voltage is too high, the turn-on current of the cell transistor is reduced and the write recovery time (tWR) of the volatile memory device is long. Therefore, the threshold voltage of the cell transistor should be lower than a predetermined value (upper limit).

The foregoing describes the general fact that the upper limit of the threshold voltage of the transistor is determined by the value of the turn-on current, and the lower limit is determined by the value of the subthreshold current, that is, the leakage current. All transistors should be designed so that the threshold voltage is maintained between the specified upper and lower limits under the possible operating environment (change of temperature, applied voltage and process conditions).

On the other hand, the threshold voltage used can be defined in a number of ways, of which external VT (Vext), which describes the point in time at which a constant turn-on current flows, is suitable for defining an upper limit.

In addition, a saturation VT (VTsat) representing an applied gate voltage when a specified current value (eg, 10 nA) flows in a subthreshold voltage state is suitable for defining a lower limit value.

That is, the upper limit of the threshold voltage of the transistor may be represented by VText, and the lower limit may be represented by Vsat. These two threshold voltages may vary slightly depending on the definition, but are generally determined as shown in FIGS. 1A and 1B.

As can be seen in FIG. 1A, the threshold voltage VText is the gate-source voltage Vgs that crosses the slope of the drain current Id in a state where the drain-source voltage Vds of the transistor is about 0.1V. Is defined.

As shown in FIG. 1B, the threshold voltage VTsat is a gate-to-source voltage Vgs when the drain current logId is 10 mA when the drain-source voltage Vds of the transistor is about 1.8V. Is defined as

However, even when the semiconductor manufacturing process is stabilized so that the threshold voltages of the transistors integrated in the semiconductor device are between the upper and lower limits mentioned above, when the ambient temperature and the like change, the threshold voltages of the transistors are different from the upper limits mentioned above. Sometimes the threshold is out of bounds (typically, when the ambient temperature changes from a high temperature of 50 degrees to a room temperature of 25 degrees, the threshold voltage increases by about 50 mV). This can seriously change the operating characteristics of the transistor. It may cause malfunction of the semiconductor device.

The present invention has been proposed to solve the above problems, and to provide a transistor having a stable threshold voltage despite temperature changes.

In addition, the present invention provides a well bias voltage generator capable of varying the well bias voltage of a transistor according to a temperature change in order to prevent the threshold voltage of the transistor from changing with temperature.

In addition, the present invention is to prevent the threshold voltage of the transistor increases when the ambient temperature is lowered, the well bias to maintain the threshold voltage of the transistor constant by reducing the well bias voltage when the ambient temperature is lowered Provide a voltage generator.

In an embodiment of the present invention, a well bias voltage generator for a transistor includes a reference voltage generator for generating a reference voltage as a function of temperature, a level detector for receiving a reference voltage generated from the reference voltage generator, and an output signal of the level detector. An oscillator for generating a pulse of a predetermined period, and a pump for receiving the pulse generated from the oscillator and generating a well bias voltage applied to a well of a transistor,

The level detector compares the absolute value of the reference voltage with the well bias voltage and outputs a signal for driving the oscillator until it is equal to the reference voltage.

In the present invention, the well bias voltage is a back bias voltage which is a negative voltage, and the back bias voltage is applied to the well of the NMOS transistor.

In the present invention, the well bias voltage is a high voltage higher than the power supply voltage, and the high voltage is applied to the well of the PMOS transistor and the source of the PMOS transistor.

In the present invention, the change ratio of the reference voltage according to the change of the ambient temperature has a positive coefficient.

In the present invention, the change ratio with respect to the temperature of the back bias voltage and the high voltage has a positive coefficient.

In the present invention, the ratio of the change of the back bias voltage to the temperature has a negative coefficient (when the temperature increases, the back bias (negative value) becomes small) to the temperature of the high voltage applied to the wells and sources of the PMOS transistors. The ratio of change to has a positive coefficient.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. For reference, the well bias voltage generator described in the present invention is a term including a back bias voltage generator for adjusting the well bias of the NMOS transistor and a high voltage generator for adjusting the well bias of the PMOS transistor.

2 shows a back bias voltage generator capable of adjusting the back bias voltage of a transistor in response to temperature variations.

The back bias voltage generator shown in FIG. 2 includes a reference voltage generator 201, a level detector 202, an oscillator 203, and a back bias pump 204.

Unlike a general reference voltage generator having a characteristic insensitive to temperature change, the reference voltage Vr generated from the reference voltage generator 201 of the present invention contains information on temperature change. That is, when the ambient temperature of the semiconductor device rises, the reference voltage Vr generated from the reference voltage generator 201 increases at a constant rate. Those skilled in the art will be able to implement a variety of reference voltage generator 201 having such characteristics.

The level detector 102 is a circuit for comparing the reference voltage Vr generated from the reference voltage generator 201 with the back bias voltage VBB output from the back bias pump 204. As is well known, comparator circuits for receiving two voltages and comparing their heights are variously known and one of ordinary skill in the art would be able to select one of a variety of known comparator circuits and implement it with the level detector of FIG. The level detector 202 continues to output a logic signal for operating the oscillator 203 until the absolute value of the reference voltage Vr and the back bias voltage VBB to be described later become equal.

The oscillator 203 is a circuit for generating pulses of a predetermined period, the operation of which is determined according to the logic level of the output signal (enable) of the level detector 202. Those skilled in the art will be able to implement one of the known oscillators to implement the back bias voltage generator of the present invention.

 The back bias pump 204 is a pump circuit that receives a pulse of a predetermined period generated from the oscillator 203 and outputs a back bias voltage VBB which is a negative voltage. As described above, the back bias voltage VBB is applied to the level detector 202. One skilled in the art will be able to select one of the known back bias pumps and apply it to the back bias voltage generator of the present invention. As is well known, the back bias voltage VBB generated from the back bias pump 204 is used as the back bias voltage of the transistor integrated in the semiconductor device.

In operation, when the ambient temperature rises, the reference voltage Vr generated from the reference voltage generator 201 increases. When the reference voltage Vr increases, the level detector 202 outputs a signal having a logic level for driving the oscillator 203. Thus, the oscillator 203 generates a pulse of a predetermined period and applies it to the back bias pump 204. As a result, the back bias voltage VBB output from the back bias pump 204 becomes even more negative. That is, the absolute value of the back bias voltage VBB increases. In other words, when the ambient temperature rises, the absolute value of the back bias voltage VBB also increases.

For NMOS transistors, VText and VTsat tend to decrease as the temperature increases. VText decreases with increasing temperature, since intrinsic carrier density increases with increasing temperature. VTsat decreases with increasing temperature because the diffusion current, which accounts for most of the subthreshold current, increases with increasing temperature. Although the descriptors according to the temperature of each of these threshold voltages may be different depending on the mechanism, the fact that the threshold voltage decreases with increasing temperature is the same.

FIG. 2B is an embodiment of the reference voltage generator of FIG. 2A.

As shown, the embodiment of FIG. 2B includes reference voltage generators 20 and 21 and a voltage amplifier 22.

The reference voltage generator 20 is the same as a conventional reference voltage generator for outputting a stable voltage vr1 regardless of temperature, and such a circuit is known to those skilled in the art in various configurations.

Next, the reference voltage generator 21 is a circuit for receiving another reference voltage vr1 output from the reference voltage generator 20 and generating another reference voltage vr2, which is connected in series between the power supply voltage and the ground. It consists of a resistor R1, transistors P1 and N1, and a resistor R2. Transistor P1 is a PMOS transistor, and transistor N1 is an NMOS transistor, but those skilled in the art can replace it with other configurations as needed. The reference voltage vr1 is applied to the gate of the PMOS transistor P1, the gate and the drain of the NMOS transistor N1 are connected to each other to have a resistance function, and the reference voltage vr2 which is an output of the reference voltage generator 21 is provided. Is taken out from the drain terminal of the NMOS transistor N1.

Since the reference voltage generator 21 is formed by simply connecting a resistor and a transistor in series, the voltage level of the output voltage vr2 changes due to the influence of ambient temperature, unlike the case of the reference voltage generator 20. The temperature-dependent reference voltage generator can be variously implemented by those skilled in the art, and the present invention is merely suggested as an example.

The reference voltage vr2 output from the temperature dependent reference voltage generator 21 is applied to the voltage amplifier 22 for outputting the internal voltage. As shown, the voltage amplifier 22 includes differential amplifiers P2, P3, N2, N3, N4, a driver P4, and voltage dividers N5, N6. The differential amplifier comparatively amplifies the reference voltage vr2 and the output voltage of the voltage divider to generate the reference voltage Vr. As described in the prior art, the reference voltage Vr is used as the driving voltage of the oscillator.

In the embodiment of FIG. 2B, since the reference voltage vr2 has a characteristic that varies with temperature, when the temperature changes, the reference voltage Vr, which is an output voltage of the voltage amplifier 22, also has a characteristic that varies with temperature. .

The temperature characteristic graph of the embodiment of FIG. 2B is shown in FIG. 2C.

As can be seen in FIG. 2C, it can be seen that the reference voltage vr1, which is insensitive to temperature characteristics, maintains about 0.7 V regardless of a temperature change of about −20 ° C. to about 90 ° C. FIG. On the other hand, it can be seen that the reference voltage vr2 is gradually decreasing with increasing temperature.

For this reason, it can be seen that in the case of the present invention using the reference voltage vr2, the reference voltage Vr increases with a constant slope as shown in the graph as the temperature changes. That is, it can be seen that the output voltage (Vr) of the reference voltage generator of the present invention has a characteristic that changes with the change of temperature.

3A shows the change of VText and VTsat with temperature.

As can be seen in FIG. 3A, the lower limit value 305 of the operating temperature is determined by the VText 302 which tends to increase with decreasing temperature and the operating temperature by the VTsat 304 which tends to decrease with increasing temperature. The upper limit value 306 is determined to determine the allowable operating temperature range 307 of the transistor.

3B illustrates a change in the threshold voltage of a transistor according to temperature change when a back bias voltage according to the present invention is applied.

As can be seen in FIG. 3B, it can be seen that the lower limit of the operating temperature changes from (305) to (312) as the previous VText 302, which was not compensated for temperature change, changed to the same as VText 309, which compensated for temperature change. Can be. In addition, it can be seen that the upper limit of the operating temperature is changed from 306 to 311 as the previous VTsat 304 in which the temperature change is not compensated changes like the VTsat 310 in which the temperature change is compensated. As a result, the allowable operating temperature range widens from 307 to 313 as the temperature change is compensated for.

In FIG. 3B, 308 represents the reference temperature. This reference temperature means a temperature at which the back bias value is kept constant before and after use of the temperature compensated back bias generator. The reference temperature is located at the midpoint between the upper limit and the lower limit, as can be seen in Figure 3b. When the reference temperature is set to room temperature (27 ° C), the back bias for compensating for the temperature change is expressed as follows.

VBB (T) = VBBnorm + B * {(T / 300) -1}

Here, VBBnorm represents the back bias voltage at room temperature, B represents the temperature compensation coefficient, and T is the Kelvin temperature. VBB (T) has a negative value and B is negative because the absolute value of VBB (T) must increase when the temperature increases. In particular, by properly selecting the temperature compensation coefficient (B) it can be implemented a transistor having a threshold voltage insensitive to temperature changes.

3C shows the temperature compensation of the threshold voltage when the reference temperature is defined as the upper temperature limit 306. In this case, the upper limit of the temperature does not change any more, but it can be seen that the lower limit of the temperature is further improved than in the case of FIG. 3B.

3D shows the temperature compensation of the threshold voltage when the reference temperature is determined by the lower temperature limit 305. In this case, the lower limit of the temperature does not change any more, but it can be seen that the upper limit of the temperature is further improved than in the case of FIG. 3B.

In this way, it can be seen that the extent of improvement of the upper limit value and the lower limit value of the temperature varies depending on how the reference temperature is determined.

4 is an experimental result using the circuit proposed in the present invention.

In FIG. 4, both VText and VTsat represent threshold voltages, VText represents external VTs, and VTsat represents saturation VTs.

The relation regarding the temperature of VText and VTsat used in the experiment utilized the formula described in "Device Electronics for Integrated Circuits, second Edition" (author: R.S. Muller & T.I.Kamins, 1986). In addition, although the temperature compensation coefficient B was 2.98, this value can be changed according to the structure or process conditions of the transistor.

As can be seen from the experimental results of FIG. 4, in the conventional case, VText, which determines the turn-on characteristic of the transistor, increases when the temperature falls. However, as VText increases, the turn-on current of the transistor decreases. Therefore, in the conventional case, when the transistor is used as a memory cell transistor, the tWR fail bit will increase at a low temperature.

On the other hand, in the case of the present invention, it can be seen that the VText characteristic is almost constant regardless of the change in temperature.

On the other hand, as shown, in the case of the VTsat that determines the turn-off characteristics of the transistor, the diffusion current (diffusion) of the subthreshold region is very sensitive to changes in temperature, it is difficult to obtain the VTsat characteristics insensitive to changes in temperature it's difficult. However, even in the case of VTsat, when the circuit of the present invention is applied, it can be seen that the VTsat slightly increases and the slope is gentle at high temperatures. As VTsat increases, the leakage current of the transistors in the turn-off state decreases. Therefore, when the transistor with reduced leakage current is used as the cell transistor of the volatile memory device, the refresh characteristics can be improved.

The back bias voltage generator of the present invention described so far can be applied to all semiconductor devices. For example, a transistor having a stable threshold voltage may be implemented by applying a back bias voltage output from the back bias voltage generator of the present invention to transistors integrated in a cell array of a volatile memory device and a peripheral circuit thereof. Here, the back bias voltage is used as the well bias voltage of the NMOS transistors.

Meanwhile, the technical idea of the present application may be equally applied to a PMOS transistor.

That is, the PMOS transistor having a stable threshold voltage can be provided by providing a high voltage generator that increases the high voltage VPP applied as the well bias voltage of the PMOS transistor at an appropriate ratio as the temperature increases. Except for generating a high voltage, the basic structure of the high voltage generator is the same as the back bias voltage generator of FIG. However, unlike the case of the NMOS transistor, since the high voltage (VPP) used as the well bias voltage of the PMOS transistor is also used as the source voltage, it is necessary to consider the operating characteristics of the PMOS transistor.

In general, in the case of PMOS transistors, there is a factor in that the turn-on current decreases as the threshold voltage decreases as the temperature increases. However, when the temperature increases, the effect of reducing the turn-on current due to the decrease in the mobility of the carrier is greater than the effect of reducing the threshold voltage. As a result, when the temperature rises, the turn-on current of the PMOS transistor decreases. However, in this case (when the temperature rises), increasing the source-drain voltage difference of the PMOS transistor by increasing the well bias voltage and the high voltage (VPP) used as the source voltage of the PMOS transistor increases the turn-on current of the PMOS transistor. Can be increased. Therefore, even when the temperature rises and the mobility of the carrier of the PMOS transistor decreases, the high voltage can be increased to stabilize the operation characteristics of the PMOS transistor.

As described above, due to the high integration of the semiconductor device, the width of the transistor integrated in the semiconductor device is reduced and the length is reduced. However, in order to prevent the short channel effect, it is necessary to keep the threshold voltage Vt of the transistor above a certain level.

In the related art, when the threshold voltage increases due to temperature change, there is a problem in that the amount of current applied to the transistor in the turned-on state decreases. In addition, when the threshold voltage is lowered due to the temperature change, there is a problem in that the leakage current of the transistor to maintain the turn-off state increases.

In the present invention, it can be seen that the operation of the transistor insensitive to the temperature change is provided by providing a well bias voltage generator to cancel the temperature change of the threshold voltage.

As can be seen from the above, the present invention describes a well bias voltage generator capable of stabilizing the operation of a transistor integrated in a highly integrated semiconductor device.                     

The present invention can be applied to a cell array of a semiconductor device, particularly a volatile memory device, and a peripheral circuit thereof.

In particular, by applying to the peripheral circuit of the memory device, it is also possible to greatly mitigate the temperature characteristic mismatch phenomenon caused by the difference in the zero temperature coefficient (ZTC) of the NMOS and PMOS transistors that are a problem in low-voltage operation.

Claims (8)

A reference voltage generator that generates a reference voltage corresponding to changes in ambient temperature. A level detector for comparing the reference voltage generated from the reference voltage generator with a well bias voltage applied to the well of the transistor and outputting an enable signal corresponding thereto; An oscillator receiving the enable signal from the level detector and determining pulse generation at a predetermined period according to the level of the enable signal; And a pump for generating the well bias voltage to the transistor when the pulse is provided from the oscillator. The method of claim 1, The ratio of change of the reference voltage according to the change of the ambient temperature has a positive coefficient. The method of claim 2, The ratio of the change of the well bias voltage according to the change of the ambient temperature has a positive coefficient. The method of claim 1, The well bias voltage is a back bias voltage which is a negative voltage, and the back bias voltage is applied to the well of the NMOS transistor. The method of claim 4, wherein The change ratio of the reference voltage according to the change of ambient temperature has a positive coefficient, The ratio of change of the absolute value of the back bias voltage according to the change of ambient temperature has a positive coefficient. The method of claim 1, The well bias voltage is a high voltage higher than a power supply voltage, and the high voltage is applied to the well of the PMOS transistor and the source of the PMOS transistor. The method of claim 6, The change ratio of the reference voltage according to the change of ambient temperature has a positive coefficient, And the ratio of change of the high voltage with a change in ambient temperature has a positive coefficient. The method of claim 1, And the level detector outputs a signal for driving the oscillator until it is equal to the reference voltage by comparing the absolute value of the reference voltage and the well bias voltage.

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