KR100617033B1 - LCD - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device further comprising a stain preventing pattern between gate link lines and data link lines in order to reduce stain defects that may occur during coating of an organic insulating layer. A TFT array substrate divided into an active region including a plurality of gate wirings and data wirings, and a pad region of an outer portion of the active region, the gate link line extending from the gate wiring and the data wiring and formed in the pad portion region. And a stain prevention pattern formed of a plurality of dot patterns between the data link line, the data pad formed at the end of the data link line, the gate pad formed at the end of the gate link line, and the gate link line and the data link line. Characterized in that it comprises a.

Pad part, stain prevention pattern, organic insulating film

Description

Liquid Crystal Display Device

1 is a plan view of a small liquid crystal display device according to the prior art.

FIG. 2 is a cross-sectional view of the liquid crystal display device along the line II ′ of FIG. 1. FIG.

3 is a cross-sectional view of the liquid crystal display device along the II-II 'line of FIG.

4 is a plan view of a liquid crystal display device according to the present invention;

FIG. 5 is a cross-sectional view of the liquid crystal display device along the III-III ′ line of FIG. 4 according to the first embodiment of the present invention; FIG.

6 is a cross-sectional view of the liquid crystal display device along the line III-III 'of FIG. 4 according to a second embodiment of the present invention.

7 is a plan view of a liquid crystal display device according to a third embodiment of the present invention.

* Explanation of symbols on the main parts of the drawings

111 TFT array substrate 113 gate insulating film

116: protective film 117: pixel electrode

150: stain prevention pattern 153: active area

154: pad portion region

g1, g2, g3, .., gn-1, gn: gate wiring

d1, d2, d3, .., dm-1, dm: data wiring

L _g1 , L _g2 , L _g3 , .., L _gn-1 , L _gn : Gate link line

L _d1 , L _d2 , L _d3 , .., L _dm-1 , L _dm : Data link line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device (LCD), and more particularly, to a liquid crystal display device for preventing unevenness occurring during image display of a liquid crystal display device.

BACKGROUND ART Liquid crystal display devices, which have recently been spotlighted as flat panel display devices, have been actively researched due to their high contrast ratio, suitable for gradation display or moving picture display, and low power consumption.

In particular, it can be manufactured with a thin thickness so that it can be used as an ultra-thin display device such as a wall-mounted TV in the future, and is light in weight and consumes significantly less power than a CRT CRT. It is being used as a next generation display device. In addition, since it is manufactured as a small panel and used as a mobile phone display, its use is various.

Such liquid crystal display devices generally include a TFT array substrate in which a thin film transistor (TFT) and a pixel electrode are formed in each pixel region defined by gate wiring and data wiring, a color filter substrate in which a color filter layer and a common electrode are formed, It is composed of a liquid crystal layer interposed between the substrate, by applying a voltage to the electrode to rearrange the liquid crystal molecules of the liquid crystal layer to adjust the amount of light transmitted to display an image.

In this case, the TFT array substrate is required for driving from an active region including a plurality of pixel regions formed at each intersection of the gate wiring and the data wiring, and from the external drive integrated circuits to the gate wiring and data wiring of the active region. The pad portion may be divided into a pad portion region outside the active region including a gate pad and a data pad for supplying various signals.

A gate link line extending from the gate line to the gate pad and a data link line extending from the data line to the data pad are further formed in the pad area.

The gate pad and the data pad are connected to a printed circuit board (PCB) by a tape carrier package (TCP) in which a drive IC is mounted to supply a gate signal and a data signal. In the printed circuit board, a plurality of devices such as integrated circuits are formed on a substrate to generate various control signals and data signals for driving the liquid crystal display device.

Hereinafter, a TFT array substrate of a liquid crystal display device according to the prior art will be described in detail with reference to the accompanying drawings.

1 is a plan view of a small liquid crystal display device according to the prior art, FIG. 2 is a cross-sectional view of the liquid crystal display device along the line II ′ of FIG. 1, and FIG. 3 is a view of the liquid crystal display device along the line II-II ′ of FIG. 1. It is a cross section.

As illustrated in FIG. 1, the TFT array substrate 11 includes a plurality of gate lines G1, G2, G3,... Gn-1, Gn and data lines D1, D2, D3, which cross each other at right angles. The active region 53 in which a plurality of pixels are defined by Dm-1, Dm, and a printed circuit board (not shown) which is an external driving circuit by the gate pad 22 and the data pad 24; The pad portion region 54 is connected.

Specifically, a plurality of gate wirings G1, G2, G3, .., Gn-1, Gn and data wirings D1, D2, D3, .., Dm-1, Dm cross on the glass substrate in the active region. A thin film transistor (TFT) is formed at the intersection of the gate line and the data line as a switching element, and the thin film transistor has a protective layer, which is an organic insulating material, between the pixel electrode 17 and the thin film transistor. It is connected.

In the pad region, a gate pad 22 for applying a gate driving signal to each of the gate lines and a plurality of data pads 24 for applying a data signal to the data lines are formed. Interface electrical signals.

In this case, the gate pads 22 may include a plurality of gate link lines L _G1 , LG _G2 , LG _G3 , .. extending from a plurality of gate lines G1, G2, G3,..., Gn-1, Gn. The data pads 24 are formed at ends of, L _Gn-1 , L _Gn , and the data pads 24 extend from a plurality of data lines D1, D2, D3, .., Dm-1, Dm. _D1 , L _D2 , L _D3 , .., L _Dm-1 , L _Dm ).

In addition, the gate line, the gate link line, and the gate pad are formed at the same time, and the data line, the data link line, and the data pad are formed at the same time. A gate insulating film in which SiO x) or silicon nitride (SiN x) is deposited to a thickness of 2000 μs by a plasma enhanced chemical vapor deposition method is interposed.

In addition, a protective film is formed on the entire surface including the gate wiring and the data wiring by coating an organic insulating material such as benzocyclobutene (BCB) or an acrylic material to a thickness of 13 μm by spin coating.

Meanwhile, the pad portion region is divided into a gate pad portion having a gate pad and a data pad portion having a data pad. In general, the gate pad portion is disposed on the left and right sides of the liquid crystal panel and the data pad portion is disposed on the upper and lower sides of the liquid crystal panel.

However, in the case of a small panel used for a cellular phone monitor or the like, as shown in FIG. 1, the gate pad part and the data pad part are collectively disposed under the liquid crystal panel to minimize the size of the pad area.

For example, as illustrated in FIG. 1, the plurality of data wires D1, D2, D3,..., Dm-2, Dm-1, Dm may include data link lines L _D1 , L _D2 , L _D3,. ., _Dm-1 through L, L _Dm) connected to a data pad 24, and a plurality of gate lines (G1, G2, G3, .., Gn-1, Gn) linked to the gate lines _(G1 L , L _G2 , L _G3 , .., L _Gn-1 , L _{Gn are} connected to the first and second gate pads 22: 22a and 22b and disposed on left and right sides of the data pad 24, respectively. Here, odd-numbered gate lines G1, G3, ..., Gn-1 are connected to the first gate pad 22a, and even-numbered gate lines G2, ..., ... are connected to the second gate pad 22b. Gn-2, Gn) are connected.

At this time, it is a principle that the first gate pad portion and the second gate pad portion are symmetrically designed by forming an interval between the gate link line and the data link line at equal intervals.

However, since odd-numbered gate wires are connected to the first gate pad part and even-numbered gate wires are connected to the second gate pad part, the first gate pad part and the second gate pad part are not symmetrically designed. Occurred.

2 and 3, the distance d between L _G1 of the gate link line and L _D1 of the data link line is equal to the distance between L _Dm of the data link line and L _G2 of the gate link line. d ') narrower than

In addition, when the organic insulating material such as BCB or acrylic material is used as the protective layer 16, the groove 19 is generated between the gate link line and the data link line due to the high spin speed during the spin coating of the organic insulating material.

As such, when the groove 19 is formed along the link line between the gate link line and the data link line, spots are formed on the screen corresponding to the groove 19 (the right edge in FIG. 1), thereby degrading image quality. . As shown in FIG. 3, as the distance between the gate link line and the data link line increases, the groove is turned on during the spin coating of the protective film 16, thereby degrading the image quality.

For reference, reference numeral 13 in FIG. 2 and FIG. 3 denotes a gate insulating film, and reference numeral 16 denotes a protective film.

The present invention has been made to solve the above problems, the liquid crystal display device to prevent the staining of the image by arranging the stain prevention pattern in a relatively large space between the gate link line and the data link line to form a flat protective film The purpose is to provide.

A liquid crystal display device for achieving the object of the present invention is a TFT array substrate divided into an active region including a plurality of gate wirings and data wirings defining a plurality of pixels perpendicular to each other and a pad region of the outer portion of the active region. A gate link line and a data link line extending from the gate line and the data line and formed in the pad portion region, a data pad formed at an end of the data link line, and a gate pad formed at an end of the gate link line; And a stain prevention pattern formed in a plurality of dot patterns between the gate link line and the data link line.

That is, when the gap between the gate link line and the data link line is large, a stain prevention pattern is disposed between the gate link line and the data link line so that the thickness of the BCB or acrylic resin is uniform in the case of BCB or acrylic resin spin coating. It features.

Particularly, in the small panel, when the link line spacing of either the left or the right side is designed to be wider than the other side, during the spin coating of the organic insulating material such as BCB or acrylic resin by further disposing the anti-staining pattern between the wide gaps, It is characterized in that the image quality is to be improved by preventing grooves from occurring.

Hereinafter, a liquid crystal display device according to the present invention will be described with reference to the accompanying drawings.

4 is a plan view of a liquid crystal display device according to the present invention.

FIG. 5 is a cross-sectional view of the III-III 'liquid crystal display device of FIG. 4 according to the first embodiment of the present invention, and FIG. 6 is a III-III' line of FIG. 4 according to the second embodiment of the present invention. Is a cross-sectional view of the liquid crystal display device, and FIG. 7 is a plan view of the liquid crystal display device according to the third embodiment of the present invention.

As described above, the liquid crystal display device is divided into a color filter substrate on which a color filter layer for color realization is formed, an active region in which a switching element for changing the arrangement direction of liquid crystal molecules is formed, and a pad portion region connected to an external driving circuit. The TFT array substrate and a liquid crystal layer formed between the two substrates will be described. Hereinafter, the TFT array substrate will be described in detail.

As illustrated in FIG. 4, the TFT array substrate 111 includes a plurality of gate lines g1, g2, g3,.. active region 153 in which a plurality of pixels are defined by ..., dm-1, dm, and a plurality of gate link lines L _g1 , L _g2 , L _g3 , .., L _gn-1 , L _gn of the gate pad 122 and the plurality of data link lines L _d1 , L _d2 , L _d3 , .., L _dm-1 , L _dm extending from the data line. The pad pad region 154 connected to the external driving circuit is divided by the data pad 124 formed at the end thereof.

In this case, when the gap between the gate link line and the data link line is wide in the pad portion region, a spot prevention pattern 150 is further formed between the gate link line and the data link line.

Specifically, on the TFT array substrate 111 of the active region 153, a plurality of gate wirings g1, g2, g3, .., gn-1, gn and data wirings d1, d2, d3, .., dm A thin film transistor (TFT) is formed as a switching element at the intersection of the gate wiring and the data wiring, and a pixel electrode 117 is formed in each pixel region. The drain electrode of the thin film transistor is connected to the pixel electrode 117 with a passivation layer formed of an organic insulating material therebetween.

In this case, the gate wirings g1, g2, g3, .., gn-1, gn and the data wirings d1, d2, d3, ..dm-1, dm are made of aluminum (Al) and aluminum alloy ( Low-resistance metal materials such as AlNd), molybdenum (Mo), and chromium (Cr) are deposited and patterned by a sputtering method, and the pixel electrode 117 is formed on indium tin oxide (ITO) or indium tin oxide (IZO) on the passivation layer. It is formed by depositing and patterning a transparent conductive material such as Zinc Oxide).

The protective film is formed by applying an organic insulating material such as BCB (Benzocyclobutene) or an acrylic material by spin coating.

The thin film transistor may include a gate electrode branching from the gate wiring, a gate insulating layer formed by depositing an inorganic insulating material of silicon oxide (SiOx) or silicon nitride (SiNx) on the gate electrode, and a gate section on the gate electrode. A semiconductor layer of amorphous silicon (a-Si: H) formed on the smoke film and a stacked film of source / drain electrodes branched from the data line and formed on the semiconductor layer.

On the other hand, a gate pad 122 for applying a gate driving signal to each of the gate wirings and a data pad 124 for applying a data signal to each of the data wirings are formed in the pad region, thereby providing an external driving circuit and an electrical signal. In the case of the small panel, the gate pad and the data pad are collectively disposed under the liquid crystal panel to minimize the size of the pad region. That is, the first gate pad 122a and the second gate pad 122b are disposed on the left and right sides of the data pad 124, respectively.

A plurality of data link lines L _d1 , L _d2 , L _d3 , .., L _dm-1 , L _dm are connected to the data pad 124, and odd-numbered gate links are connected to the first gate pad 122a. Lines L _g1 , L _g3 , .., L _gn-1 are connected, and the second gate pad 122b has even-numbered gate link lines L _g2 ,,., Lg _n-2 , L _gn . Connected.

In this case, the gate link lines L _g1 , L _g2 , L _g3 , .., L _gn-1 , L _gn and the gate pad 122 are connected to the gate lines g1, g2, g3, .., gn-1. and gn are formed at the same time, and the data link lines L _d1 , L _d2 , L _d3 , .., L _dm-1 , L _dm and the data pad 124 are connected to the data lines d1, d2, d3, formed simultaneously with .., dm-1, dm).

Therefore, a gate insulating film is interposed between the gate link line and the data link line, and a protective film is formed on the entire surface including the data link line.

Meanwhile, as shown in FIG. 4, an island-like stain prevention pattern 150 formed of a plurality of dot patterns is formed between L _dm of the gate link line and L _g2 of the data link line. During spin coating of the protective film, which is an organic insulating material, the coating film is coated with a uniform thickness.

As shown in FIG. 7, the stain preventing pattern 150 is not formed in an island shape formed of a plurality of dot patterns, as shown in FIG. 4, and the gate link line L _dm and the data link line L are illustrated in FIG. 7. _g2 ) may be formed in a straight line.

As shown in FIG. 5, the spot prevention pattern 150 may be simultaneously formed on the same layer as the gate link line L _dm , and as shown in FIG. 6, the data link line L _g2. ) May be simultaneously formed on the same layer.

Therefore, even when spin-coating an organic insulating material on the entire surface including the link line, the spot preventing pattern 150 prevents a stain from being displayed on the screen without forming a groove between the gate link line and the data link line having a wide interval. .

Reference numeral “113” in FIGS. 5 and 6 denotes a gate insulating film, and “116” denotes a protective film.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

That is, in the present invention, the organic insulating material is limited to using the organic insulating material as the material of the protective film. However, the organic insulating material may also be used as the material of the uneven pattern provided to scatter external light in the reflective liquid crystal display device to improve viewing angle characteristics. In this case, the technical idea of the present invention will be applied.

The liquid crystal display of the present invention as described above has the following effects.

That is, when the gap between the gate link line and the data link line is large, the stain prevention pattern is disposed between the gate link line and the data link line to make the thickness of the organic insulating material uniform during spin coating of the organic insulating material.

Therefore, the formation of grooves due to uneven application of the organic insulating material between the wide link lines is prevented in advance, and as a result, the unevenness of the grooves can be removed, thereby improving the image quality of the liquid crystal display device.

Claims (11)

A TFT array substrate which is divided into an active region including a plurality of gate lines and data lines that vertically cross each other to define a plurality of pixels, and a pad portion region that is limited to one edge of the active region. A gate link line and a data link line extending from the gate line and data line and formed in the pad portion region; A data pad formed at an end of the data link line; A gate pad formed at an end of the gate link line and disposed adjacent to the data pad; And a stain prevention pattern additionally arranged in a plurality of dot patterns between the gate link line and the data link line. delete The gate pad of claim 1, wherein the gate pad includes a first gate pad formed at an end of an odd-numbered gate link line, and a second gate pad formed at an end of an even-numbered gate link line. And the first gate pad and the second gate pad are disposed at left and right sides of the data pad, respectively. The gate link line and the data of claim 3, wherein a space between the second gate pad and the data pad is larger than a space between the first gate pad and the data pad, and the anti-stain pattern is connected to the second gate pad. And a data link line connected to the pad. delete delete The liquid crystal display of claim 1, wherein the anti-staining pattern is formed on the same layer as the gate link line or the data link line. The liquid crystal display device of claim 1, further comprising a passivation layer on a front surface of the gate link line, the data link line, and the anti-staining pattern. The liquid crystal display device of claim 8, wherein the passivation layer is formed using an organic insulating material. The liquid crystal display device according to claim 8, wherein the protective film is BCB or photo acrylic resin. The liquid crystal display device of claim 8, wherein the passivation layer comprises an uneven pattern.

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