KR100614574B1 - Semiconductor device with landing plug and method of manufacturing same - Google Patents

Abstract

The present invention provides a semiconductor device having a landing plug that can increase contact resistance and prevent self-aligned contact failing between a storage node contact and a gate line without performing a photo and etching process for forming a landing plug, and a method of manufacturing the same. According to the present invention, a method of manufacturing a semiconductor device includes forming a plurality of gate lines on an upper surface of a semiconductor substrate, and forming a landing plug by growing a silicon epitaxial layer on the semiconductor substrate between the plurality of gate lines. Forming a metal silicide having both ends covering the upper edge of the gate line on the landing plug; forming an interlayer insulating film on the entire surface including the metal silicide; etching the interlayer insulating film to etch the metal silicide Forming a storage node contact hole exposing a portion of the surface of the And forming a storage node contact buried in the storage node contact hole. As described above, the present invention adds a metal silicide between the landing plug and the storage node contact, thereby suppressing an increase in contact resistance and etching a self-aligned contact. Fail of the process can be prevented.

Landing plug, storage node contact, silicon epitaxial layer, metal silicide

Description

Semiconductor device with landing plug and manufacturing method therefor {SEMICONDUCTOR DEVICE WITH LANDING-PLUG AND METHOD FOR MANUFACTURING THE SAME}             

1A to 1D are cross-sectional views illustrating a method of forming a landing plug according to the prior art;

2 illustrates a self-aligned contact fail according to the prior art;

3 is a structural cross-sectional view of a semiconductor device having a landing plug according to an embodiment of the present invention;

4A to 4G are cross-sectional views illustrating a method of manufacturing a semiconductor device having a landing plug according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 32 field oxide film

33: gate line 34: LDD region

35: gate spacer 36: source / drain area

37a, 37b: landing plug 38: first interlayer insulating film

39: titanium 40: titanium silicide

43: bit line 45: storage node contact hole                 

46: Storage node contact

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly to a method of manufacturing a semiconductor device having a landing plug.

In general, in the manufacture of semiconductor devices, electrical contact with a capacitor and a bit line is possible through a contact connected to a source / drain of a transistor.

Recently, as the degree of integration of semiconductor devices increases, the gap between conductive lines such as gate lines has narrowed, and thus, contact process margins have decreased. In order to secure such a contact process margin, a self aligned contact (SAC) process is being performed.

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device having a landing plug according to the prior art, and FIG. 2 illustrates a self-aligned contact fail according to the prior art.

As shown in FIG. 1A, after forming a field oxide film 12 for isolation between devices in a semiconductor substrate 11 having a cell region defined therein, a plurality of gate lines 13 are formed on the semiconductor substrate 11. do.

Next, after the ion implantation for forming the LDD region 14 is performed, the gate spacer 15 in contact with both sidewalls of the gate line 13 is formed, and the ions for forming the source / drain region 16 are formed. Proceed with infusion.

Subsequently, after the first interlayer insulating film 17 is formed on the entire surface, the first interlayer insulating film 17 is etched through a photo and etching process to form a landing plug contact hole (not shown) to form a landing plug contact. The polysilicon film 18 is deposited until the hole is filled.

As shown in FIG. 1B, the polysilicon film 18 is CMPed to form the landing plugs 18a and 18b until the upper portion of the gate line 13 is exposed. At this time, the first interlayer insulating film 17 is also planarized by CMP.

Next, after depositing the second interlayer insulating film 19 on the entire surface, a bit line contact hole (not shown) for opening one of the landing plugs 18a and 18b (not shown) is formed, and the bit line contact hole is formed. The bit line 20 is connected to one of the landing plugs 18b.

As illustrated in FIG. 1C, after the third interlayer dielectric layer 21 is deposited on the bit line 20, the third interlayer dielectric layer 21 and the second interlayer dielectric layer 19 are etched to form the bit line 20. The storage node contact hole 22 opening the surface of the landing plug 18b therebetween is formed.

As illustrated in FIG. 1D, the storage node contact 23 embedded in the storage node contact hole 22 is formed. At this time, the storage node contact 23 is formed by depositing a polysilicon layer until the storage node contact hole 22 is filled, and then etching back or CMP the polysilicon layer.

However, the above-described prior art forms a landing plug formed in a cell region by using a photo and etching process when forming a short channel, thereby causing source / drain parasitic resistance, junction capacitance, and leakage current.

In addition, the prior art has a problem that the contact resistance of the cell is increased by forming a contact made of the storage node and the storage node contact, the storage node contact and the landing plug are all made of a polysilicon layer, and the increase in contact resistance causes a problem of slowing down the speed. have.

In addition, in the etching process for forming the landing plug contact hole and the storage node contact hole, the process line is etched to the upper edge of the gate line, resulting in a process margin shortage, which is accompanied by the upper loss of the gate line ('24' in FIG. Therefore, there is a problem of causing a short between the storage node contact and the gate line, which is one of the self-aligned contact fail (SAC Fail).

The present invention has been proposed to solve the above problems of the prior art, it is possible to prevent the source / drain parasitic resistance, junction capacitance and leakage current generated when the landing plug is formed by employing the photo and etching process when forming the short channel SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a landing plug, and a method of manufacturing the same.

Another object of the present invention is to provide a semiconductor device having a landing plug and a method of manufacturing the same, which can prevent self-aligned contact failing between a storage node contact and a gate line while preventing an increase in contact resistance of a cell.

The semiconductor device of the present invention for achieving the above object is a landing plug of a semiconductor substrate, a plurality of gate lines formed on the semiconductor substrate, a silicon epitaxial layer grown on the surface of the semiconductor substrate between the plurality of gate lines, the A metal silicide formed on the landing plug and having both ends covering the upper edge of the gate line, and a storage node contact formed on the metal silicide, wherein the metal silicide covers the upper edge of the gate line. It is characterized by the form.

The method of manufacturing a semiconductor device of the present invention includes forming a plurality of gate lines on a semiconductor substrate, growing a silicon epitaxial layer on the semiconductor substrate between the plurality of gate lines, and forming a landing plug. Forming a metal silicide having a shape at which both ends cover an upper edge of the gate line on the landing plug, forming an interlayer insulating film on the entire surface including the metal silicide, and etching the interlayer insulating film to partially surface the metal silicide. Forming a storage node contact hole exposing the storage node contact hole, and forming a storage node contact embedded in the storage node contact hole, wherein the metal silicide partially covers an upper edge of the gate line. It is characterized by the overgrowth to be.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3 is a cross-sectional view illustrating a structure of a semiconductor device according to an embodiment of the present invention.                     

Referring to FIG. 3, a semiconductor device includes a semiconductor substrate 31 having a field oxide film 32 formed therein, a plurality of gate lines 33 formed on the semiconductor substrate 31, and a surface of the semiconductor substrate 31 between the plurality of gate lines. A landing plug 37a and 37b of a silicon epitaxial layer grown on it, a titanium silicide 40 formed on the landing plugs 37a and 37b, and a storage node contact 46 formed on the titanium silicide 40. do.

In FIG. 3, the titanium silicide 40 is formed to cover the upper edge of the gate line 33, and cobalt silicide is formed between the landing plug 37a and the storage node contact 46 in addition to the titanium silicide 40. Nickel silicide and molybdenum silicide are possible.

A source / drain region 36 having an LDD region 34 is formed on the surface of the semiconductor substrate 31 under the landing plugs 37a and 37b, and gate spacers are formed on both sidewalls of the gate line 33. 35) is formed.

The first interlayer insulating film 38 is embedded between the gate lines 33 except for the landing plugs 37a and 37b, and a part of the landing plugs 37a and 37b is filled with the second interlayer insulating film 41. The bit line 43 penetrating through is connected.

Finally, the storage node contact 46 is a polysilicon film, which simultaneously passes through the third interlayer insulating film 44 and the second interlayer insulating film 41 formed on the second interlayer insulating film 41 (not shown). And embedded in the titanium silicide 40.

Hereinafter, the manufacturing method will be described.

4A to 4G are cross-sectional views illustrating a method of manufacturing a semiconductor device having a landing plug according to an embodiment of the present invention.

As shown in FIG. 4A, after the field oxide layer 32 is formed on the semiconductor substrate 31 in which the cell region is defined, the element oxide layer 32 is separated from each other, and then a plurality of gate lines 33 are formed on the semiconductor substrate 31. do. Here, the gate lines 33 are stacked in the order of the gate oxide film, the polysilicon film, the tungsten film, and the hard mask nitride film, as is well known.

Next, after the ion implantation for forming the LDD region 34 is performed, ions for forming the gate spacer 35 contacting both side walls of the gate line 33 and forming the source / drain region 36 are formed. Proceed with infusion. Here, the gate spacer 35 is formed of a double structure of a silicon nitride film (Si ₃ N ₄₎ as formed, or, HLD (High temperature Low pressure Deposition) oxide film and a silicon nitride film (Si ₃ N _4).

Subsequently, a silicon epitaxial layer to be the landing plugs 37a and 37b is grown on the surface of the source / drain region 36.

At this time, the silicon epitaxial layer does not grow on the field oxide film 32, the gate spacer 35, and the gate line 33, which are insulating films, but grows only on the surface of the source / drain region 36.

As shown in FIG. 4B, the first interlayer insulating film 38 is formed on the entire surface, and then planarized by chemical mechanical polishing (CMP) until the surfaces of the landing plugs 37a and 37b are exposed.

Next, a metal film 39 is deposited on the entire surface including the planarized first interlayer insulating film 38. In this case, the metal film 39 is formed of titanium (Ti), cobalt (Co), nickel (Ni), and molybdenum (Mo). Hereinafter, the metal film 39 is abbreviated as "titanium 39" for convenience of description.

Titanium 39 is deposited to a thickness of 200 kPa to 450 kPa, and the deposition of titanium 39 proceeds for several tens of seconds at a temperature of 100 ° C to 400 ° C in a physical vapor deposition (PVD) apparatus in a vacuum atmosphere.

As shown in FIG. 4C, the annealing process is performed in a gas atmosphere of ammonia (NH ₃ ), nitrogen (N), or argon (Ar) to form a boundary between the titanium 39 and the landing plugs 37a and 37b. Titanium silicide 40 is formed.

Here, the annealing process for forming the titanium silicide 40 is performed for 10 seconds to 30 seconds at 650 ℃ to 750 ℃.

The titanium silicide 40 formed by the annealing process is formed by the reaction of the silicon of the titanium 39 and the landing plugs 37a and 37b. To have a shape covering the upper edge of the. That is, while inducing overgrowth of the titanium silicide 40, neighboring titanium silicide 40 is not shorted to each other.

Preferably, in order to easily cause overgrowth of the titanium silicide 40, the sum of the thicknesses of the landing plugs 37a and 37b and the thickness of the titanium makes the total height of the gate line 33 the same.

After the titanium silicide 40 is formed, unreacted titanium 39a remains.                     

As shown in FIG. 4D, unreacted titanium 39a that does not participate in the titanium silicide 40 reaction is removed. At this time, the unreacted titanium (39a) is removed using a wet etching process, but using a mixture of NH ₄ OH: H ₂ O ₂ : H ₂ O of 1: 1: 5. This mixed solution selectively etches only unreacted titanium 39a.

Next, an annealing process is further performed to implement electrical stabilization of the titanium silicide 40. At this time, the additional annealing process is performed for 10 seconds to 30 seconds at 800 ℃ to 850 ℃. For example, titanium silicide 40 is known to have an unstable C49 phase prior to further annealing, and an additional annealing process is applied to phase change the C49 to a stable C59 phase. As a result, the specific resistance of the titanium silicide 40 is reduced to implement a reduction in contact resistance.

Meanwhile, cobalt silicide, nickel silicide and molybdenum silicide formed of the metal films as described above in addition to the titanium silicide 40 are also possible.

As shown in FIG. 4E, after the second interlayer dielectric layer 41 is deposited on the entire surface, the second interlayer dielectric layer 41 is selectively etched to form the bit line contact hole 42.

In this case, since the titanium silicide 40 serves as an etch stop layer, the upper edge of the gate line 33 may be prevented from being etched.

As shown in FIG. 4F, a bit line 43 connected to any one landing plug 37b is formed through the bit line contact hole 42. Here, since the bit line 43 is electrically connected to the landing plug 37b through the titanium silicide 40, the contact resistance is reduced.

Next, after depositing the third interlayer insulating layer 44 on the bit line 43, the third interlayer insulating layer 45 and the second interlayer insulating layer 41 are etched to open the bit line 43. The node contact hole 45 is formed.

In this case, since the titanium silicide 40 serves as an etch stop layer, the upper edge of the gate line 33 may be prevented from being etched.

As shown in FIG. 4G, the storage node contact 46 is formed in the storage node contact hole 45. In this case, the storage node contact 46 is formed by depositing a polysilicon layer until the storage node contact hole 45 is filled, and then etching back or CMP the polysilicon layer.

According to the above embodiment, the titanium silicide serves as an etch stop layer during the etching process for forming the storage node contact hole and the bit line contact hole, thereby preventing the upper edge of the gate line from being attacked.

In addition, the contact resistance is lowered by adding titanium silicide between the landing plug and the bit line and between the landing plug and the storage node contact.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above has the effect of preventing the source / drain parasitic resistance, junction capacitance and leakage current when the shorting channel is implemented by forming the landing plug as a silicon epitaxial layer.

In addition, the present invention can reduce the contact resistance by forming the landing plug of the silicon epitaxial layer and titanium silicide, and also the effect of securing the process margin because titanium silicide acts as an etch stop layer during the self-aligned contact etching process. There is.

Claims (11)

Semiconductor substrates; A plurality of gate lines formed on the semiconductor substrate; A landing plug made of a silicon epitaxial layer grown on the semiconductor substrate surface between the plurality of gate lines; Metal silicide formed on the landing plug and having opposite ends covering upper edges of the gate line; And A storage node contact formed on the metal silicide Semiconductor device comprising a. delete The method of claim 1, The metal silicide, A semiconductor device, characterized in that selected from titanium silicide, cobalt silicide, nickel silicide and molybdenum silicide. The method of claim 1, And a source / drain region is formed on a surface of the semiconductor substrate on which the silicon epitaxy layer is grown. The method of claim 1, The storage node contact is a semiconductor device, characterized in that the polysilicon film. Forming a plurality of gate lines on the semiconductor substrate; Forming a landing plug by growing a silicon epitaxial layer on the semiconductor substrate between the plurality of gate lines; Forming metal silicides on both sides of the landing plug, the ends of which cover upper edges of the gate lines; Forming an interlayer insulating film on the entire surface including the metal silicide; Etching the interlayer insulating layer to form a storage node contact hole exposing a portion of the metal silicide surface; And Forming a storage node contact embedded in the storage node contact hole Method for manufacturing a semiconductor device comprising a. The method of claim 6, Forming the metal silicide, Depositing a metal film on the entire surface including the silicon epitaxial layer; Conducting an annealing process for forming the metal silicide by inducing a reaction between the metal film and the silicon epitaxial layer; And Removing an unreacted metal film not participating in the metal silicide formation Method for manufacturing a semiconductor device comprising a. delete The method of claim 7, wherein The metal film, Method of manufacturing a semiconductor device, characterized in that selected from titanium, cobalt, nickel and molybdenum. The method of claim 7, wherein The total thickness of the metal film and the silicon epitaxial layer is formed to be equal to the total height of the gate line. The method of claim 6, The storage node contact is formed of a polysilicon film.

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