KR100608382B1 - Output Enable Signal Generation Circuit - Google Patents

Abstract

The present invention relates to an output enable signal generation circuit which efficiently adjusts a delay of a DLL clock relative to an external clock and performs stable operation even in a high speed memory device. An output enable signal generation circuit is provided that combines an internal read command of a memory device and a DLL clock provided from a delay locked loop to generate an output enable signal (outen) that matches the cas latency (CL): An enable signal generator which receives the internal command and outputs a first enable signal synchronized with an external clock; It includes a plurality of sub chains having the same delay amount, and outputs the DLL clock as a plurality of first clock signals having different delay amounts by varying the number of the sub chains selected according to the cas latency (CL) Equal interval delay means; A plurality of first mux means for receiving each of the plurality of first clock signals and outputting one of the plurality of first clock signals as a second clock signal according to the cas latency (CL); The shift register includes a plurality of second clock signals as driving clocks and shifts the first enable signal to output a plurality of fourth enable signals having different delay amounts.

Description

Circuit for generating of output enable signal

1 is a simplified diagram of a typical data control circuit used in a memory device.

2 shows a simplified diagram of a conventional output enable signal generator.

3 is a configuration diagram of a conventional output signal generator.

4 is a simplified diagram of an output enable signal generator according to the present invention;

5 is an internal configuration diagram of an output signal generator according to the present invention.

6 is an internal configuration diagram of a sub chain according to the present invention.

7 is an internal configuration diagram of a bias voltage generation circuit according to the present invention.

8 is an internal configuration diagram of a first mux means according to the present invention;

9 is an operation waveform diagram of an output enable signal generator according to the present invention when the cascade latency CL is '6'.

Explanation of symbols on the main parts of the drawings

500: enable signal generator 600: output signal generator

610: equal interval delay means 630: shift register

640: sub-chain 620, 700: mux means

800: bias voltage generator

The present invention relates to an output enable signal generation circuit of a memory device. More particularly, the present invention relates to an output enable signal generation circuit that efficiently adjusts a delay of a DLL clock relative to an external clock and performs stable operation even in a high speed memory device. It is about.

1 is a simplified diagram of a typical data control circuit used in a memory device.

As shown, the data control circuit includes a control signal generator 100, an output enable signal generator 200, an output driver 300, and a delay locked loop 400.

The control signal generator 100 combines an external clock and a command to generate an internal clock, a read command readp, and a read end command bstendbp. Here, the read command readp is a high level pulse generated by the combination of the external commands RAS, CAS, .., and the read end command bstendbp is generated at the burst end, that is, at the end of the read operation. Low level pulse.

 The output enable signal generator 200 combines the output signals readp and bstendbp of the control signal generator 100 and the DLL clocks rclk and fclk provided from the delay lock loop 400 to provide a cascade latency CL. Generates an output enable signal (outen).

The delay locked loop 400 compensates for the delay tDO of the output driver 300 and lags with '-tDO' relative to the external clock to align the output data at the edge of the external clock. Generate DLL clocks (rclk and fclk).

The conventional data control circuit having the above configuration has a specific delay value according to the operation of each component. Looking at this, 'tCMD' is a delay for creating a read command (readp) or a read end command (bstendp); 'tDA' is a line delay from the control signal generator 100 to the output enable signal generator 200; 'tDO' is the delay of the output driver 300; 'DDD' refers to a line delay from the delay locked loop 400 to the output enable signal generator 200.

2 shows a simplified diagram of a conventional output enable signal generator.

As shown in the drawing, the conventional output enable signal generator 200 receives a read command readp and a read end command bstendbp, and outputs an enable signal oe00 synchronized with an external clock. Able signal generator 210; An output signal generator 220 for synchronizing the enable signal oe00 with the dll clocks rclk and fclk; And mux means 230 for generating an output enable signal outen corresponding to the cascade latency CL.

Referring to FIG. 3, a configuration of a conventional output signal generator 220 will be described.

As shown, the output signal generator 220 includes a shift register 221 composed of a plurality of D flip-flops; Multiple delay lines 222 for compensating 'tTOT (tCMD + tDA-tDD + tDO)', which is a delay difference between the enable signal oe00 and the DLL clock, and for applying a delay corresponding to the cascade latency CL. And mux means 223.

Through such a configuration, the existing circuit generates an enable signal dll_clk_oe synchronized to the DLL clock by means of each delay line 222 having a unique delay according to the cascade latency CL. Latch a read command readp.

However, the conventional circuit may have a problem that it is difficult to latch the enable pulse section of the read command (readp) in the high speed operation. That is, as the speed of the memory device increases, the enable pulse section of the read command is shortened, so that it is difficult to accurately adjust the delay of each of the plurality of delay lines 222 to latch it. In addition, since the D flip-flop used in the shift register 221 must be provided with a latch circuit (not shown) for maintaining the output node at a constant level, there is a limit of setup / hold margin in high speed operation. .

Therefore, the present invention was created to solve the problems according to the prior art as described above, an object of the present invention is to change the structure of the delay line and the shift register output enable signal generation circuit for stable operation at high frequency In providing.

In order to achieve the above object, according to an aspect of the present invention, an output enable signal (outen) matching the cas latency (CL) is combined by combining an internal read command of a memory device and a DLL clock provided from a delay locked loop. A generated output enable signal generation circuit is provided, the circuit comprising: an enable signal generator for receiving the internal command and outputting a first enable signal synchronized with an external clock; It includes a plurality of sub chains having the same delay amount, and outputs the DLL clock as a plurality of first clock signals having different delay amounts by varying the number of the sub chains selected according to the cas latency (CL) Equal interval delay means; A plurality of first mux means for receiving each of the plurality of first clock signals and outputting one of the plurality of first clock signals as a second clock signal according to the cas latency (CL); And a shift register configured to output the plurality of fourth enable signals having different delay amounts by shifting the first enable signal by using the plurality of second clock signals as driving clocks.

In the above configuration, the equal interval delay means is constituted by the sub-chains connected in series, and a connection node of the sub-chain is provided with a buffer for outputting data.

In the above configuration, the sub chain is composed of a CMOS buffer and an NMOS transistor connected in series between a power supply voltage and ground, and receives a bias voltage to the gate terminal of the NMOS transistor.

In the above configuration, the delay amount of the signal input to the CMOS buffer is adjusted by the bias voltage.

In the above configuration, the shift register is composed of a plurality of DYNAMIC D flip-flops.

In the above configuration, the output enable signal generation circuit receives the plurality of fourth enable signals, and outputs one of the plurality of fourth enable signals based on the cas latency CL. and a second mux means for outputting to the outen.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 shows a simplified diagram of an output enable signal generator according to the present invention.

As illustrated, the output enable signal generation unit according to the present invention receives a read command readp and a read end command bstendbp, and outputs an enable signal oe00 synchronized with an external clock. Generating unit 500; An output signal generator 600 for synchronizing the enable signal oe00 with the dll clocks rclk and fclk; Mux means 700 for generating an output enable signal outen corresponding to the cascade latency CL; And a bias voltage generator for providing a bias voltage BIAS to the output signal generator 600.

5 is a diagram illustrating an internal configuration of an output signal generator according to the present invention.

As shown, the output signal generator 600 according to the present invention outputs the DLL clock dll_clk input according to the cascade latency CL as a plurality of first clock signals clk_CL having different delay amounts. Equal interval delay means (610); A plurality of mux means 620 for receiving a plurality of first clock signals clk_CL and outputting one of the plurality of first clock signals as a second clock signal dll_clk_oe according to the cascade latency CL; And shifting the first enable signal oe00 to output the plurality of fourth enable signals oe10 to oe90 having different delay amounts, respectively, by using the plurality of second clock signals dll_clk_oe as a driving clock and shifting the first enable signal oe00. A register 630 is provided.

The equal interval delay means 610 is configured in series with a plurality of sub chains 640 having the same delay, and a connection node of each of the plurality of sub chains 640 is provided with a buffer 650 for signal output. Here, the total delay of the equal interval delay means 610 has a delay of 'tTOT (tCMD + tDA-tDD + tDO)' which is a delay difference between the enable signal oe00 and the DLL clock dll_clk described with reference to FIG. 1. . In addition, referring to FIG. 6, the configuration of the sub chain 640 includes a CMOS buffer 641 and an NMOS transistor 642 connected in series between a power supply voltage and a ground, and an NMOS transistor ( A predetermined delay is applied to the input signal in according to the voltage level of the bias voltage BIAS input to the gate terminal of 642. At this time, since the bias voltage BIAS is input to the plurality of sub chains 640 in common, each sub chain 640 has the same delay. On the other hand, the bias voltage generator 800 has a configuration as shown in FIG. 7, and can adjust the voltage level of the bias voltage BIAS through the selection signals sel <0> to sel <n>. That is, when the selection signal 'sel <0>' is enabled, the bias voltage BIAS has the lowest level, and when the selection signal 'sel <n>' is enabled, the bias voltage BIAS has the highest level. In addition, when all of the selection signals sel <0> to sel <n> are disabled, the bias voltage BIAS has a power supply voltage VDD level.

Hereinafter, a driving method of the output signal generator 600 according to the cascade latency CL will be described.

For example, when the cascade latency CL is '9', the equal interval delay means 610 divides the plurality of subchains 640 into eight equal parts, and the DLL clock dll_clk from the output terminal of the divided subchains 640. A plurality of first clock signals clk_CL91 to clk_CL97 and dll_clkd are delayed. At this time, among the first clock signals clk_CL91 to clk_CL97, dll_clkd, the first clock signal clk_CL91 output from the sub-chain 640 farthest from the input DLL clock dll_clk is referred to as' tTOT (tCMD +). tDA-tDD + tDO) '. On the other hand, the first clock signal dll_clkd nearest to the input DLL clock dll_clk has the same delay as the DLL clock dll_clk.

For reference, when the cascade latency cl is '6', the equal interval delay means 610 divides the plurality of subchains 640 into six equal parts, and thus, the first clock from the output terminal of the divided subchains 640. The signals clk_CL61 to clk_CL64 and dll_clkd are output. Of course, the first clock signal clk_CL61 output from the sub-chain 640 farthest from the input DLL clock dll_clk among the first clock signals may be the same as that of the above-described 'tTOT (tCMD + tDA-tDD + tDO)'. Has a delay. The first clock signal dll_clkd nearest to the input DLL clock dll_clk has the same delay as the DLL clock dll_clk.

 Thereafter, the plurality of mux means 620 receives the plurality of first clock signals clk_CL91 to clk_CL97 and dll_clkd, respectively, and the plurality of first clock signals clk_CL91 to clk_CL97 and dll_clkd according to the cas latency. Is output as the second clock signal dll_clk_oe10 to dll_clk_oe80.

The shift register 630 uses the plurality of second clock signals dll_clk_oe10 to dll_clk_oe80 as driving clocks, and shifts the first enable signal oe00 so that a plurality of fourth enable signals oe10 to different delay amounts are provided. output oe90). Here, the shift register 630 uses each of the second clock signals dll_clk_oe10 to dll_clk_oe80 as a driving clock, and is composed of a plurality of dynamic D flip-flops 631 connected in series. That is, the first enable signal oe00 synchronized to the external clock is output as a plurality of fourth enable signals oe10 to oe80 having different delay amounts in synchronization with the second clock signals dll_clk_oe10 to dll_clk_oe80 having different periods. The fourth enable signal oe80 output from the D flip-flop 631 of the last stage is output in synchronization with the DLL clock dll_clk.

The mux means 700 receives a plurality of fourth enable signals oe10 to oe80 as shown in FIG. 8, and outputs an output enable signal outen corresponding to the cascade latency CL by a logical combination. Occurs. Therefore, the mux means 700 outputs the fourth enable signal oe80 as an output enable signal outen when the cas latency latencies CL is '9'.

9 illustrates an operation waveform diagram of the output enable signal generation unit according to the present invention when the cascade latency CL is '6'.

As shown, when the read command READ is applied, the enable signal oe00 is output from the enable signal generator 500 after a 'tCMD + tDA' delay in synchronization with the external clock CLK. Thereafter, the output signal generator 600 compensates for the delay of 'tTOT (tCMD + tDA-tDD + tDO)', which is a delay difference between the enable signal oe00 and the DLL clock dll_clk. The fourth enable signal oe50 is output by synchronizing the enable signal oe00 with the DLL clocks rclk_dll and fclk_dll. Next, the first mux means 700 outputs the fourth enable signal oe50 as an output enable signal outen by the CAS latency CL6, and the output driver (not shown) receiving the signal is external. The data DQ is output 6 clocks after the read command READ command is applied (eclk6) based on the clock CLK.

As described above, the output enable signal generator according to the present invention includes an equal interval delay means 610 in place of a plurality of delay lines provided in the existing circuit. This is composed of a plurality of sub chains having the same delay, so that even in high-speed operation of the memory device, accurate delay adjustment according to cas latency can be performed. In other words, the circuit of the present invention can accurately latch a short pulse section of a read command as the delay can be adjusted accurately even in a high-speed memory device. In addition, instead of the general D flip-flop used in the shift register 630, by using the dynamic D flip-flop 631, which keeps the output node in a floating state in the standby state, it is advantageous for high speed operation.

According to the above-described configuration of the present invention, it is possible to accurately latch the short pulse section of the read command as it is possible to control the stable delay even at a high frequency.

While the invention has been shown and described with reference to certain preferred embodiments, the invention is not so limited, and the invention is not limited to the spirit and scope of the invention as set forth in the following claims. Those skilled in the art can readily appreciate that these various modifications and variations can be made.

Claims (6)

 An output enable signal generation circuit for combining an internal command of the memory device with the DLL clock provided from the delay locked loop to generate an output enable signal (outen) suitable for the cascade latency (CL); An enable signal generator which receives the internal command and outputs a first enable signal synchronized with an external clock; It includes a plurality of sub chains having the same delay amount, and outputs the DLL clock as a plurality of first clock signals having different delay amounts by varying the number of the sub chains selected according to the cas latency (CL) Equal interval delay means; A plurality of first mux means for receiving each of the plurality of first clock signals and outputting one of the plurality of first clock signals as a second clock signal according to the cas latency (CL); An output enable signal comprising a plurality of second clock signals as driving clocks, shift shifting the first enable signal, and outputting a plurality of fourth enable signals having different delay amounts; Generating circuit. The method of claim 1, The equal interval delay means, And a plurality of sub-chains connected in series, each of the access nodes of the plurality of sub-chains being provided with a buffer for outputting data. The method of claim 2, The sub chain, And a CMOS buffer and an NMOS transistor connected in series between a power supply voltage and a ground, and receiving a bias voltage through a gate terminal of the NMOS transistor. The method of claim 2, The sub chain, And a delay amount of a signal input to the CMOS buffer by the bias voltage. The method of claim 1, The shift register, And an output enable generation circuit comprising a plurality of dynamic D flip-flops. The method of claim 1, The output enable signal generation circuit, Second mux means for receiving the plurality of fourth enable signals and outputting one of the plurality of fourth enable signals as the output enable signal (outen) according to the cas latency (CL); And an output enable signal generation circuit comprising:

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