KR100608324B1 - Manufacturing Method of Semiconductor Device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. First, by growing a silicon by using a selective growth method, a planar MOS capacitor and a process of implementing the device are performed. It can be used as a planar MOS capacitor area to increase the capacitor capacity by increasing the area. A method of manufacturing a semiconductor device according to the present invention includes forming a shallow trench isolation (STI) film on a silicon substrate and then forming an oxide film for insulation; Forming a silicon growth film by growing silicon on the silicon substrate without the oxide film using a selective growth method; Implanting ions onto the structure to form N wells and P wells; Forming a gate oxide film and a polysilicon film on the structure; The gate oxide layer and the polysilicon layer are divided into a first region to be used as a gate of a transistor and a second region to be used as a planar capacitor, and are simultaneously patterned. Patterning as possible; Implanting LDD ions and tilt ions onto the structure to form an LDD ion implantation layer and a tilt ion implantation layer; Forming a buffer oxide layer and an LDD spacer on sidewalls of the gate; Performing a N + / P + ion implantation process on the structure to form a source / drain junction layer; And forming a silicide layer on the gate and the source / drain junction layer by performing an annealing process after forming a metal material layer for forming the silicide layer on the structure.

Description

Method of manufacturing a semiconductor device {METHOD OF MANUFACTURE SEMICONDUCTOR DEVICE}

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

(Explanation of symbols for the main parts of the drawing)

21 silicon substrate 22 shallow trench separator

23 silicon growth film 24 photoresist film

26 gate oxide film 27 gate polysilicon film

28: LDD ion implantation layer 29: tilt ion implantation layer

30 buffer oxide film 31 spacer layer

33 source / drain bonding layer 34 silicide film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to form and control a planar MOS capacitor forming region during a semiconductor process of manufacturing a device implementing DRAM and logic as one chip. The present invention relates to a method of fabricating a semiconductor device in which silicon is grown using a selective growth method in a device implementation region, and then a Salicide process is performed from a well ion implantation.

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

First, as shown in FIG. 1A, a shallow trench isolation (STI) film 2 for device isolation is formed on a silicon (Si) substrate 1. At this time, the STI film 2 is filled with an insulating film (or an oxide film) and processes a region other than active by a chemical mechanical polishing (CMP) process (planarization).

Next, as shown in FIG. 1B, after forming the mask pattern 3 on the structure, well ions are implanted into the silicon substrate 1 to form P wells and N wells.

Next, as shown in FIG. 1C, a gate oxide layer 5 and a polysilicon layer 6 are deposited on the structure, and then a gate electrode is formed through a patterning process. At this time, the polysilicon film 6 is isotropically etched.

Next, as shown in FIG. 1D, after the gate pattern is formed, LDD ion implantation is performed on the lightly doped drain (LDD) ion implantation layer 7 to control electric fields of carriers flowing between the source / drain junction layers. This is because the size of the device is reduced, but the operating voltage of the device is not reduced, so that a very high electric field is concentrated in a portion of the channel drain side, and thus an unwanted carrier flow is formed, which makes it difficult to operate the device. The hot carrier effect (HCE) can be minimized.

After the LDD ion implantation layer 7, formation of the LDD ion implantation layer is performed by giving ion to give a tilt to improve the characteristics of the SCE (Short Channel Effect), in which the channel length is reduced and the threshold voltage is lowered. (7) By forming the tilt ion implantation layer 8 in the periphery, the SCE phenomenon is alleviated.

Next, as shown in FIG. 1E, a buffer oxide film 9 is formed on the sidewall of the gate 6.

Next, a nitride film is deposited on the structure and then etched to form an LDD spacer 10 on the sidewall of the gate.

Next, as shown in FIG. 1F, a process of N + / P + ion implantation 11 is performed on the structure to form a source / drain region 12.

Next, as shown in FIG. 1G, a cobalt (Co) and a TiN film (not shown), which is a capping material, are formed on the structure to perform an annealing process.

Then, after removing the capping material and the unreacted cobalt (Co) film, a cobalt silicide film 13 is formed on the gate 6 and the source / drain region 12 where the polysilicon is exposed.

However, in the conventional method of manufacturing a semiconductor device, as shown in FIG. 1C, an area where a capacitor can be formed has a limit in implementing a capacitor having a gate oxide film as an insulator. This limits the capacitance of the capacitor, which requires increasing the planar MOS capacitor formation area to achieve the desired capacitor capacity. However, in this case, there is a problem in that the density in the wafer is reduced and the chip size of one product is increased.

That is, in the case of DRAM using a planar MOS capacitor during the process of implementing DRAM and logic as one chip as part of the system on chip business The logic process is used as it is, but there is a problem in that the capacity of the capacitor is limited according to the limitation of the capacitor formation region.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to first grow a silicon by using a selective growth method, and then proceed with a process of implementing a planar MOS capacitor and a device, without deteriorating the density in the wafer. To provide a method for manufacturing a semiconductor device that can be used as a planar MOS capacitor region to the side surface of the selectively grown silicon can increase the capacitor capacity through the increase in area.

According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method including: forming a shallow trench isolation (STI) film on a silicon substrate and forming an oxide film for insulation to define an active region; Selectively growing silicon in the active region on the silicon substrate to form a silicon growth film; Implanting ions onto the structure to form N wells or P wells; Forming a gate oxide film and a polysilicon film on the structure; The gate oxide layer and the polysilicon layer are divided into a first region to be used as a gate of a transistor and a second region to be used as a planar capacitor, and are simultaneously patterned. Patterning as possible; Implanting LDD ions and tilt ions onto the structure to form an LDD ion implantation layer and a tilt ion implantation layer; Forming a buffer oxide film and an LDD spacer on sidewalls of the polysilicon film patterned into the first region and the second region; Ion implanting impurities of P + or N + on the structure to form a source / drain junction layer; And forming a silicide layer on the source / drain junction layer and the polysilicon layer patterned into the first region and the second region by performing an annealing process after forming a metal material layer for forming a silicide layer on the structure. do.

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Before the silicon growth film is formed, a natural oxide film is removed using a hydrogen fluoride (HF) -based compound.

Before forming the silicon growth layer, a hydrogen annealing process is used to protect the silicon substrate to be epi-growth with hydrogen.

The hydrogen annealing process is characterized in that for about 10 seconds to 5 minutes flowing hydrogen (H ₂ ) 1 to 20 liters (liters) per minute in the temperature range of 800-1000 ℃.

The silicon growth film has a thickness of 100 to 2000 kPa.

The epitaxial growth condition during the formation of the silicon growth layer is characterized in that the progress in the range of 650 to 900 ℃, 10mtorr to 10torr.

Gas used in the formation of the silicon growth film is characterized in that the SiH ₂ Cl ₂ and HCl proceeds in the range of 40 to 800cc, 10 to 200cc, respectively.

The source of the silicon growth film is characterized by using any one of SiH ₂ Cl ₂ , SiH ₄ , Si ₂ H ₆ .

The gas added for the selective growth is characterized by using HCl or Cl ₂ gas.

The source of the tilt ion implantation process is characterized by using boron (Bron) or BF ₂ ions in the case of P wells, phosphorus (P) or arsenic in the case of N wells.

Energy during the tilt ion implantation process is characterized in that the range of 2 to 50 KeV.

The dose in the tilt ion implantation step is characterized in that the range of 1.0E12 to 5.0E13 atoms / cm ² .

The tilt during the tilt ion implantation process is characterized in that it proceeds to 7 to 45 °.

Twist during the tilt ion implantation process is characterized in that in the range of 0 to 360 °.

The circulation conditions during the tilt ion implantation process is characterized in that four times.

The gate oxide film may have a thickness of about 20 to about 70 kPa.

The thickness of the polysilicon film is formed to about 1500 to 2500Å.

The buffer oxide film may be formed to have a thickness of about 150 to 300 kPa.

The LDD spacer may have a thickness of about 800 to 1500 mW.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

First, FIG. 2A shows a pattern state before forming a device. In order to secure a region where a device is to be formed, shallow trench isolation (STI) for device isolation on a silicon (Si) substrate 21 is performed. Film 22 is formed.

Next, as shown in FIG. 2B, the silicon growth film 23 is formed by selectively growing silicon only in an area in which the oxide film forming the shallow trench isolation film 22 on the silicon substrate 21 is absent. At this time, the growth thickness is determined in consideration of the size of the area increase of the planar MOS capacitor, and is also determined to be less than the local STI formation area.

Next, as shown in FIG. 2C, in order to proceed with the well formation process, the photoresist layer 24 is covered with a photoresist layer 24, and then ion implantation 25 is performed, followed by the photoresist layer 24. By eliminating it, the active area in which the device is to be implemented is secured. At this time, in the case of an NMOS transistor, a P well using boron is formed, and in the case of a PMOS transistor, an N well using phosphorus and arsenic is formed.

Next, as shown in FIG. 2D, the gate oxide layer 26 and the polysilicon layer 27 are grown and deposited on the structure, and then a pattern is formed. At this time, the portion to be used as the gate of the MOS transistor and the portion to be used as the dielectric film and the upper electrode of the planar MOS capacitor are simultaneously patterned. The portion to be used as the upper electrode of the MOS capacitor of the silicon growth film 23 is used as the lower electrode of the MOS capacitor.

In this case, in the case of the planar MOS capacitor portion, the gate oxide layer 26 and the polysilicon layer 27 are formed not only on the upper side but also on the side surface of the selectively grown silicon growth layer 23 by the structural shape of the selectively grown silicon surface. . Therefore, it is possible to have a higher degree of integration than a planar MOS capacitor manufactured by the conventional method, and also to have a large capacitor area, thereby increasing the capacitor capacity.

In the case of gate doping, doping may be performed simultaneously during the subsequent process of forming the source / drain junction layer, or ion implantation may be performed before gate patterning if additional doping is required.

Next, as shown in FIG. 2E, after the gate pattern is formed, LDD ion implantation is performed on the lightly doped drain (LDD) ion implantation layer 28 to control the electric field of carriers flowing between the source / drain junction layer. This is because the size of the device is reduced, but the operating voltage of the device is not reduced, so that a very high electric field is concentrated in a portion of the channel drain side, and thus an unwanted carrier flow is formed, which makes it difficult to operate the device. HCE can be minimized.

After the LDD ion implantation layer 28 is formed, the length of the channel is reduced and the LDD ion implantation layer is implanted by giving a tilt to improve the characteristics of the SCE (Short Channel Effect), which lowers the threshold voltage. (28) The SCE phenomenon is alleviated by forming the tilt ion implantation layer 29 around the periphery.

Then, as shown in FIG. 2F, the buffer oxide film 30 is formed on the sidewalls of the polysilicon film 27 of the portion to be patterned to be used as the upper electrode of the gate and the planar MOS capacitor, respectively.

Next, a nitride film is deposited on the structure and then dry-etched to form the LDD spacers 31 on the buffer oxide film 30.

Next, as shown in FIG. 2G, a process of N + / P + ion implantation 32 is performed on the structure to form a source / drain junction layer 33.

Then, an annealing process is performed so that a high concentration of dopant may be present in the portion to be used as the gate of the polysilicon film 27 and the source / drain junction layer 33.

The portion to be used as the gate of the polysilicon layer 27 and the source / drain junction layer 33 are then brought into contact with a metal to apply an operating voltage, thereby selectively controlling the flow of carriers. However, in this state, since the contact resistance with the metal is high, the silicide layer 34 is formed on the portion to be used as the gate of the polysilicon layer 27 and the source / drain junction layer 33 as shown in FIG. 2H. Process is required.

As shown in FIG. 2H, a cobalt (Co) and a TiN film (not shown), which is a capping material, are formed on the structure to perform an annealing process.

Then, after the capping material and the unreacted cobalt (Co) film are removed, the cobalt silicide film 34 is deposited on the source / drain junction layer 33 and the portion to be used as the gate of the polysilicon film 27 where the polysilicon is exposed. Is formed.

As described above, according to the method of manufacturing a semiconductor device according to the present invention, by first growing the silicon using the selective growth method, and then proceeding to implement the planar MOS capacitor and the device, thereby selectively without deteriorating the density in the wafer As the planar MOS capacitor region can be used to the side of the grown silicon, the capacitor capacity can be increased by increasing the area.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (6)

Forming a shallow trench isolation (STI) film on the silicon substrate and forming an oxide film for insulation to define an active region; Selectively growing silicon in the active region on the silicon substrate to form a silicon growth film; Implanting ions onto the structure to form N wells or P wells; Forming a gate oxide film and a polysilicon film on the structure; The gate oxide layer and the polysilicon layer are divided into a first region to be used as a gate of a transistor and a second region to be used as a planar capacitor, and are simultaneously patterned. Patterning as possible; Implanting LDD ions and tilt ions onto the structure to form an LDD ion implantation layer and a tilt ion implantation layer; Forming a buffer oxide film and an LDD spacer on sidewalls of the polysilicon film patterned into the first region and the second region; Ion implanting impurities of P + or N + on the structure to form a source / drain junction layer; And And forming a silicide layer on the source / drain junction layer and the polysilicon layer patterned into the first region and the second region by performing an annealing process after forming a metal material layer for forming a silicide layer on the structure. A method of manufacturing a semiconductor device, characterized in that. The method of claim 1, A method of manufacturing a semiconductor device, characterized in that before the silicon growth layer is formed, a silicon substrate to be epitaxially grown is protected by hydrogen through a hydrogen annealing process. The method of claim 3, wherein The hydrogen annealing process is a method of manufacturing a semiconductor device, characterized in that for about 10 seconds to 5 minutes flowing hydrogen (H ₂ ) 1-20 liters (liters) per minute in the temperature range of 800-1000 ℃. The method of claim 1, The silicon growth film has a thickness of 100 to 2000 kPa, the semiconductor device manufacturing method characterized by the above-mentioned. The method of claim 1, The epitaxial growth condition during the formation of the silicon growth film is a method of manufacturing a semiconductor device, characterized in that proceeding in the range of 650 to 900 ℃, 10mtorr to 10torr. The method of claim 1, The gas used in the formation of the silicon growth film is a method for manufacturing a semiconductor device, characterized in that the SiH ₂ Cl ₂ and HCl proceeds in the range of 40 to 800cc, 10 to 200cc respectively.

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