KR100604792B1 - Optical Transfer System having Transmitter and Receiver - Google Patents

Abstract

An optical transmission system comprising a transmitting device and a receiving device is disclosed. In an optical transmission system including a transmitting device and a receiving device according to the present invention, an optical transmission system converts an externally applied video signal into an optical signal, transmits the optical signal, and restores the converted optical signal to an original video signal. A video controller, a transmission device, a transmission photodiode, an optical transmission path, a reception photodiode, and a reception device are provided. The video controller separates the color signal and the horizontal / vertical sync signal from the video signal and transmits the color signal and the horizontal / vertical sync signal in response to a predetermined data enable signal and a clock signal applied from the outside. The transmitting device skews and compresses the signals applied from the video controller and converts the compressed signal into a drive current. The transmission photodiode converts the drive current output from the transmission device into an optical signal and outputs the converted optical signal. The optical transmission path is composed of a predetermined number of channels to transmit optical signals. The receiving photodiode converts an optical signal applied through an optical transmission path into a current and outputs the converted current signal. The receiving device converts the current signal into a voltage, decompresses and skews the converted signal to restore the original signal. According to the present invention, high-speed data transmission can be performed by optically transmitting data of the LCD monitor, and there is an effect that electromagnetic interference (EMI) noise can be eliminated.

Description

Optical transfer system having a transmitter and a receiver {Optical Transfer System having Transmitter and Receiver}

1 is a block diagram schematically illustrating an optical transmission system according to an exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing a transmitting device of the optical transmission system shown in FIG.

FIG. 3 is a block diagram showing an optical driver of the transmitting apparatus shown in FIG. 2.

FIG. 4 is a circuit diagram specifically illustrating a band gap circuit of the optical driver illustrated in FIG. 3.

FIG. 5 is a circuit diagram illustrating a laser driver of the optical driver shown in FIG. 3.

6 (a) to 6 (c) are waveform diagrams for explaining the operation of the laser driver shown in FIG.

7 (a) to 7 (c) are other waveform diagrams for explaining the operation of the laser driver shown in FIG.

8 is a block diagram illustrating a receiving apparatus of the optical transmission system shown in FIG. 1.

FIG. 9 is a block diagram illustrating an optical receiver of the receiving device illustrated in FIG. 8.

10 is a detailed circuit diagram of the optical receiver shown in FIG.

11A and 11B are waveform diagrams illustrating input and output signals of the optical receiver illustrated in FIG. 10.

12A to 12D are waveform diagrams for describing an operation of the optical receiver illustrated in FIG. 10.

13 (a) to 13 (c) are other waveform diagrams for explaining the operation of the optical receiver shown in FIG.

FIG. 14 is a block diagram illustrating a data recovery and skew compensation unit of the reception apparatus illustrated in FIG. 8.

15 (a) and 15 (b) are waveform diagrams of word clock signals and serial data applied to the data recovery and skew compensation unit shown in FIG.

FIG. 16 is a flowchart illustrating a data restoration method using the apparatus shown in FIG. 14.

17 are waveform diagrams of first through ninth non-overlapping clock signals output from a word clock signal and a clock signal generator.

FIG. 18 is a circuit diagram specifically illustrating a first latch unit illustrated in FIG. 14.

19 is a block diagram illustrating in detail the synchronization unit illustrated in FIG. 14.

20 is a detailed flowchart of operation 540 of FIG. 16.

The present invention relates to a data transmission system, and more particularly, to an optical transmission system having a transmitting device and a receiving device.

In general, cathode ray tube (CRT) monitors are controlled by analog methods. However, liquid crystal display (LCD) monitors use digital signals as drive signals. For example, an LCD monitor, which is not connected to the main body and is provided externally, converts an analog video signal into a digital signal inside the monitor using a digital / analog converter, and displays the data on the screen by the converted digital signal. . In addition, the LCD monitor of the notebook computer receives the digital signal itself from the main body, and displays the data on the screen accordingly. However, in the case of transmitting and displaying the digital signal in this way, the influence of the interference or noise of the signal may occur. Therefore, a method of changing a signal type using a panel link chip using a low voltage differential signal (LVDS) or the like and transmitting the same to a LCD panel is widely used.

However, conventional LCD monitors using the digital system use coaxial cables for data transmission. In such a case, the price can be increased by using an analog / digital converter. In addition, as resolutions for displays are increasingly increased, special countermeasures such as increased transfer rates are required. In addition, in the case of transmitting data through a coaxial cable, there is a disadvantage that a limitation depending on the signal transmission distance may occur. That is, if the cable length is increased, noise may be generated according to the cable, making long distance transmission difficult. In addition, there is a problem that the electromagnetic interference (EMI) phenomenon between the cables can be generated and the quality of the transmission data may be degraded.

SUMMARY OF THE INVENTION The first technical problem to be solved by the present invention is to provide an optical transmission system having a transmitting device and a receiving device capable of high-speed transmission and eliminating electromagnetic interference between cables.

A second technical problem to be achieved by the present invention is to provide an optical driver provided in the transmission device of the optical transmission system.

 The third technical problem to be achieved by the present invention is to provide an optical receiver provided in the receiving device of the optical transmission system.

A fourth technical object of the present invention is to provide a data recovery and skew compensation circuit capable of stably restoring original information data by compensating for skew between data transmitted through a transmission channel and a word clock signal in the receiving apparatus. To provide.

A fifth technical object of the present invention is to provide a data restoration method performed in the data restoration and skew compensation circuit.

In order to achieve the first object, an optical transmission system including a transmitting device and a receiving device according to the present invention converts an externally applied video signal into an optical signal and transmits the converted optical signal to the original video signal. An optical transmission system for restoring a light source, comprising: a video controller, a transmission device, a transmission photodiode, an optical transmission path, a reception photodiode, and a reception device. The video controller separates the color signal and the horizontal / vertical sync signal from the video signal and transmits the color signal and the horizontal / vertical sync signal in response to a predetermined data enable signal and a clock signal applied from the outside. The transmitting device skews and compresses the signals applied from the video controller and converts the compressed signal into a drive current. The transmission photodiode converts the drive current output from the transmission device into an optical signal and outputs the converted optical signal. The optical transmission path is composed of a predetermined number of channels to transmit optical signals. The receiving photodiode converts an optical signal applied through an optical transmission path into a current and outputs the converted current signal. The receiving device converts the current signal into a voltage, decompresses and skews the converted signal to restore the original signal.

In order to achieve the second object, the optical driver included in the transmission device of the optical transmission system according to the present invention is provided to an optical driver of a transmitter for transmitting predetermined channel data as an optical signal through an optical transmission path. A bias and modulation resistance variable part, a band gap circuit, and a laser driver are provided. The bias and modulation resistance variable part includes a bias resistor and a modulation resistor whose resistance value is varied, and changes the bias resistance and the amount of current output by the change of the modulation resistance value. The band gap circuit sets a band gap reference voltage that is always maintained at a constant value regardless of external changes, and varies the bias current or modulation current by the set reference voltage and the current change by the bias resistor and the modulation resistor. The laser driver receives each channel data, converts it into a current signal, and outputs the modulation current generated in the band gap circuit and the bias current as a driving current for driving an external optical element by adding the current signal.

In order to achieve the third object, the optical receiver provided in the receiving apparatus of the optical transmission system according to the present invention receives the channel data converted from the external optical receiving diode into a current signal and restores the digital signal to a digital signal. An optical receiver comprising: a bias circuit, a current / voltage converter, an amplifier, a duty compensator, and a level converter. The bias circuit receives a predetermined current from a power supply voltage to generate a first bias current and a second bias current. The current / voltage converter sources the current in response to the first bias current, and converts the current signal output from the light receiving diode into a differential voltage signal. The amplifier unit sources the current in response to the first bias current, amplifies the differential voltage signal, and generates the amplified result as the first differential output signal and the second differential output signal. The duty compensator is implemented by comparators having a current summing structure in which the current is sourced in response to the first bias current and the output current is added to each other, and the first differential output signal is compared with the first reference voltage, and the second differential The output signal is compared with the second reference voltage to generate first and second output signals corresponding to the compared result. The level converter sources the current in response to the second bias current, digitizes the voltage levels of the first output signal and the second output signal output from the duty compensator, and outputs the digitized signal.

In order to achieve the fourth object, the data recovery and skew compensation circuit provided in the receiving apparatus of the optical transmission system according to the present invention is a phase for generating first to nth non-overlapping clock signals having a predetermined offset so as not to overlap each other. A synchronization loop, each of n (where n is a positive integer of 1 or more), and multiplexed synchronization signals and information data to serially transmit data through the transmission channel to the first through nth non-overlapping clock signals. A data recovery and skew compensation circuit of a receiving device which restores in response, comprising a first latch unit, a second latch unit, and a synchronization unit. The first latch unit latches the received serial transmission data in units of n + N−1 bits (where N is a positive integer of 3 or more) in parallel in response to the first through nth non-overlapping clock signals, and N state data consisting of n bits each latched with a time offset of a predetermined offset are output. The second latch unit latches N state data in parallel in response to an X (1 ≦ X ≦ n) non-overlapping clock signal having the largest timing margin among the first to nth non-overlapping clock signals. The synchronization unit outputs, as the information data, the state data for which the synchronization signal is detected among the data latched in the second latch unit in response to the predetermined synchronization existence signal and the X-th non-overlapping clock signal.

In order to achieve the fifth task, the data recovery method of the data recovery and skew compensation circuit according to the present invention is transmitted in series with a clock signal through a transmission channel, where n is n (where n is a positive integer of 1 or more). A data recovery method for recovering information data from serial transmission data multiplexed with a bit-synchronous signal and information data, comprising steps (a) to (e). In step (a), first to nth non-overlapping clock signals having a predetermined offset are generated based on the clock signal so that they do not overlap each other. Step (b) latches the received serial transmission data in units of n + N-1 bits (where N is a positive integer of 3 or more) in parallel using the first through nth non-overlapping clock signals. Step (c) generates N state data of n bits each having a time offset of a predetermined offset from each other. In step (d), the N state data are latched in parallel in synchronization with the Xth (1 ≦ X ≦ n) nonoverlapping clock signal having the largest timing margin among the first through nth nonoverlapping clock signals. In step (e), when the serial transmission data is a synchronization signal, the state data for which a synchronization signal is detected among the latched state data is determined as the restored information data.

Hereinafter, an optical transmission system including a transmitter and a receiver according to the present invention will be described with reference to the accompanying drawings.

1 is a block diagram schematically illustrating an optical transmission system according to an exemplary embodiment of the present invention. The optical transmission system includes a video controller 10, a transmission device 12, a transmission photodiode 14, an optical transmission path 15, a reception photodiode 16, and a reception device 17. For convenience of description, a thin film transistor (hereinafter, referred to as TFT) LCD panel 19 is shown together. The optical transmission system of the present invention can be applied between an LCD monitor and a PC, and can be applied between other display devices and external devices.

The video controller 10 separates the R / G / B color signal and the horizontal / vertical sync signal (HSYNC, VSYNC) from a video signal applied through a programmable communication bus (PCI) system bus from the PC main body or the outside. In addition, the video controller 10 transmits the R / G / B color signal or the synchronization signal HSYNC / VSYNC in response to an externally enabled data enable signal DE and a clock signal CLK. As an example, the R / G / B color signals may be implemented as 8-bit digital signals, respectively.

The transmitter 12 skew-compensates and compresses the digital signal applied from the video controller 10, and generates a driving current for driving the optical transmission diode 14 using the compressed signal.

The transmitting photodiode 14 is typically implemented with a laser diode such as a vertical cavity surface emitting laser (VCSEL). In addition, the transmission photodiode 14 converts the drive current applied from the transmission device 12 into an optical signal and transmits it.

The optical optical fiber (POF) 15 transmits the optical signal converted by the transmitting optical diode 14 to the receiving optical diode 16 on the receiving side.

The receiving photodiode 16 is generally implemented as a photodiode. In addition, the receiving photodiode 16 converts the received optical signal into a current signal and outputs it.

The receiving device 17 converts the current signal applied from the receiving photodiode 16 into a voltage, decompresses and skews the converted signal to restore the original digital signal. At this time, the restored signal is displayed on the LCD panel 19 in response to the clock signal CLK and the data enable signal DE.

First, the transmission apparatus of the optical transmission system shown in FIG. 1 will be described in more detail.

FIG. 2 is a block diagram of an embodiment showing the transmitting device 12 shown in FIG. Referring to FIG. 2, the transmitting device 12 includes a skew compensator 200, a scrambler 220, a data serializer 240, a phase locked loop (PLL) 270, and an optical driver ( 260).

The PLL 270 receives a clock signal CLK from the video controller 10 (see FIG. 1) to generate a clock signal synchronized with the clock signal CLK, and provides the generated clock signal to each of the blocks. Here, the PLL 270 inputs a clock signal CLK having a frequency of 25 MHz to 112 MHz in the case of a high speed transmission having a Giga Hz transmission rate. In addition, the PLL 270 generates non-ovelapping clock signals CKP for data compression performed by the data serialization unit 240 using the synchronized clock signal.

The skew compensator 200 receives channel data of a predetermined bit from the video controller 10 in response to the synchronized clock signal, and compensates for the skew generated between the channel data with respect to the clock signal. Here, skew means that the transmission time between data is shifted from each other with respect to the reference clock. That is, the skew compensator 200 compensates for a shift between a plurality of data lines with respect to a clock signal that is a reference for data transmission. If the skew between the data channels exceeds the allowable value, the picture may be abnormal because video data is distorted or no synchronization signal is detected. To prevent this, the skew compensator 200 sets a specific bit stream so that the start and end of the data bit stream can be known. It also allows the start of each data bitstream to be aligned around any set point in time. In FIG. 2, each R / G / B signal may be implemented with 8 bits (n−1), and the control signal CON may be implemented with 4 bits (m). In addition, it is assumed that the horizontal / vertical synchronization signal HSYNC / VSYNC and the data enable signal DE are applied through one control signal input terminal CON.

The scrambler 220 of FIG. 2 counts the number of high and low levels of skew-compensated channel data in response to the synchronized clock signal, and adds the counted information to each channel data as DC balance information. That is, the DC balance information added by the scrambler 220 indicates whether the high level and the low level of each data bit are balanced in the digital transmission. Therefore, the DC balance information serves as a criterion for determining the level of data when restoring data on the receiving side. For example, if the power supply voltage is overloaded, a change in power supply and ground may cause an error in determining a high level and a low level in the received data. Also, if the high / low level sections are not balanced during data transfer, the reference potential changes proportionally. For this reason, an error may occur in determining the high and low levels of data at the receiving side. To this end, the scrambler 220 counts the number of high level sections and low level sections within a character. The counted result is sent to the receiving side on top of the data to be transmitted. For example, assuming that data bits of a character input to the scrambler 220 are 8 bits, the output data bits are 9 bits to which DC balance information is added.

The data serializer 240 of FIG. 2 compresses parallel data of each channel output from the scrambler 220 in response to the non-overlapping clock signals CKP generated by the PLL 270. The compressed result is generated with channel data of 1 bit. Here, the channel data may be an R / G / B color signal and a control signal CON. If the data is not compressed and transmitted, channels of the number of bits constituting each R / G / B color signal and channels of the number of bits constituting the control signal are required. However, if data is compressed and transmitted as in the present invention, the number of channels can be reduced. In addition, the data transfer rate is increased proportionally by the rate of compression when the data is compressed. For example, when 9-bit parallel data is compressed into a 1-bit signal, the transmission speed may be 9 times faster. As such, it is possible to implement transmission rates of 1.008 Gbps and 1.458 Gbps depending on the data compression ratio. The data serializer 240 is implemented with devices having a fast gating time so as to be suitable for high speed transmission.

The optical driver 260 receives the compressed channel data and the clock signal into different channel data, converts them into current signals, and outputs the converted current signals to drive an external optical device. In addition, the optical driver 260 changes the modulation current and the bias current by the band gap reference voltage and the external modulation resistance and bias resistance values. In addition, the optical driver 260 converts the channel data into a current, and generates a driving current by reflecting the modulation current and the bias current in the channel data. RDL_OUT, GLD_OUT, and BLD_OUT in FIG. 2 represent R / G / B signals converted to optical signals, respectively. Also, CONLD_OUT and CLKLD_OUT represent a control signal CON and a clock signal CLK, which are converted into optical signals, respectively. Here, the output intensity of the current for driving the optical element can be adjusted externally. The optical driver 260 is described in detail with reference to FIG. 3.

3 is a block diagram for describing the optical driver 260 shown in FIG. 2. Referring to FIG. 3, the optical driver 260 includes a band gap circuit 300, a bias and modulation resistance variable unit 360, and a laser driver 340. For convenience of description, the external parasitic element unit 370 and the laser diode 14 are shown together.

The band gap circuit 300 of FIG. 3 includes a band gap reference voltage generator 310 and a bias and modulation current generator 320. The band gap circuit 300 generates an external photodiode driving current based on the internal band gap reference voltage. The bias and modulation resistance variable unit 360 is externally provided to change the bias resistance value and the modulation resistance value to vary the bias current VBIA and the modulation current VMOD. Here, the modulation current VMOD is defined as the current for varying the swing range of the optical signal actually transmitted. In addition, the bias current VBIA is defined as a current for controlling the DC level of the optical signal to be output. The bias current is set at the on / off boundary of the laser diode to prevent the data transfer rate due to the on / off of the laser diode from decreasing.

As described above, the band gap reference voltage generator 310 internally generates a band gap reference voltage for determining a driving current for driving the laser diode. Here, the band gap reference voltage is always unaffected by process problems, external temperature, power supply or noise and is always kept constant. In addition, the band gap reference voltage generator 310 amplifies the modulation voltage generated by the external modulation resistor and the bias voltage generated by the bias resistor. Here, each output of the operation amplified is kept constant.

The bias and modulation current generator 320 feeds the operational amplification outputs VO1 and VO2 output from the band gap reference voltage setting unit 310 to the band gap reference voltage generator 310 to keep the output voltage constant at all times. do. In addition, the bias and modulation current generator 320 may vary the laser diode driving current according to an externally varying bias and modulation current.

The bias and modulation resistance variable part 360 of FIG. 3 includes a resistor R30 and a capacitor C30 connected between a bias voltage RBIA and a ground GND and a capacitor C30 and a modulation voltage RMOD and a ground GND. It includes a resistor (R31) and a capacitor (C31) connected. Here, the resistor R30 is a resistor for varying the bias resistor value externally. Therefore, the bias current for driving the laser diode is determined by the value of the resistor R30. In addition, the resistor R31 is a resistor for varying the modulation resistance value externally. Therefore, as the value of the resistor R31 is changed, the swing width of the current for driving the laser diode is determined. In addition, the capacitors C30 and C31 are additionally provided to reduce the influence of external noise.

The laser driver 340 receives each channel data SIN and converts the channel data SIN into a current signal. The laser driver 340 adds the modulation current VMOD generated by the band gap circuit 300 and the bias current VBIAS to add the driving current LD_OUT. Generate. The laser driver 340 is described in detail with reference to FIG. 5.

In addition, the external parasitic element unit 370 of FIG. 3 includes resistors R32 and R33, capacitors C32 and C33, coils L31 and L32, resistors R34, and capacitors C34. That is, the external parasitic element unit 370 represents a model in which parasitic elements that may be generated between the output of the laser driver 340 and the laser diode 14 are modeled. For example, parasitic capacitor components by pads of integrated circuits and parasitic components by bonding wire thickness or area of a chip may be modeled. In other words, when the compressed data is transmitted at a high frequency of 1.5 Gbps as in the present invention, such parasitic components must be taken into consideration when designing a circuit since the influence of parasitic elements cannot be ignored.

The optical driver 260 illustrated in FIG. 3 is provided for each channel. That is, five driver circuits are provided for three channels for each of the R / G / B color signals and two channels for the control signal CON and the clock signal CLK. Here, the number of channels may change somewhat depending on the circuit design scheme.

FIG. 4 is a detailed circuit diagram illustrating the band gap circuit 300 of the optical driver 260 shown in FIG. 3. Referring to FIG. 4, the band gap circuit 300 includes a band gap reference voltage generator 310, a bias and modulation current generator 320, and a power save controller 330.

The band gap reference voltage generator 310 of FIG. 4 includes a voltage generator 312 and an operational amplifier 314. In the band gap reference voltage generator 310, the voltage generator 312 receives the power supply voltage VCC and generates a band gap reference voltage REF that is always maintained at a constant value even when an external change occurs. To this end, the voltage generator 312 may be configured to control the PMOS transistors MP10, MP11, MP13, and MP14, the PNP transistors QN11 to QN19, the resistors R10 to R19, and the capacitors C10 and C11. Include.

Subsequently, the voltage generator 312 is described in more detail. The voltage generator 312 detects the change in the band gap reference voltage REF due to an external change, for example, a distribution of a resistance, a change in power supply voltage, a change in temperature, or a change in characteristics of a transistor. To compensate. The potential of the first node N1, which is a reference in the voltage generator 312, is determined by the voltage across the gate of the transistor MP14. The current flowing through the transistor MP14 is controlled by the voltage between the gate and the source of the transistor MP14. The band gap reference voltage REF is determined by a value obtained by dividing the voltage of the first node N1 by the resistor R18 and the resistor R20. In addition, the voltages RMOD and RBIA applied to the external resistors R30 and R31 are always compensated to a constant level by forming a feedback loop by the operational amplifiers 46 and 48. If the power supply voltage, the temperature, the amplification coefficient change and the resistance distribution of the transistor change, the voltage of the first node N1 changes. At this time, the transistors QN11 and QN12 having a base connected to the other side of the resistors R16 and R17 having one side connected to the first node N1 sense the respective amounts of change and compensate for the amount of change. That is, when the amount of change is sensed in the transistors QN11 and QN12, the gate-source voltage Vgs of the PMOS transistor MP11 is changed. At this time, assuming that the changed gate-source voltage is ΔV, the voltage between the base and emitter of the NPN transistor QN15 is changed by ΔV. As a result, the potential of the third node N3 is changed, and as a result, the voltage of the third node N3 is changed by ΔV. At this time, since the voltage of the third node N3 is applied to the gate of the PMOS transistor MP13, when the voltage of the third node N3 is changed, the current flowing in the MP13 may also change. Therefore, the DC potential of the second node N2 connected to the source of MP13 is changed. Since the second node N2 is connected to the gate of the PMOS transistor MP14, when the DC potential of the second node N2 is changed, the voltage between the gate and the source of the transistor MP14 is changed. Therefore, the potential of the first node N1 connected to the drain of the transistor MP14 is compensated in response to the change amount of the second node N2. As a result, the voltage of the third node N2, which is changed due to the resistance distribution, the power supply voltage, the temperature change, or the amplification coefficient of the transistor, is compensated by the amount of change through the second node N2 and the first node N1. Can be. Therefore, the band gap reference voltage REF is always maintained at a constant voltage by compensating the voltage of the first node N1.

The operational amplifier 314 is configured to determine a band gap reference voltage REF generated by the voltage generator 312, a voltage RBIA applied to the external bias resistor R30, and a voltage RMOD applied to the modulation resistor R31. Operationally amplification is performed to generate a first output voltage VO1 and a second output voltage VO2. To this end, the operational amplifier 314 includes PMOS transistors MP15 and MP16 and operational amplifiers 46 and 48.

Subsequently, the operational amplifier 314 is described in detail. The band gap reference voltage REF is applied to each positive input terminal of the operational amplifiers 46 and 48. The voltage RBIA applied to the external bias resistor R30 is applied to the negative input terminal of the operational amplifier 46. In addition, the voltage RMOD applied to the external modulation resistor R31 is applied to the negative input terminal of the operational amplifier 48. The result of the operational amplification VO1 in the first operational amplifier 46 and the result of the operational amplification in the second operational amplifier 46 are fed back to the respective sub-input terminals to keep the output voltages VO1 and VO2 constant. . For this reason, the bias voltage RBIA and the modulation voltage RMOD are always kept constant. However, when the resistance value of the external bias resistor R30 or the modulation resistor R31 is changed, the amount of current flowing through the terminals RBIA and RMOD is changed. Therefore, the amount of current output through the operational amplifier 46 or 48 can be varied. Here, in the PMOS transistors MP15 and MP16, the voltage between the gate and the source is changed according to the voltage of the second node N2 of the voltage generator 312. Current flowing through each drain of the transistors MP15 and MP16 is applied as a bias current of the operational amplifiers 46 and 48.

In the band gap circuit 300 of FIG. 4, the bias and modulation current generator 320 feeds back the first and second output voltages VO1 and VO2 to the band gap reference voltage generator 310. Accordingly, the first and second output voltages VO1 and VO2 are kept constant, and the modulation voltage RMOD and the bias voltage RBIA are also kept constant. In addition, the bias current VBIA and the modulation current VMOD are varied by the resistance values of the bias resistor or the modulation resistor.

Subsequently, the bias and modulation current generator 320 is described in detail. When the value of the bias resistor R30 is changed in the bias and modulation current generator 320, the current output from the operational amplifier 48 is changed. Thus, the base current of the transistor MP20 is variable. As a result, the amount of current flowing through the transistors QN20 and QN21 is varied to change the amount of current flowing through the transistor MP17. Therefore, the bias current VBIA output to the laser driver 340 is different. In addition, when the modulation resistor R31 is changed, the current output from the operational amplifier 46 is changed. At this time, the base current of the transistor QN22 is varied so that the current flowing through the transistors QN22 and QN23 is changed. As a result, the amount of current flowing through the transistor MP20 is changed so that the modulation current VMOD applied to the laser driver 340 (see FIG. 3) is varied. In the present invention, the power supply voltage VCC may be designed for low voltage and implemented as 3.3V, and the band gap reference voltage REF may be set to about 1V. At this time, if the resistance value of the external bias resistor or the modulation resistor is 10KΩ, the current transmitted through the VBIA or VMOD is about 100uA.

In order to minimize power consumption, the power save controller 330 of FIG. 4 converts the band gap circuit 300 to the sleep mode in response to an externally applied power save control signal PDB. To this end, the power save control unit 330 includes inverters 42 and 44 and PMOS transistors MP12, MP18 and MP19 connected in series.

For example, when the power save control signal PDB applied from the outside is inactive at a high level, the transistors MP12, MP18, and MP19 are turned off. In addition, when the power save control signal PDB is activated at a low level, the transistors MP12, MP18, and MP19 are turned on. As such, when the power save control signal PDB is activated, the third node N3 and each of the current output nodes VBIA and VMOD are fixed to a high level. As a result, the band gap reference voltage generator 310 and the bias and modulation current generator 320 do not operate and are switched to the sleep mode.

FIG. 5 is a circuit diagram illustrating the laser driver 340 of the optical driver 260 of FIG. 3 in detail. Referring to FIG. 5, the laser driver 340 includes a data separator 50 and a voltage / current converter and a current driver 55.

The data separator 50 of FIG. 5 separates each channel data into a non-inverted signal and an inverted signal, and generates the separated results as a non-inverted output signal and an inverted output signal. To this end, the data separator 50 includes an inverter 51, a first separator 52, and a second separator 53.

Here, the inverter 51 is composed of a PMOS transistor MP30 and an NMOS transistor MN30. In addition, the input channel data SIN is inverted and the inverted result is output. The first separator 52 includes six series-connected inverters 52a to 52f to obtain the data NSIN whose phase is inverted with respect to the original data SIN. The inverters 52a to 52f each consist of one PMOS transistor and one NMOS transistor.

The second separator 53 includes five series-connected inverters 53a to 53e to obtain the non-inverting signal PSIN having the same phase as the original input data SIN. The inverters 53a to 53e are each implemented with one PMOS transistor and one PMOS transistor. As described above, the data separator 50 may separate the input data SIN into a non-inverted signal and an inverted signal, thereby improving the rise / fall time characteristics of the data.

Here, the number of inverters in the first separator 52 and the second separator 53 of the data separator 50 may be different. However, data transfer is made at high speed, and the delay time between the two separators is designed to be equal to each other. Therefore, the width and length of the transistor channel are set in consideration of the ratio of the size and the speed of the transistors constituting the first separator 52 and the second separator 53. Therefore, the time delay from the low frequency to the high frequency of the input data SIN is implemented to match.

The voltage / current conversion and current driver 55 of FIG. 5 obtains a voltage difference between the non-inverted output signal and the inverted output signal separated by the data separator 50, generates a current corresponding to the voltage difference, and generates the generated current. Is added as a bias current and a modulation current and output as a drive current LD_OUT. To this end, the voltage / current conversion and current driver 55 includes PMOS transistors MP42 to MP46, NMOS transistors MN42 and MN43, NPN transistors QN32 to QN33, and resistors R30 to R35. do.

In the voltage / current conversion and current driver 55, the NMOS transistors MN42 and MN43 constitute a comparator. In other words, the inverted output signal NSIN and the non-inverted output signal PSIN output from the data separator 50 are compared by the NMOS transistors MN42 and MN43 to obtain a voltage difference. At this time, the obtained voltage difference is converted into current and mirrored through the PMOS transistors MP44 and MP45 of the current mirror structure. For example, if the voltage level of the data output from the first separator 52 is higher than the output of the second separator 53, the current flowing through the PMOS transistor MP43 is increased by the level difference. In addition, when the voltage level of the data output from the second separator 53 is higher than the voltage level of the data output from the first separator 52, the current flowing through the PMOS transistor MP44 is increased by the level difference. At this time, the current determined by the input data SIN is controlled by the modulation current VMOD or the bias current VBIA obtained by the band gap circuit 300 and is output as the final driving current LD_OUT.

Subsequently, the laser driver 340 is described in detail. The modulation current VMOD is transmitted to the PMOS transistor MP42, and a current flowing in proportion to the size of the transistor of the MP42 flows. In addition, the bias current VBIA is transmitted to the transistor MP46, and a current flowing in proportion to the size of the transistor MP46 flows. It is assumed that the resistor R31 has a resistance value about twice as large as the resistor R33, and the PMOS transistor MP45 has a size five times larger than the transistor MP44. At this time, since the resistance value of the resistor R31 is twice the resistance value of the resistor R33, the current flowing through the transistor QN32 becomes twice the current flowing through QN31. The current doubled through QN31 is delivered through the PMOS transistor MP44. Here, the current delivered to the MP44 is increased by five times by the PMOS transistor MP45 having a five times size. Therefore, the current swing width of the input data SIN obtained by the modulation current VMOD, that is, the current flowing through the PMOS transistor MP45 is output as a 10 times increase in current compared to the VMOD. This modulation current is mixed with the DC current flowing in proportion to the size of the PMOS transistor MP46 by the bias current VBIA and output as the laser diode driving current LD_OUT.

6 (a) to 6 (c) and 7 (a) to 7 (c) are waveform diagrams for explaining the operation of the laser driver 340 shown in FIG. 5, and FIGS. 6 (a) and 7 ( a) represents the input channel data SIN. 6 (b) and 7 (b) show changes in signals NSIN and PSIN output from the first and second separators 52 and 53 of the data separator 50, respectively. 6C and 7C show changes in the laser diode driving current LD_OUT.

6 (b) and 7 (b), reference numerals 62 and 72 denote output signals NSIN of the first separator 52 and 64 and 74 denote output signals PSIN of the second separator 53. Indicates. 6 (c) and 7 (c), L65 and L75 denote swing ranges of the drive current LD_OUT, and L67 and L77 denote bias levels of the drive current LD_OUT.

Referring to FIG. 6, FIG. 6 illustrates a case in which the laser driver 340 receives a duty clock of 1.429 Gbps as input data SIN. At this time, the input data SIN has a duty width of 0.7 ns as shown in FIG. 6. In addition, the rise / fall time of the input data SIN is set to have a margin of 0.1 ns. As described above, FIG. 6 (b) is an output signal of the first and second separators 52 and 53, respectively, so that the two signals 62 and 64 have inverted phases.

Referring to FIG. 7, that is, FIG. 7 illustrates a case where a duty clock of 2 Gbps is received as the input signal SIN. In FIG. 7A, the clock has a duty width of 0.5 ns. As described above, the DC bias level and the current swing width of the input data SIN are determined by the bias current VBIA and the modulation current VMOD.

Hereinafter, a receiving apparatus of an optical transmission system according to the present invention will be described with reference to the accompanying drawings.

FIG. 8 is a block diagram specifically showing a receiving device 17 of the optical transmission system shown in FIG. Referring to FIG. 8, the reception device 17 includes an optical receiver 80, a data recovery and skew compensator 82, a descrambler 84, and a phase locked loop (PLL) 88.

The optical receiver 80 converts a signal that is converted into a current from an optical receiving diode such as a photodiode into a voltage, duty compensated, and level-converted and output as a digitalized signal. In this case, the output signal may be each R / G / B color signal, a control signal CON, and a clock signal CLK.

The PLL 88 inputs a clock signal CLK from the optical receiver 80 to generate a clock signal synchronized with the clock signal CLK, and provides the generated clock signal to each of the blocks. In addition, the PLL 88 uses the synchronized clock signal CLK to generate non-ovelapping clock signals CKP for data decompression and data decompression performed by the skew compensator 82. Create

The data deserializer and skew compensator 82 converts the serialized data compressed and transmitted by the transmitting apparatus 12 (see FIG. 1) into an original signal in response to a non-overlapping clock signal output from the PLL 88. In this case, the signal is released in parallel and compensated if skew occurs. That is, the data recovery and skew compensator 82 recovers the compressed data into parallel data of a predetermined bit and outputs the parallel data.

The descrambler 84 inputs signals of a predetermined bit restored by the data recovery and skew compensator 82, and accurately decodes the high level and low level sections by the DC balance information loaded at the head of the data bit. Determine. The data output from the descrambler 84 may be referred to as R / G / B output signals R_OUT, G_OUT and B_OUT, control signal CON_OUT, and clock signal CLK_OUT, respectively.

9 is a block diagram showing the optical receiver 80 shown in FIG. Referring to FIG. 9, the optical receiver 80 includes a current / voltage converter 920, an amplifier 930, a duty compensator 940, a power down controller 950, a bias circuit 960, and a level converter. 970 and a buffer unit 980. For convenience of description, the photodiode 900 and the parasitic element 910 are shown together.

The photodiode 900 shown in FIG. 9 converts an optical signal applied from the transmission device 12 (see FIG. 1) into an electrical signal through the optical transmission path 15 (see FIG. 1). The parasitic element unit 910 represents a block in which parasitic elements that are predicted when the external photodiode 900 transmits a current signal therein are modeled.

In the optical receiver 80 of FIG. 9, the bias circuit 960 receives a predetermined current from a power supply voltage to generate a first bias current B1 and a second bias current B2.

The current / voltage converter 920 sources the current in response to the first bias current B1, and converts and outputs a current signal applied through the photodiode 900 to a differential voltage signal. N1 and N2 of FIG. 9 represent differential voltage signal output lines of the current / voltage converter 920, respectively.

The amplifier 930 sources the current in response to the first bias current B1, amplifies an input signal converted into a differential signal, and outputs a differential amplified signal. N3 and N4 in FIG. 9 represent differential amplified signal output lines of the amplifier 930.

The duty compensator 940 sources the current in response to the first bias current B1, compares the output signal of the amplifier 930 with a predetermined reference voltage, and outputs a differential output signal corresponding to the comparison result. Create That is, the duty compensator 940 is configured as a comparator having a current summing structure to compensate for the duty of the input signal. Here, the output signal of the duty compensator 940 becomes a differential output signal represented by one input signal and an inverted signal of the input signal. This is to prevent a change in the duty of the output signal because the switching point can be changed when the dresshold voltage of the transistor changes with temperature and other conditions. N5 and N6 of FIG. 9 respectively represent differential output signal lines of the duty compensator 940.

The level converter 970 sources the current in response to the second bias current B2. In addition, the level converter 970 converts the voltage levels of the first and second output signals output from the duty compensator 940 and outputs a digitalized TTL (Transistor-Transistor Logic) level signal. N7 in FIG. 9 represents an output signal line of the level converter 970.

The buffer unit 980 buffers the signal output from the level converter 970 to generate a digitalized output signal OUT. In this case, the buffer unit 980 outputs a signal amplified by a predetermined level with respect to the input signal to improve the output driving capability. The output signal OUT of the buffer unit 980 may be R, G, B, a control signal CON, or a clock signal CLK.

In addition, the power down controller 950 controls the bias circuit 960 not to be driven in response to a power down control signal PDIN applied from the outside. Therefore, in the power down mode, other entire blocks are not operated to reduce power consumption.

FIG. 10 is a detailed circuit diagram of the optical receiver 80 shown in FIG.

The photodiode 900 shown in FIG. 10 is a model of an actual light receiving diode, for example, a photodiode. That is, the pulse generator P90 of FIG. 10 generates a current having the same shape as the current output from the photodiode. Capacitor C46 connected across the pulse generator P90 represents the parasitic capacitor component of the photodiode. The voltage source V _BAT is set to a voltage at the same level as VCC because the photodiode is actually connected to the power supply voltage VCC.

The capacitors C40 to C42 and C45, the resistors R40 and R41, and the coil L40 of the parasitic element unit 910 are predicted when an external photodiode 900 transmits a current signal therein. The resulting parasitic elements represent the modeled results. As in the present invention, in systems where data is processed at a rate of several Gbps, the circuit is designed in consideration of the influence on parasitic components. In addition, capacitor C45 represents a parasitic capacitor that may be represented by a pad to which a signal is input. In practical circuit design, however, it is implemented as a dummy pad that is implemented identically to the input pad to generate a differential voltage signal from the input current. As described above, the parasitic element unit 910 is a model in which parasitic components that may appear in the lead frame, the bonding wire, or the pad in the package assembly state when the receiving chip is integrated.

The current / voltage converter 920 of FIG. 10 converts the current signal applied through the parasitic element unit 910 from the photodiode 900 to a differential voltage signal. To this end, the current / voltage converter 920 includes NPN transistors QN50 to QN55 and QN58, resistors R50 to R62, and a capacitor C50. Transistors QN52 and QN53 output a current signal as a differential voltage. That is, the collector current of the QN52 is changed by the input current applied through the resistor R54, thereby changing the voltage of the first node N1. Here, the transistor QN53 generates a reference signal to generate a differential signal corresponding to the voltage of the first node N1. The voltage of the second node N2 in FIG. 10 becomes a reference signal. Here, the resistor R54 is provided for ESD protection. The capacitor C50 is provided to match the capacitor C46 of the photodiode portion 900. A resistor R53 coupled between the base of transistor QN52 and the emitter of transistor QN50 determines the gain during current / voltage conversion. In addition, the resistors R52 and R55 connected to the base of the transistor QN53 match the resistors R54 and R53, respectively. The transistors QN50 and QN51 are connected between the power supply voltage VCC and the collector of the transistor QN54 to receive a predetermined current from the power supply voltage VCC. The DC level of the signal input to the amplifier 930 is determined by the resistors R50 and R51. Transistors QN54, QN55 and QN58 serve as current sources for flowing a reference current in response to bias current B1 applied from bias circuit 960.

The amplifier 930 of FIG. 10 includes resistors R64 to R72 and NPN transistors QN56 to QN63. In the amplifier 930, the NPN transistor QN56 and the NPN transistor QN57 input the voltages of the first node N1 and the second node N2 as a base and differentially amplify them. At this time, the amplified result is output to the third node N3 and the fourth node N4 through the transistors QN63 and QN62, respectively.

For example, when the voltage of the first node N1 is higher than the voltage of the second node N2, the collector voltage of QN56 is relatively low. At this time, the collector voltage of QN57 is higher than before, increasing the base-emitter voltage of QN62, and increasing the voltage of fourth node N4. On the contrary, when the voltage of the second node N2 is higher than the voltage of the first node N1, the collector voltage of QN57 is relatively low. At this time, the collector voltage of QN56 is higher than before, so that the base-emitter voltage of QN63 is increased, and the voltage of third node N3 is increased. Here, the resistor R64 together with the resistor R66 determines the amplification gain of the amplifier 930. That is, the amplification gain with respect to the collector voltage of QN56 can be expressed as follows.

Here, r _eq56 represents the emitter resistance of the NPN transistor Q56. In addition, the transistors QN59 to QN61 and the resistors R67 to R72 in the amplifier 930 form a current source by the bias current B1 generated in the bias circuit 960.

The duty compensator 940 of FIG. 10 includes the resistors R73 and R74, the NPN transistors QN66 to QN71, the resistors R75 and R76, and the transistors QN64, QN65 and QN72 to form a current source. QN74) and resistors R77 to R86. That is, in the duty compensator 940, the transistors QN64, QN65, QN72 ˜ QN74 and the resistors R77 ˜ R86 serve as current sources for inputting the bias current B1. In addition, the transistors QN66 and QN67 and the transistors QN68 and QN69 each constitute two different comparators having a current summating structure.

Here, the voltage of the third node N3 and the voltage of the fourth node N4, which are outputs of the amplifier 93, are applied to the base of QN66 and the base of QN69, respectively. In addition, the voltage of the third node N3 is integrated by the resistor R75 and the capacitor C75 and applied to the base of the transistor QN67 as the first reference voltage. Referring to FIG. 10, the first reference voltage is defined as a voltage applied to the node N3a. Similarly, the voltage of the fourth node N4 is integrated by the resistor R76 and the capacitor C76 and applied to the base of the transistor QN68 as the second reference voltage. Similarly, the second reference voltage is defined as the voltage across the node N4a. Since the present invention operates at a speed of Gbps, the R and C values for determining the time constant are appropriately set in correspondence with the speed. In particular, the capacitors C75 and C76 are set to have a value of 40 pF or more.

As such, the comparison voltage of each comparator is set to an integral value for the input signal and is set to be proportional to the various input signals. In addition, the transistor QN70 having the output of the first comparator as a base input generates an output signal and applies it to the sixth node N6. Similarly, the transistor QN71 having the output of the second comparator as its base input generates an output signal and applies it to the fifth node N5.

More specifically, the operation of the duty compensator 940 is described. First, the first current I1 of the duty compensator 930 may be defined by the following equation.

Here, I _CQN66 represents the collector current of _QN66 , and I _SQN66 represents the saturation current of the transistor QN66. V _BEQN66 also represents the voltage between the base and emitter of QN66. The variables for Q68 are defined in the same way. Thus, I1 is defined as the sum of the collector current of QN66 and the collector current of QN68.

In addition, the current I2 can be represented by the following equation.

Here, I _CQN67 represents the collector current of _QN67 , and I _SQN67 represents the saturation current of the transistor QN67. V _BEQN67 also represents the voltage between the base and emitter of QN67. The variables for Q67 are defined in the same way. As such, I2 is defined as the sum of the collector current of QN67 and the collector current of QN69. Accordingly, the voltage applied to the resistor R73, that is, the base voltage of the transistor QN70 and the voltage applied to the resistor R74 may be obtained as follows.

As such, the voltage across R73 and R74 varies depending on the current values I1 and I2. Thus, the voltage between the base-emitter of the transistors QN70 and QN71 also changes. In other words, it is obvious that the potentials of the output nodes N6 and N5 vary depending on the currents I1 and I2.

For example, if the voltage of the third node N3 is at a level higher than that of the fourth node N4, the current I1 mostly flows through the transistor QN66. At this time, the collector voltage of QN66 is lowered, while the collector voltage of QN69 is relatively high. Therefore, more current flows through QN71, resulting in a higher voltage at the fifth node N5. On the other hand, when the voltage of the fourth node N4 has a higher level than the voltage of the third node N3, the current I2 mostly flows through the transistor Q67. At this time, the collector voltage of QN69 is low and the collector voltage of QN66 is high. Therefore, the voltage of the sixth node N6 is increased. In addition, the duty compensator 940 is implemented such that the duty of the output signal is accurately compensated by using the differential signals.

The bias circuit 960 of FIG. 10 includes resistors R87 to R91, NMOS transistors MN71 and MN72, and NPN transistors QN76 to QN78. That is, when power is applied, when the power-down control signal PDIN is not at the low level, the NMOS transistors MN71 and MN72 operate to turn on the transistor QN75. That is, the current flowing through the emitter of transistor QN75 is transmitted through transistor QN77. The collector current of transistor QN77 is generated as first bias current B1. In addition, the current flowing through QN77 is mirrored to transistor QN76 having a current mirror structure with QN77. On the other hand, the current flowing through the transistor MN71 is mirrored to the transistor QN78, and at this time, the current flowing through the QN78 becomes the second bias current B2. The second bias current B2 is applied as a bias current of the level converter 970 through the resistor R92.

In the present invention, the bias current is set so that the frequency response characteristic of the transistor can be maximized. In other words, the frequency response characteristics of the transistor depend on how the amount of current is set. Accordingly, the transistors are sized so that the current sources of each block that input the bias currents B1 and B2 flow the required current according to the function of each block. In addition, in order to operate at a high speed as in the present invention, the base resistance and the emitter resistance of each transistor are set so that the characteristics of the transistor itself can be maximized so that the current value is maximized.

The level converter 970 of FIG. 10 includes PMOS transistors MP70 to MP73, NPN transistors QN79 to QN84, and resistors R92 to R96. In addition, the level converter 970 digitalizes the level of the signal and converts the signal into a TTL level in order to process the analog signal as a digital signal. The resistors R92 and R93 of the level converter 970 and the transistor QN79 serve as current sources for repeating the bias current B2 applied from the bias circuit 960. In addition, the NPN transistors QN80 and QN81 of the level converter 970 have a differential structure for inputting voltages of the fifth node N5 and the sixth node N6 from the duty compensator 940. The PMOS transistors MP70 and MP71 have a current mirror structure and are switched on / off by the collector voltage of QN80. In addition, MP72 and MP73 also have a current mirror structure, and are switched on / off by the collector voltage of QN81. In addition, the transistors QN82, QN83 and QN84 and the resistors R94 to R96 cause a predetermined current to flow to the ground GND according to the current flowing in the MP71.

As described above, the level converter 970 receives the differential input signal and generates one output signal. Accepting the input signal in differential form here is intended to prevent the switching point from changing the duty of the output signal when the transistor's dresshold voltage changes over temperature and other conditions. At this time, the switched output generates the output voltage by turning on / off the PMOS transistors MP72 and MP73. The seventh node N7 of FIG. 10 represents an output node of the level converter 970.

First, when the voltage of the fifth node N5 is higher than the voltage of the sixth node N6, the current flowing through the QN80 of the level converter 970 is increased. Therefore, the collector potential of QN80 is lowered, and the PMOS transistors MP70 and MP71 are turned on. At this time, the current flowing through the MP71 causes a predetermined current to flow by the NPN transistors QN82, QN83, and QN84. Therefore, the voltage of the seventh node N7 becomes relatively low. On the contrary, when the voltage VN6 of the sixth node N6 is higher than the voltage VN5 of the fifth node N5, the current flowing through the QN81 of the level converter 970 is increased. Thus, the collector potential of QN80 is lowered, and the PMOS transistors MP72 and MP73 are turned on. At this time, the voltage of the output node N7 connected to the drain of the MP73 becomes high.

The power down controller 950 of FIG. 10 includes inverters 952 and 954 connected in series. In addition, the power down controller 950 is switched in response to a power down control signal PDIN applied from the outside. That is, in the power down mode, the entire circuit of the optical receiver 80 is set to the sleep mode in response to the power down control signal PDIN, and the consumption of the power supply voltage is minimized. That is, in the normal operation, the power down control signal PDIN is set to the high level, and the NMOS transistors MN70 and MN71 of the bias circuit 960 are turned on to perform normal operation. However, when the power down control signal PDIN is set to the low level, the bias circuit 960 cannot operate normally because the MN70 and the MN71 are turned off. Therefore, since the bias currents B1 and B2 cannot be generated, the entire circuit is switched to the sleep mode.

The buffer unit 970 of FIG. 10 includes inverters 91 to 95 connected in series. In FIG. 10, five inverters are output as signals having an inverse phase with respect to the input of the buffer unit 970. However, the input signal of the optical receiver 80 itself is output as an in-phase signal. In addition, although not specifically illustrated, internal transistor sizes constituting the inverters 91 to 95 are configured to increase in size by two times with respect to the inverter 91 at the front end, thereby improving the drive capability of the output signal. .

As such, the optical receiver 80 varies the current signal output from the photodiode to a voltage to enable digital processing. In addition, the optical receiver 80 is converted and buffered to a TTL level where the final output is full swing with respect to the supply voltage. In addition, the optical receiver 80 is designed so that the influence of parasitic elements is taken into account so that the dynamic range (DYNAMIC RANGE) for the current input is extended. In addition, for power saving, the optical receiver 80 is designed for low voltage and the rise / fall time and duty margin are taken into account during current / voltage switching. In addition, in order to prevent noise generated by the power supply voltage and the ground GND in the optical receiver 80 of FIG. 10, the power supply voltage VCC between the current / voltage converter 920 and the amplifier 930. And ground (GND) are separated from each other. For the same reason, the bias circuit 960 also includes a power supply voltage (VCC) line and a ground (GND) line used in the circuit for generating the first bias current B1 and the circuit for generating the second bias current B2. Are separated.

11 (a) and 11 (b) are diagrams for explaining input and output signals of the optical receiver 80 shown in FIG. FIG. 11A illustrates a current signal applied through the photodiode unit 900, and FIG. 11B illustrates a voltage signal having a TTL level output through the buffer unit 980.

Referring to Fig. 11A, the input current is a source clock signal having a peak value of 0 to 100uA, and the waveform is not clean, which indicates that the parasitic capacitor component of the photodiode is affected. FIG. 11B shows that the influence of parasitic elements is shaped and output as a waveform from which noise is removed.

12 (a) to 12 (d) are waveform diagrams for explaining the operation of the optical receiver 80 shown in FIG. 10, where 12 (a) shows an output signal of the parasitic element unit 910, and FIG. b) shows the output signal of the current / voltage converter 920, and 12 (c) and 12 (d) shows the output signal of the amplifier 930 and the integrated signal of the output signal.

13 (a) to 13 (c) are other waveform diagrams for explaining the operation of the optical receiver 80 shown in FIG. 10, FIG. 13 (a) shows an output signal of the duty compensator 940, FIG. 13B illustrates an output signal of the level converter 970, and FIG. 13C illustrates an output signal of the buffer unit 980.

10 to 13, an optical receiver 80 according to the present invention is described in more detail. First, when a current signal as shown in FIG. 10 (a) is applied from the photodiode unit 900, the parasitic element unit 910 is shown in FIG. 12 (a) by a parasitic component that may be generated in a lead frame or a pad. It appears as an unshaped waveform like That is, since the current signal that is primarily affected by the parasitic capacitor C46 in the photodiode 900 is again affected by the parasitic element 910, the input waveform appears as the worst form.

At this time, the current signal shown in FIG. 12 (a) is applied to the current / voltage converter 920 and is generated as a differential input signal as shown in FIG. 12 (b). VN1 in FIG. 12A shows a voltage across the emitter of the transistor QN50, that is, the first node N1. In addition, VN2 in Fig. 12A shows a reference signal for generating a differential input with respect to the input signal VN1. That is, the input signal VN1 and the reference signal VN2 shown in FIG. 12B are output as differential signals from the current / voltage converter 920. The differential signal is differentially amplified by the amplifier 930 and output to the third node N3 and the fourth node N4, respectively. The third node N3 and the fourth node N4 represent emitters of the NPN transistor QN63 of the amplifier 930 and emitter voltage of QN62, respectively.

The voltage NV3 of the third node N3 and the voltage VN4 of the fourth node N4 are applied as respective input signals of the two comparators of the duty compensator 940. The voltage waveform VN3 of FIG. 12C shows the first amplified output applied to the base input of the NPN transistor QN66 of the duty compensator 940. The voltage waveform VN4 of FIG. 12D shows the second amplified output applied to the base of the NPN transistor QN67 of the duty compensator 940. Referring to FIG. 12C, the voltage waveform VN3a becomes a reference voltage of the first comparator as a result of integrating the voltage VN3 of the third node N3 by the resistor R75 and the capacitor C75. 12 (d), the voltage waveform VN4a is a reference voltage of the second comparator as a result of integrating the voltage VN4 of the fourth node N4 by the resistor R76 and the capacitor C76. Becomes As such, in the present invention, the integrated value of the input signal is set to the reference voltage, so that the reference level is proportional to the various input signals. The input signal and the reference voltage shown in FIGS. 12 (c) and 12 (d) are respectively compared in different comparators and output from the fifth node N5 and the sixth node N6, respectively. The voltage waveforms VN5 and VN6 of FIG. 13A represent emitter voltages of the NPN transistor QN71 and QN70 of the duty compensator 940, respectively. 12 (c), 12 (d) and 13 (a), it can be seen that the voltage VN3 of the third node N3 and the voltage VN5 of the fifth node N5 are proportional to each other. . Referring to FIG. 13A, the two voltage signals VN5 and VN6 are crossed with respect to the level of the intermediate point. That is, the duty of the output signal of the output signal of the optical receiver 80 is determined by the crossing position of two signals differentially output from the duty compensator 940. Therefore, it is important that the differential signals be designed so that they cross exactly at the center point. That is, in the present invention, the relative comparability is performed by the differential signal in the duty compensator 940 to accurately determine the duty of the output signal. As shown in FIG. 13A, the output signals N5 and N6 of the duty compensator 940 that cross each other are applied to the bases of the input transistors QN80 and QN81 of the level converter 970, respectively. FIG. 13B illustrates a simulation result of the output signal of the level converter 970 and illustrates the voltage VN7 of the seventh node N7. Therefore, when the voltage VN5 of the fifth node N5 remains high based on the crossing point of FIG. 13A, the potential of the seventh node N7 illustrated in FIG. 13B is lowered. On the contrary, when the voltage VN6 of the sixth node N6 remains high based on the crossing point of FIG. 13A, the potential of the seventh node N7 shown in FIG. 13B becomes high. . In this way, the signal converted to the TTL level is buffered through the buffer unit 980, and the driving capability is improved to appear as a waveform of FIG. 13 (c).

As a result, as shown in Figs. 12 and 13, the analog current signal applied to the optical receiver 80 is converted into a final TTL level signal and converted into a digitalized output.

FIG. 14 is a block diagram illustrating a data restoration and skew compensator 82 of the reception apparatus illustrated in FIG. 8. The data recovery and skew compensation unit 82 includes first and second latch units 400 and 410 and a synchronization unit 420. The phase locked loop 88 is shown together for ease of explanation.

The phase locked loop 88 inputs the clock signal CLK through the optical receiver 80 and generates first to nth non-overlapping clock signals having a predetermined offset from each other so as not to overlap. . Here, n can be assumed to be nine.

The first latch unit 400 latches the received serial data in parallel in response to n non-overlapping clock signals to generate n bits of parallel data. For example, if n is 9, 9 bits of parallel data may be assumed to be 1 word. The latched parallel data is also output as state data having a time difference of a predetermined offset from each other. Here, the status data may be data of four channels for each R / G / B color signal and a control signal CON including a synchronization signal. In addition, for convenience of explanation, the R / G / B color signal will be referred to as information data. Depending on the system implementation, the type of state data may be implemented in N instead of four.

The second latch unit 410 latches the state data output from the first latch unit 400 in parallel in response to one non-overlapping clock signal having the largest timing margin among the n overlapping clock signals. The non-overlapping clock signal having a large timing margin is defined as an X (0 ≦ X ≦ n) th clock signal, that is, CKPX.

The synchronization unit 420 inputs the data latched by the second latch unit 410, and restores state data from which the synchronization signal is detected in response to a predetermined synchronization existence signal and an X-th non-overlapping clock signal. Output as data. Here, the synchronization existence signal DATA / SYNC is applied from the outside as a signal indicating whether a synchronization signal exists in the input data.

That is, the data recovery and skew compensator 82 shown in FIG. 14 releases the data compressed by the transmitter 12 of FIG. 1 into original parallel data. In addition, the data recovery and skew compensator 82 compensates for the occurrence of skew in the channel data received through the optical transmission path 15.

15A and 15B are waveform diagrams illustrating the operation of the apparatus shown in FIG. 14, and FIG. 15A illustrates a clock signal CLK received through the optical receiver 80. b) represents the serial channel data DATAIN received via the optical receiver 80.

FIG. 16 is a flowchart for describing a data restoration method performed in the apparatus shown in FIG. 14. The method for recovering data according to the present invention comprises obtaining N state data using serial data DATAIN and a clock signal CLK (steps 500 to 520), and determining which state data a synchronization signal is detected from. Steps 530 and 540 are performed.

A data restoration and skew compensation unit 82 and a data restoration method performed by the data restoration and skew compensation unit 82 according to the present invention will be described with reference to FIGS. 14 to 16.

First, the PLL 88 shown in FIG. 1 receives the clock signal CLK shown in FIG. 15A through the optical receiver 80. As shown in FIG. In addition, the PLL 88 generates n non-overlapping (where M is a positive integer of 1 or more) clock signals having a predetermined offset from each other so as not to overlap each other with respect to the clock signal CLK. (Step 500). Here, the predetermined offset may correspond to the width P18 of the unit bits in the serial data shown in FIG. 15B. For example, as described below, the first non-overlapping clock signal has the same phase and period as the clock signal CLK shown in FIG. 15A. Also, the second non-overlapping clock signal is defined as a signal in which the first non-overlapping clock signal is phase shifted by a width P18 of unit bits. As such, the PLL 88 may phase shift the first non-overlapping clock signal at a predetermined offset interval to generate n non-overlapping clock signals having a phase difference equal to an offset from each other.

After operation 510, the first latch unit 400 performs n + N−1 in parallel with the serial data DATAIN illustrated in FIG. 15B in response to n non-overlapping clock signals. A positive integer of 3 or more) is latched in units of bits (step 520). Here, serial data DATAIN means data in which information data for a sync word and an R / G / B color signal, each of which is n bits, is multiplexed. Therefore, serial data DATAIN is transmitted in series through the optical receiver 80 together with the clock signal CLK. Here, the synchronization signal represents each horizontal synchronization signal and vertical synchronization signal. For example, as shown in FIG. 15B, the serial data DATAIN is composed of information data P20 having n bits (d ₀ d ₁ ... D _n-3 d _n-2 d _n-1 ). The n-bit (d ₀ d ₁ ... d _n-3 d _n-2 d _n-1 ) synchronization structure 22 has a structure multiplexed. Therefore, one synchronization signal P22 is inserted for every predetermined number of pieces of information data.

After operation 520, the first latch unit 400 outputs N state data each consisting of n bits latched in operation 510 to the second latch unit 12 having a time offset of a predetermined offset from each other (operation 28). ). Here, the N pieces of state data may include first state data DD synchronized with the clock signal CLK illustrated in FIG. 2A, and at least one second state data lagging in phase with the first state data. DL), at least one third state data DE, etc. leading in phase than the first state data.

After operation 520, the second latch unit 410 outputs N state data output from the first latch unit 400, and has the largest timing margin among the n non-overlapping clock signals CKP0 to CKPn-1. In synchronization with the X-non-non-overlapping clock signal, latching is performed in parallel (operation 530). This is to provide the n state data output from the first latch unit 400 to the synchronization unit 420 in parallel at the same time. That is, although the first latch unit 400 shown in FIG. 14 operates in response to n non-overlap clock signals, the second latch unit 410 and the synchronizer 420 may operate only by the X-th non-overlap clock signal. It works.

After operation 530, the synchronization unit 420 responds to the synchronization existence signal DATA / SYNC and the X-th non-overlapping clock signal CKPX, and among the state data latched by the second latch unit 410. Is determined as the restored information data DATAOUT (step 540). Here, the synchronization existence signal DATA / SYNC is defined as a signal indicating whether the input data is information data such as an actual R / G / B color signal or a horizontal or vertical synchronization signal.

To facilitate understanding of the present invention, assuming that n = 9, that is, one word is 9 bits, and N = 3, the apparatus shown in FIG. 14 and the method shown in FIG. 16 are described as follows. do.

17 shows waveform diagrams of the clock signal CLK and the first to ninth non-overlapping clock signals CKP0 to CKP8 output from the PLL 88 shown in FIG. 14, respectively.

FIG. 18 is a diagram illustrating the first latch unit 400 illustrated in FIG. 14. The first latch unit 400 includes first to eleventh flip-flops 70a to 70k and first to third buffers 700, 710, and 720.

Each of the first to eleventh flip-flops 70a to 70k illustrated in FIG. 18 inputs a unit bit of the received serial transmission data DATAIN to the data input terminal D, and receives the first to ninth non-overlapping clocks. Each of the signals CKP0 to CKP8 is input to the clock terminal CK. For example, the first flip-flop 70a inputs the first non-overlapping clock signal CKP0 to the clock terminal CK, and inputs one bit of serially received data DATAIN to the data input terminal D. ).

The first buffer 700 inputs and buffers the positive outputs Q of the first to ninth flip-flops 70a to 70i. At this time, the buffered result is output as the second state data DL in response to the second non-overlapping clock signal CKP1. The second buffer 710 receives and buffers the positive outputs Q of the second to tenth flip-flops 70b to 70j. At this time, the buffered result is output as the first state data DD in response to the first non-overlapping clock signal CKP0. The third buffer 720 inputs and buffers the positive outputs Q of the third to eleventh flip-flops 70c to 70k. At this time, the buffered result is output as the third state data DE in response to the ninth non-overlapping clock signal CKP8.

As shown in FIG. 17, the first non-overlapping clock signal CKP0 has a phase and a period identical to the clock signal CLK, and the second non-overlapping clock signal CKP1 is united than the clock signal CLK. The phase is slower by the bit width, and the ninth non-overlapping clock signal CKP8 is faster in phase by a unit bit period than the clock signal CLK. Therefore, the first state data DD is out of phase with the second state data DL and is out of phase with the third state data DE by the unit bit width. As such, the reason for generating the second and third state data DL and DE having the phase difference by the unit bit width of the clock signal CLK is to compensate for the skew as described below.

19 is a block diagram illustrating the synchronization unit 420 illustrated in FIG. 14. The synchronizer 420 includes a selector 730, a state and selection signal generator 740, and a fourth buffer 750.

The selector 730 shown in FIG. 19 responds to the select signal S by selecting one of the first, second, and third state data DD, DL, and DE output from the second latch unit 410. After the selection, the selected result DATAOUT is output to the state and selection signal generator 740. At this time, the state and selection signal generator 740 responds to the first, second or third state data DD, IDL and IDE and the previously stored sync signal in response to the sync present signal DATA / SYNC. The predetermined bit pattern is compared. In addition, the state and selection signal generator 740 logically combines the result of comparison and the present state signal representing the present state to generate the selection signal S and the next state signal representing the next state. In this case, the selection signal S is applied to the selection unit 730, and the next state signal is applied to the fourth buffer 750. Here, the selection unit 730 selects the first state data DD in the initial state by the selection signal S, and if the first state data DD does not match the predetermined bit pattern, the second state data DL Select). Also, the selector 730 selects the third state data DE when the second state data DL and the predetermined bit pattern do not coincide with the selection signal S. FIG. To this end, the state and selection signal generator 740 logically combines the current state signal output from the fourth buffer 750 to generate the next state signal.

The fourth buffer 750 responds to the next non-overlapping clock signal CKPX, for example, the eighth non-overlapping clock signal CKP7, by outputting the next state signal output from the state and selection signal generator 72. Buffer The result buffered by the fourth buffer 750 is applied to the state and selection signal generator 740 as a current state signal. At this time, the restored information data DATAOUT corresponds to the state data selected by the selecting unit 730 when the synchronization signal and the predetermined bit pattern match.

20 is a detailed flowchart of step 540 shown in FIG. 16. Step 540 is performed by comparing first, second and third state data DD, DL, and DE with a predetermined bit pattern of a synchronization signal. Determining the information data DATAOUT (steps 800 to 880).

First, if the serial transmission data DATAIN transmitted through the transmission channel is a synchronization signal, the state and selection signal generator 740 shown in FIG. 19 matches the predetermined bit pattern of the sync word. It is determined whether to (step 800). For example, when the serial transmission data DATAIN is a synchronization signal, a high level synchronization present signal DATA / SYNC is input from the outside. If the serial transmission data DATAIN is information data, a low level synchronization present signal DATA / SYNC is input from the outside. At this time, the state and selection signal generator 740 is enabled only when the high level synchronization present signal DATA / SYNC is input. In addition, the state and selection signal generator 740 bypasses the current state signal as the next state signal when the low level synchronization existence signal DATA / SYNC is input.

If the first state data DD coincides with a predetermined bit pattern of the synchronization signal, the first state data DD is determined as the restored information data DATAOUT (step 860).

However, if the first state data DD does not match the predetermined bit pattern, the state and selection signal generator 740 determines whether the second state data DL matches the predetermined bit pattern (operation 820). . If the second state data DL matches the predetermined bit pattern, the second state data DL is determined as the restored information data DATAOUT (step 870).

On the other hand, if the second state data DL does not match the predetermined bit pattern, it is determined whether the third state data DE matches the predetermined bit pattern (step 840). If the third state data DE matches the predetermined bit pattern, the third state data DE is determined as the restored information data DATAOUT (step 880). However, if the third state data DE does not match the predetermined bit pattern, the process returns to operation 800. Further, even after the first, second or third state data DD, DL or DE is determined as recovered information data, the first, second or third state data DD, DL or DE matches the predetermined bit pattern. If no, the process proceeds to step 800.

As a result, if there is no skew between the serial transmission data DATAIN and the clock signal CLK, the first state data DD is determined as the restored information data. Further, if there is a skew of ± 1 bit period between the serial transmission data DATAIN and the clock signal CLK, the second or third state data DL or DE is determined as recovered information data.

In the above embodiment, it is assumed that n = 9 and N = 3. However, if n and N are varied, the device according to the present invention shown in Fig. 1 has a ± present between the serial transmission data DATAIN and the clock signal CLK. Skew more than two bit periods may be compensated.

According to the present invention, not only high-speed data transmission can be performed by replacing data transmission between a display device such as an LCD monitor and a PC with optical transmission, but also the effects of EMI noise or interference that may be caused by electrical cables. The effect is that you can not receive. In addition, long distance transmission can be performed without increasing the price, it can be easily applied to high-resolution display device. In addition, there is an effect that the input and output signals can be matched by designing the circuit with sufficient consideration of the influence of the parasitic elements.

Further, according to the present invention, when serial transmission data in which synchronization signals and information data are multiplexed are transmitted / received, even if skew occurs in the transmission channel, there is an effect that the information data can be stably recovered from the serial transmission data.

Claims (24)

In the optical transmission system for converting the video signal applied from the outside into an optical signal and transmitting, and restores the converted optical signal to the original video signal, A video controller separating the color signal and the horizontal / vertical synchronization signal from the video signal and transmitting the color signal and the horizontal / vertical synchronization signal in response to a predetermined data enable signal and a clock signal applied from the outside; A transmission device for skew compensation and compression of signals applied from the video controller and converting the compressed signal into a driving current; A transmission photodiode for converting the driving current output from the transmission device into an optical signal and outputting the converted optical signal; An optical transmission path composed of a predetermined number of channels for transmitting the optical signal; A reception optical diode converting an optical signal applied through the optical transmission path into a current and outputting the converted current signal; And Converting the current signal into a voltage and decompressing and skewing the converted signal to restore an original signal; The transmitting device, A phase locked loop which generates a clock signal synchronized with the externally applied clock signal and outputs the synchronized clock signal as an actual clock signal for data transmission; Skew compensation which receives data represented by each predetermined bit from the video controller as a plurality of channel data in response to the synchronized clock signal as a reference of data transmission, and compensates the skew generated between the channel data with respect to the clock signal. part; A scrambler that counts the number of high and low levels of the skew-compensated respective channel data, and adds the counted information to each channel data as direct current balance information; A data serializer configured to compress the scrambled channel data in response to the synchronized clock signal, and output the compressed result as channel data of one bit; And And an optical driver for receiving the compressed channel data and the clock signal into different channel data, converting the compressed channel data into a current signal, and outputting the converted current signal to drive the transmitting photodiode. Optical transmission system of optical transmission system. delete The method of claim 1, wherein the optical driver, A bias and modulation resistance variable unit including a bias resistor and a modulation resistor having a variable resistance value, and varying the bias resistance and the amount of current output by the change of the modulation resistance value; A band gap circuit for setting a band gap reference voltage that is always maintained at a constant value regardless of external changes, and varying a bias current or a modulation current by the set reference voltage and a change in current caused by the bias resistance and the modulation resistance; And And a laser driver which receives the respective channel data, converts it into a current signal, and outputs the modulation current generated in the band gap circuit and the bias current with the current signal as a driving current for driving an external optical element. Light transmission system, characterized in that. The method of claim 3, wherein the band gap circuit, Compensating the voltage of the first node to be kept constant according to the change of the voltage of the first node, which is a reference for setting the voltage, and calculating and amplifying the voltage applied to the band gap reference voltage and the modulation resistor, and the band gap. A band gap reference voltage generator configured to generate a result of the operation amplification of the reference voltage and the voltage applied to the bias resistor as a first output voltage and a second output voltage, respectively; The first output voltage and the second output voltage are fed back to the band gap reference voltage generator to maintain the first and second output voltages and the voltages applied to the modulation resistors and the bias resistors, and the modulation resistors or A bias and modulation current generator configured to vary the modulation or bias current by a bias resistance value; And And one or more switches that are switched in response to an externally applied power save control signal, wherein the power save switch converts the band gap reference voltage generator and the bias and modulation current generator into a sleep mode by a switching operation of the switches. And a control unit. The method of claim 3, wherein the laser driver, A data separator for separating the channel data into non-inverted signals and inverted signals, respectively, and generating the separated results as non-inverted output signals and inverted output signals; And A voltage / current conversion for obtaining a voltage difference between the non-inverted output signal and the inverted output signal to generate a current corresponding to the voltage difference, and outputting the generated current as the driving current in addition to the bias current and the modulation current. And a current driver. The method of claim 1, wherein the receiving device, An optical receiver for converting a current signal applied through the receiving photodiode into a voltage, and performing duty compensation and level conversion from the converted voltage to output a digitized signal as respective channel data; A phase locked loop for generating a clock signal synchronized with the clock signal included in the channel data and outputting the synchronized clock signal as an actual clock signal for data reception; A data recovery and skew compensator releasing channel data compressed and transmitted from the transmitting device in response to the synchronized clock signal, skew-compensating the released result and outputting the channel data as a predetermined bit of channel data; And And a descrambler configured to descramble a low level and a high level of the channel data in response to the DC balance information of each channel data output from the data recovery and skew compensator. The method of claim 6, wherein the optical receiver, A bias circuit configured to receive a predetermined current from a power supply voltage to generate a first bias current and a second bias current; A current / voltage converter for sourcing a current in response to the first bias current and converting a current signal output from the light receiving diode into a differential voltage signal; An amplifier for sourcing a current in response to the first bias current and amplifying the differential voltage signal to generate the amplified result as a first differential output signal and a second differential output signal; Sourced in response to the first bias current, and implemented with different comparators in a current summing structure in which output currents are added to each other, comparing the first differential output signal with a first reference voltage, A duty compensator for comparing first and second differential output signals with a second reference voltage to generate first and second output signals corresponding to the compared results; A level converter for sourcing a current in response to the second bias current, converting and digitizing a voltage level of the first output signal and the second output signal output from the duty compensator, and outputting the digitized signal; And And a buffer unit for buffering and amplifying the signal output from the level converting unit, and outputting the buffered result as the channel data of the digital signal.        The method of claim 6, wherein the optical receiver, And a power down controller for controlling the bias circuit not to operate in response to an externally applied power down control signal. The method of claim 6, wherein the data recovery and skew compensation unit, The data transmitted serially from the optical receiver is latched in units of n + N−1 (where N is a positive integer of 3 or more) in parallel in response to predetermined first through nth non-overlapping clock signals, and A first latch unit having a time difference of the predetermined offset therebetween and outputting N state data each consisting of n bits latched; A second latch unit configured to latch the N state data in parallel in response to an X (1 ≦ X ≦ n) non-overlapping clock signal having a largest timing margin among the first to nth non-overlapping clock signals ; And In response to a predetermined synchronization existence signal and the X-th non-overlapping clock signal, a synchronization unit for outputting, as the information data, the state data in which the synchronization signal is detected among the data latched in the second latch unit; , And the first to nth non-overlapping overlapping clock signals have a predetermined offset such that they are generated in the phase locked loop so as not to overlap each other. In the optical driver of the transmitter (Transmitter) for transmitting a predetermined channel data applied from the outside as an optical signal through the optical transmission path, A bias and modulation resistance variable unit including a bias resistor and a modulation resistor having a variable resistance value, and varying the bias resistance and the amount of current output by the change of the modulation resistance value; A band gap circuit for setting a band gap reference voltage that is always maintained at a constant value regardless of external changes, and varying a bias current or a modulation current by the set reference voltage and a change in current caused by the bias resistance and the modulation resistance; And And a laser driver which receives the respective channel data, converts it into a current signal, and outputs the modulation current generated in the band gap circuit and the bias current with the current signal as a driving current for driving an external optical element. Optical driver, characterized in that. The method of claim 10, wherein the band gap circuit, Compensating the voltage of the first node to be kept constant according to the change of the voltage of the first node, which is a reference for setting the voltage, and calculating and amplifying the voltage applied to the band gap reference voltage and the modulation resistor, and the band gap. A band gap reference voltage generator configured to generate a result of the operation amplification of the reference voltage and the voltage applied to the bias resistor as a first output voltage and a second output voltage, respectively; The first output voltage and the second output voltage are fed back to the band gap reference voltage generator to maintain the first and second output voltages and the voltages applied to the modulation resistors and the bias resistors, and the modulation resistors or A bias and modulation current generator configured to vary the modulation current or the bias current by a bias resistance value; And And one or more switches that are switched in response to an externally applied power save control signal, wherein the power save switch converts the band gap reference voltage generator and the bias and modulation current generator into a sleep mode by a switching operation of the switches. An optical driver comprising a control unit. The method of claim 10, wherein the laser driver, A data separator for separating the channel data into non-inverted signals and inverted signals, respectively, and generating the separated results as non-inverted output signals and inverted output signals; And A voltage / current conversion for obtaining a voltage difference between the non-inverted output signal and the inverted output signal to generate a current corresponding to the voltage difference, and outputting the generated current as the driving current in addition to the bias current and the modulation current. And a current driver. The method of claim 12, wherein the data separator, And the non-inverting output signal and the inverting output signal have the same delay time. An optical receiver of a receiving apparatus for receiving channel data converted into a current signal from an external optical receiving diode and restoring the digital signal to a digital signal.  A bias circuit configured to receive a predetermined current from a power supply voltage to generate a first bias current and a second bias current; A current / voltage converter for sourcing a current in response to the first bias current and converting a current signal output from the light receiving diode into a differential voltage signal; An amplifier for sourcing a current in response to the first bias current and amplifying the differential voltage signal to generate the amplified result as a first differential output signal and a second differential output signal; Source current in response to the first bias current, and are implemented with different comparators having a current summing structure in which output currents are added to each other, comparing the first differential output signal with a first reference voltage, A duty compensator configured to compare the second differential output signal and the second reference voltage to generate first and second output signals corresponding to the compared result; And Source level in response to the second bias current, and converting the voltage levels of the first output signal and the second output signal output from the duty compensator to digitalize and output the digitalized signal; Optical receiver characterized in that.        The method of claim 14, wherein the optical receiver, And a buffer unit for buffering and amplifying the signal output from the level converting unit and outputting the buffered result as digital channel data. The method of claim 14, wherein the optical receiver, And a power down controller for controlling the bias circuit not to operate in response to an externally applied power down control signal. The method of claim 14, wherein the duty compensator, Integrating the first differential output signal to a first reference voltage and integrating the second differential output signal to a second reference voltage. The method of claim 15, wherein the buffer unit, And a plurality of inverters connected in series, wherein the size of the transistors constituting the inverters is gradually increased in multiples of 2K, where K is a natural number greater than zero. delete delete delete delete delete delete

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