KR100604465B1 - Nitride-based semiconductor field effect transistors and manufacturing method thereof - Google Patents

Abstract

An electric field including a sapphire base substrate having a via hole, a metal layer electrically connected through the via hole, a plurality of nitride semiconductor layers formed on the sapphire base substrate, a source electrode, a drain electrode, and a gate electrode formed on the nitride semiconductor layer. Prepare an effect transistor.

Nitride Semiconductors, Field Effect Transistors, Sapphire, Via Hole, Integrated Circuits

Description

Nitride-based semiconductor field effect transistor and method of manufacturing the same {GaN-based high electron mobility transistor and method for manufacturing the same}

1 is a view showing the basic structure of a conventional nitride semiconductor transistor.

2 is a cross-sectional view of a nitride semiconductor field effect transistor according to a first embodiment of the present invention.

3 is a graph showing the etching rates of sapphire and GaN by ICP / RIE dry etching.

4 is an etching of a nitride semiconductor layer and sapphire according to the sulfuric acid ratio (volume ratio) when wet etching the sapphire and nitride semiconductor by using a mixture solution of sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ) as an etching This is a graph comparing speed.

5 is a sapphire substrate surface photograph after wet etching the sapphire substrate after forming a specific pattern on the sapphire substrate by a wet etching method.

6 is a surface photograph of a buffer layer after removing a sapphire substrate by a wet etching method.

7 is a cross-sectional view of a nitride semiconductor transistor according to a second embodiment of the present invention.

8A is a cross-sectional view of a nitride semiconductor transistor according to a third embodiment of the present invention.
8B is a plan view of a nitride semiconductor transistor according to a third embodiment of the present invention.

9 is a perspective view of a nitride semiconductor transistor according to a fourth embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

11 Sapphire substrate 12 Buffer layer (high resistance layer)

13 Channel Layer 14 Carrier Supply Layer

15 ohmic contact layer 16 source electrode

17 gate electrode 18 drain electrode

19 Ground Electrode 21 Air Bridge Electrode

22 Via Hole 23 Transistor

24 Nitride Semiconductor Layer 25 Bias Line

26 MIM Capacitors 27 Resistor

28 RF microstrip line 29 SiNx thin film

30 MIM capacitors 31 stub transmission line

32 Via Hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nitride semiconductor field effect transistor and a method of manufacturing the same.

Since the nitride semiconductor transistor uses a nitride semiconductor, which is a wide bang gap semiconductor, as a channel, high breakdown voltage, high speed, and high output characteristics are expected from the properties of the nitride semiconductor.
1 is a view showing the basic structure of a conventional nitride semiconductor transistor.
As shown in Fig. 1, the transistor is composed of three terminals of a source electrode, a drain electrode, and a gate electrode, and the magnitude of the drain current is controlled by the voltage of the gate. In other words, if the carrier formed in the channel is electrons, applying a negative voltage to the gate depletes the carriers in the channel and reduces the number of electrons flowing into the drain, which reduces the drain current, while applying a positive voltage causes the electrons to enter the channel. Since the number of electrons gathered and flowing to the drain increases, the drain current increases. Therefore, the field effect transistor is widely used as a switching element or an amplifier because the current flowing to the drain can be adjusted according to the voltage of the gate. Such transistors are frequently used as high speed switching devices, high frequency and high power amplifiers in the radio frequency domain.

Meanwhile, due to the material properties of wide-band-gap materials, nitride semiconductors have been spotlighted as materials for high-power / high-frequency electronic devices. A lot remains.

In other words, in order to realize high frequency and high output in the high frequency operation of the field effect transistor, since the high speed operation is basically limited by the carrier speed traveling through the channel, it is obvious that increasing the carrier moving speed is the first condition. It is very important to shorten the gate length because capacity greatly affects the responsiveness of the device. However, when the gate length is shortened and the voltage between the source and the drain becomes constant, the field strength increases. In this case, if the insulation strength of the semiconductor material is small, the voltage applied between the source and the drain is inevitably small. In other words, even if there is a minimum gate length determined by the material property of the dielectric breakdown field and the gate length is shortened further, the improved high speed operation cannot be expected. Carrier mobility is a good indicator of device material in low-field device operation, but carrier saturation-velocity by itself, which is a derivative of carrier saturation speed-field strength, is significant in high-field device operation. Therefore, the saturation speed becomes more important. In addition, the output power density P _out of the field effect transistor is substantially proportional to the accumulation of the drain current I _d and the source V _sd -drain voltage V _ds , and the source V _sd for achieving high output power. Since the) -drain voltage (V _ds ) is proportional to the dielectric breakdown field, it is necessary to improve the breakdown voltage characteristic. In particular, in order to achieve the high output characteristics of the field effect transistor using a sapphire-based nitride semiconductor, it is necessary to solve the heat dissipation problem of the sapphire substrate, but no progress has been made.

In other words, in order to reduce the occurrence of crystal defects in nitride semiconductor growth, sapphire having a similar lattice constant and crystal structure is used as a base substrate, and since sapphire is not easily insulated and thermally conductive and not easily processed, Nevertheless, it is not easy to manufacture field effect transistors and high power / high frequency electronic devices which are easy to dissipate heat.

Therefore, research to develop a method that can significantly improve the heat release is continuing in the art.

The present invention is to solve the above problems, when manufacturing a field effect transistor using a sapphire-based nitride semiconductor, by forming a via hole in the sapphire substrate using an etching technique to connect to the metal, to facilitate heat dissipation In addition, it is an object of the present invention to provide a field effect transistor that enables an integrated circuit of a micro stripline transmission line electrically connecting the ground electrode and the source electrode through a via hole of a sapphire substrate, and a method of manufacturing the same.

In the present invention to achieve the above object,

A sapphire base substrate having a via hole formed to penetrate up and down; A nitride semiconductor layer formed on the sapphire base substrate and including a buffer layer, a channel layer, a first carrier supply layer and an ohmic contact layer, and having a via hole penetrating up and down to be connected to the via hole of the sapphire base substrate; A metal film formed to contact a lower surface of the sapphire base substrate, a via hole of the sapphire base substrate, and a via hole of the nitride semiconductor layer; A field effect transistor including at least one source electrode, a drain electrode, and a gate electrode formed on the nitride semiconductor layer is provided.

The metal film may be electrically connected to any one of the buffer layer, the first carrier supply layer, and the ohmic contact layer, and more preferably, the metal film may be electrically connected to the source electrode. In addition, the source electrode and the drain electrode are preferably in ohmic contact with the nitride semiconductor layer, and the gate electrode is preferably in contact with the carrier supply layer exposed by recess etching the ohmic contact layer. . Also preferably, the at least one source electrode, the drain electrode, or the gate electrode may include a single layer of any one selected from Ti, Al, Pt, Au, Ni, Cr, or a plurality of layers of a metal combination including any one or more. It may be formed of an alloy. The plurality of source electrodes are preferably connected to each other by an air bridge electrode.

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The nitride semiconductor layer of the field effect transistor may further include a second carrier supply layer configured between the buffer layer and the channel layer, and the first carrier supply layer or the second carrier supply layer may be a rectifying contact layer. The buffer layer, the channel layer, the first carrier supply layer, the second carrier supply layer or the ohmic contact layer may be In _x (Ga _y Al _1-y ) N (1≥x≥0, 1≥y≥0, x + y> It is preferable that it is comprised from the nitride semiconductor which is 0). In addition, the first carrier supply layer and the ohmic contact layer are preferably an n-type semiconductor or a p-type semiconductor, more preferably, the n-type semiconductor is doped with Si and the p-type semiconductor is doped with Mg. Do.

In addition, the doping concentration of the first carrier supply layer, the second carrier supply layer or the ohmic contact layer is preferably 10 ¹⁵ / cm 3 to 10 ¹⁸ / cm 3, the buffer layer is a high resistance layer, the specific resistance of the buffer layer is 1 kcm It is preferable that it is from 10 ⁶ 6cm. In addition, the band gap of the channel is preferably smaller than the band gap of the first carrier supply layer or the second carrier supply layer.

The field effect transistor may be integrated with a bias line, a capacitor, a resistor, and a transmission line on the semiconductor layer.

In addition, the present invention, a. Forming a plurality of nitride semiconductor layers including a buffer layer, a channel layer, a carrier supply layer, and an ohmic contact layer on the sapphire base substrate, and sequentially forming a source electrode, a drain electrode, and a gate electrode on the nitride semiconductor layers; b. Lapping and polishing the sapphire based substrate; c. Forming a protective film on a surface of the base substrate; d. Photo-etching the passivation layer on the sapphire base substrate to partially expose the surface of the base substrate; e. Forming via holes by etching the exposed portions of the sapphire base substrate and the nitride semiconductor layers thereunder; F. And forming a metal film connected to at least one of the semiconductor layer and the source electrode through the via hole.

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In the method of manufacturing the field effect transistor, the method may further include forming a resistor, a capacitor, an inductor, and a transmission line on the nitride semiconductor surface after the step a. In addition, for the step a, the source electrode 16 and In order to form the gate electrode 17, a single layer of any one of Ni, Pt, Ti, Al, Au, Cr, or a combination of metals including any one or more thereof is deposited to include nitrogen or oxygen. It is preferred to further comprise the step of heat treatment to a temperature between 200 ° C and 700 ° C in a furnace of the atmosphere.

In the manufacturing method of the field effect transistor, in order to wrap and polish the sapphire base substrate for step b, at least one of CMP, mechanical polishing, and wet etching may be used, and the sapphire base substrate may be wrapped. And when polishing, the sapphire base substrate thickness is preferably 30 탆 to 300 탆 thick.

In addition, in the method of manufacturing a field effect transistor, a mixed solution of any one or a combination of sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ) when wet etching the steps d and e, Is preferably used as the main etchant.

In addition, in order to form a via hole of the sapphire base substrate in step e of the method of manufacturing a field effect transistor, any one of sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), or a combination thereof may be used. It is preferable to use a mixed solution as a main etchant, the etchant is more preferably used in a state heated to a temperature of 100 ℃ to 500 ℃. Alternatively, in step e, a mixed solution of any one of sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ) or a combination thereof may be used as an etching solution to form a via hole of the sapphire base substrate. It is desirable to combine wet etching with ICP / RIE or RIE dry etching. The wet etching is used to etch the sapphire base substrate, and the dry etching is more preferably used to etch the nitride semiconductor layer. More preferably, the wet etching is performed on the In _x (Ga _y Al _1-y ) N (1≥x≥0, 1≥y≥0, x + y> 0) nitride semiconductor layer Mg-doped the buffer layer. It is to take advantage of the stop layer, and may also take advantage of the buffer layer by growing an SiO ₂ layer as an etch stop of the wet etching to form a cluster of SiO _2.

In addition, the dry etching used in the method for manufacturing a field effect transistor is preferably at least one of BCL ₃ , Cl ₂ , HBr, Ar.

EMBODIMENT OF THE INVENTION Hereinafter, the field effect transistor by this invention and its manufacturing method are demonstrated in detail.

<First Embodiment>

2 is a cross-sectional view of a nitride semiconductor field effect transistor according to a first embodiment of the present invention. In order to grow an In _x (Ga _y Al _1-y ) N nitride semiconductor layer, metal organic chemical vapor deposition (MOCVD) was performed on a sapphire base substrate (Sapphire, Al ₂ O ₃ ) having a thickness of about 430 μm. It is available. At this time, the composition ratio of the nitride semiconductor layer is 1≥x≥0, 1≥y≥0, and x + y> 0. The nitride-based semiconductor layer may include metal organic chemical vapor deposition, liquid phase epitaxy, hydrogen vapor phase epitaxy, molecular beam epitaxy, and MOVPE. It is also possible to grow with (metal organic vapor phase epitaxy).

The growing nitride semiconductor layer may be grown in a single layer or in multiple layers according to the type of device to be manufactured, and any one or a plurality of elements of Si, Mg, and Zn groups may be added as impurities to have a conductive property. Si may be added to make an n-type nitride based semiconductor layer and Mg may be doped to make a p-type nitride based semiconductor layer. The doping concentration may vary depending on the type of device to be manufactured, and may be preferably about 1x10 ¹⁵ / cm ³ to 1x10 ²¹ / cm ³ .

That is, depending on the doping concentration, the nitride semiconductor is classified into a high resistor or a conductive material. In the case of a high resistor, the specific resistance is 1 내지 cm to In the case of 1x10 ⁶ cm <3> and electroconductivity, it is preferable to set it as 10 * cm <1> -10 <^4> cm <cm>.

As shown in FIG. 2, the field effect transistor includes a buffer layer (In _x (Al _y Ga _1-y ) N) 12, a channel layer 13, and a carrier supply layer (commutation) on the sapphire substrate 11. Contact layer) 14 and the In _x (Al _y Ga _1-y ) N nitride semiconductor layer of the ohmic contact layer 15 are grown. That is, each layer 12, 13, 14, 15 of the nitride semiconductor layer may be formed of In _x (Al _y Ga _1-y ) N and the composition ratio is 1≥x≥0, 1≥y≥0, x + y> 0. The carrier supply layer may also consist of a rectifying contact layer. In particular, the band gap of the channel layer is preferably smaller than the band gap of the carrier supply layer (or rectifying contact layer) 14 so that electrons can be easily formed in the channel layer. In the case of the channel layer, In _x (Al _y Ga _{1- y} ) either side of a well layer of In _x (Al _y Ga _1-y ) N or a dove hetero junction consisting of a barrier layer of In _x (Al _y Ga _1-y ) N on both sides of the well layer of N It can only have a single hetero junction of the In _x (Al _y Ga _1-y ) N barrier layer, and in the InN (~ 2.2eV) bandgap structure by controlling the composition ratio of In, Ga, Al To AlN (~ 6.4eV) bandgap structure. With such heterojunctions, the carrier supply layer can be placed above or below the channel and above and below the channel layer to increase the number of carriers formed in the channel.

The field effect transistor according to the first embodiment of the present invention constitutes a plurality of In _x (Al _y Ga _1-y ) N nitride semiconductor layers on the sapphire base substrate 11, and the nitride semiconductor layer is a buffer layer 12. , Channel layer 13, carrier supply layer (or rectifying contact layer) 14, n-type ohmic contact layer 15, where x and y are 1≥x≥0, 1≥y≥0, x It has a value of + y> 0. The n-type ohmic contact layer 15 is doped with a Si impurity at a concentration of ¹ × ^{10 15} cm ⁻³ to 1 × 10 ²¹ cm ⁻³ to have a resistivity of 1 μm to 1 × 10 ⁻⁴ μm, and the carrier supply layer 14 may contain Si impurities. It was doped at a concentration of ¹ × ^{10 15} cm ⁻³ to 1 × 10 ²¹ cm ⁻³ to have a resistivity of 1 μm cm to 1 × 10 ⁻⁴ μm cm.
As described above, when the nitride semiconductor layers 12, 13, 14, and 15 are grown on the sapphire substrate 11, any one of Ti, Al, Au, Ni, Pt, and Cr is selected on the ohmic contact layer 15. The source electrode 16 and the drain electrode 18 are formed from a plurality of layers or alloys of metals including at least one layer or any combination thereof, and the ohmic contact layer 15 is recess-etched by RIE or ICP / RIE dry etching. (recess etching) to expose the carrier supply layer (or rectifying contact layer) 14, a plurality of layers of a metal combination including any one or more than one of Ni, Al, Ti, Au, Pt, Cr or It is preferable to form the gate electrode 17 from the alloy. At this time, the source electrode 16 and the drain electrode 18 is a single of any one of Ti, Al, Ni, Pt, Au, Cr so as to have a low ohmic contact resistance with the n-type ohmic contact layer 15 doped with Si. After forming a layer or a plurality of layers or alloys of a metal combination including any one or more, it is preferable to heat-treat for 1 minute to 10 minutes at a furnace in a nitrogen atmosphere and a temperature of 200 ℃ to 700 ℃, more preferably Ti / Au, Ti / Al / Ti / Au, Ni / Al / Ti / Au, Ti / Au, can be deposited by a combination of Ni / Al / Pt / Au. In addition, the gate electrode 17 is formed of a single layer of any one of Ti, Al, Ni, Pt, Au, Cr, or a plurality of metal combinations or alloys including any one or more thereof, followed by a furnace in a nitrogen atmosphere and 300 Heat treatment for 1 minute to 10 minutes at a temperature of ℃ to 700 ℃ is preferred, more preferably Ti / Au, Ti / Al / Ti / Au, Ni / Al / Ti / Au, Ti / Au, Ni / Al It can be deposited by a combination of / Pt / Au and Al / Ti / Au. Since the line width of the gate electrode 17 affects the cutoff frequency of the field effect transistor, it is preferable to reduce the line width of the gate electrode 17 in order to fabricate ultrafast and ultrahigh frequency field effect transistors. It is desirable to reduce the parasitic components of the gate electrode 17, and for this purpose, the gate electrode 17 is more preferably a T-type gate. As such, in order to form the gate electrode 17 of the submicron or less, an electron beam etching technique (e-beam lithography) may be used, and more preferably, the line width of the gate electrode may be 0.15 μm or less. have. Then, when etching the sapphire base substrate by depositing SiO ₂ or SOG (spin-on glass) on the nitride semiconductor layer, it is desirable to reduce the damage of the nitride semiconductor layer.

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After the sapphire substrate 11 is wrapped to make a thin. Here, the lapping of the sapphire substrate 11 may use mechanical polishing using CMP (chemical mechanical polishing), RIE dry etching, ICP / RIE dry etching, alumina slurry (Al ₂ O ₃ slurry) or diamond slurry (diamond slurry). Alternatively, wet etching may be used in which a mixed solution of sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), or a combination thereof is used as an etching solution. At this time, any one of BCL ₃ , Cl ₂ , HBr, Ar, or a mixed gas thereof is used as an etching gas of ICP / RIE or RIE.

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Afterwards, as shown in FIG. 2, in order to form a via hole penetrating up and down on the sapphire base substrate, first, SiO ₂ for use as a mask is deposited on the sapphire substrate 11 and the lower part of the source electrode by photolithography. The sapphire substrate 11 is exposed. Thereafter, the sapphire substrate is etched by the following method.

The wet etching of the sapphire substrate 11 for forming the via hole is performed by sapphire substrate 11 by an etching solution in which sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ) are mixed at a temperature of 100 ° C. to 500 ° C. After the etching rate is measured, the sapphire substrate is immersed in the etching solution for a time for which a thickness of about 1 μm to 5 μm more than the thickness of the sapphire substrate 11 to be etched is etched.

The etching rate of the nitride semiconductor layer by the etching solution is 1/10 or less than that of the sapphire substrate 11. That is, since the etching selectivity of the nitride based semiconductor layers 12, 13, 14, and 15 with respect to the sapphire base substrate 11 is 10 or more, the nitride may be nitrided even when the sapphire base substrate 11 is fully etched. Since the etching speed of the semiconductor layers 12, 13, 14, and 15 is slow, there is little possibility that the nitride semiconductor layers 12, 13, 14, and 15 will be damaged.

On the other hand, it is preferable to maintain the temperature of the etching solution at 100 ℃ or more in order to shorten the etching time. The heating for maintaining the temperature of the etching solution above 100 ℃ may be a direct heating method to put the solution on the heater or directly contact the heater and the indirect heating method using light absorption.

Etching of the sapphire base substrate 11 for forming the via hole may use RIE or ICP / RIE technology in addition to wet etching using sulfuric acid and phosphoric acid as described above, and may be used by using the wet etching and dry etching in combination. Do. In order to quickly etch the sapphire substrate 11, it is desirable to increase the ICP and RIE power as much as possible, but care must be taken because it may damage the epi layer.

3 is a graph showing the etching rates of sapphire and GaN by ICP / RIE dry etching. As shown in FIG. 3, as a result of experiments at 100 sccm of BCl ₃ , 1800 W of inductive power, and 10 mTorr of chamber pressure, the sapphire and nitride semiconductors have increased etching rates as the ICP and RIE powers are increased. However, it can be seen that the etching ratio (GaN etching rate to Al ₂ O ₃ etching rate) between the sapphire and the nitride semiconductor is decreasing.

As a result, when etching the sapphire substrate 11 by a dry etching method such as ICP / RIE technology, it is difficult to stop the etching in the nitride semiconductor layer 12, 13. 14, 15 made of nitride-based semiconductor. Able to know. In addition, when dry etching is used, a relatively complicated process such as an optical analysis method or a residual gas analysis method is required to stop etching in the nitride semiconductor layers 12, 13. 14, and 15.

4 is an etching of a nitride semiconductor layer and sapphire according to the sulfuric acid ratio (volume ratio) when wet etching the sapphire and nitride semiconductor by using a mixture solution of sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ) as an etching This is a graph comparing speed. As can be seen in Figure 4, the sapphire etching rate for the nitride semiconductor of the solution of sulfuric acid and phosphoric acid is dependent on the mixing ratio (volume ratio) of sulfuric acid and phosphoric acid, and to some extent the etching rate increases as the ratio of sulfuric acid increases do. In addition, the etching rate of the nitride semiconductor (GaN) also depends on the mixing ratio of sulfuric acid, it can be seen that the etching selection ratio of the nitride semiconductor (GaN) and sapphire is 20 or more in a specific ratio.

As a result, it can be seen that the nitride semiconductor layers 12, 13. 14, and 15 are effectively used as the etch stop layer of the sapphire substrate 11.

5 is a sapphire substrate surface photograph after the pattern is formed on the sapphire substrate by the wet etching method and the sapphire substrate is etched by the wet etching method. 5, it can be seen that the etched slope and the bottom are very clean. In addition, when the sapphire substrate 11 was etched at a temperature of 325 ° C. for 20 minutes, the sapphire substrate 11 was etched at 22.4 μm to exhibit an etching rate of 1.1 μm / min. This etching rate is remarkable, and considering the mass production is not a problem at all, wet etching is not limited by the productivity of the equipment can be said to have many advantages over any method in terms of mass production.

Although not shown separately, when the sapphire substrate was etched with a mixture of sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ) for a pattern having various line widths, the etched depth was different according to the open pattern width. In the case of a pattern with a narrow line width, the etching depth is automatically stopped.

In other words, in wet etching, the sapphire substrate is oriented in wet etching and the etching depth depends on the patterned line width. The base substrate 11 of sapphire mainly used is the C plane of (0001), and when the wet etching is performed, the angle of the etching surface forms an inclined surface of 54 ° or 25 ° depending on the M plane, the R plane, and the A plane. . This phenomenon is due to the difference in etching speed between C surface of (0001), M surface of (10-10), R surface of (-1012) and A-etched facet surface of (11-20). Because. In other words, the surface orientation dependence of sapphire etching speed was found to be C plane> R plane> M plane> A plane, and as a result, the etch depth is determined by the open line width. This means that you can control the depth of etching by yourself. Using these results, it is possible to form a dicing line or cleve, brake line of the device at the same time as the via hole of the sapphire base substrate. In other words, when the (0001) face of the sapphire substrate was etched to a certain depth, the etched cross section had a V-grooved shape, which was cleaner than when any cleavage line was formed with any diamond pen. The dicing line is 20㎛ line width is enough, and during the via hole etching, the etch stops at a certain depth and automatically forms a scribing line. Therefore, after forming the via hole, a dicing line is formed to separate into individual chips without further processing. can do.
Figure 6 shows a surface photograph of the buffer layer after removing the sapphire substrate by a wet etching method.

As shown in FIG. 6, when the surface was etched under a microscope, the surface morphology was very clean and no large thickness deviation could be observed.

As described above, when the sapphire wet etching technology is applied to mass production, process conditions and epitaxial structure to secure the etching selectivity between the sapphire substrate 11 and the nitride semiconductor layers 12, 13. 14, 15 are ensured. It is preferable. In particular, the nitride semiconductor layers 12, 13. 14, and 15 may be used as an sapphire etch stop layer. In this case, the nitride semiconductor layer used as the etch stop layer may be In _x (Ga _y Al _1-y ). N (1≥x≥0, 1≥y≥0, x + y> 0) series can be used, preferably it is effective to increase the composition ratio of Al or to use p-type GaN doped with Mg . If necessary, an etch stop layer such as a protective film such as SiO ₂ or SiNx may be separately formed before the nitride semiconductor layer is formed on the sapphire substrate 11. In particular, SiO ₂ has a high wet etching selectivity to sapphire in the wet etching using a mixed solution of sulfuric acid and phosphoric acid as an etching solution.

Thereafter, a via hole connected to the sapphire via hole and penetrating up and down is formed in the nitride semiconductor layer to expose the source electrode 16. In this case, the nitride semiconductor layer may be etched using RIR or ICP / RIE, and as an etching gas of dry etching, one or more of BCl ₃ , Cl ₂ , Ar, and HBr may be used in combination. Thereafter, a metal film is deposited to cover the via holes of the sapphire substrate and the sapphire substrate and the via holes of the nitride semiconductor layer. In this case, the metal film is composed of a ground electrode 19 in contact with the source electrode 16. The ground electrode 19 is preferably formed of a single layer of any one of Ti, Al, Ni, Au, Pt, Cr, or a plurality of layers or alloys of metal combinations containing at least one, and Ti / Au, Pt / It is more preferable to use multiple layers of Au and Ti / Al / Pt / Au. As such, when the ground electrode 19 is formed, not only the heat dissipation is easy, but also the high frequency integrated circuit for the transmission line to be a micro strip line can be easily manufactured.
After the deposition of the ground electrode, the devices are separated individually.

The characteristics of the field effect transistor according to the first embodiment are summarized as follows.

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The source electrode 16, the drain electrode 18, and the gate electrode 17 are formed on the nitride semiconductor layer, and the gate electrode 17 is a carrier supply layer (or rectified) exposed by recess etching the ohmic contact layer 15. Contact layer) (14). The source electrode 16 and the drain electrode 18 are in ohmic contact with the ohmic contact layer 15, and the gate electrode 17 is in rectifying contact with the carrier supply layer. The source electrode 16, the drain electrode 18, and the gate electrode 17 may be a single layer of any one selected from Ti, Al, Pt, Ni, Au, Cr, or a plurality of layers of a metal combination including any one or more. It is formed of an alloy. In addition, the ground electrode 19 includes a ground electrode 19 contacting the ohmic contact layer or the source electrode 16 through the via hole formed in the sapphire substrate 11 to facilitate heat dissipation. The ground electrode 19 may include Ti, Al, Pt, It is formed of a plurality of layers or alloys of a combination of metals including any one layer of Au, Ni, Cr, or any one or more.

Second Embodiment

7 is a cross-sectional view of a field effect transistor according to a second embodiment of the present invention.
The field effect transistor according to the second embodiment of the present invention, like the first embodiment, constitutes a plurality of In _x (Al _y Ga _1-y ) N nitride semiconductor layers on the sapphire base substrate 11, and the nitride The semiconductor layer includes a buffer layer 12, a channel layer 13, a carrier supply layer (or rectifying contact layer) 14, and an n-type ohmic contact layer 15, where x and y are 1≥x≥0, 1≥y≥0 and x + y> 0. The n-type ohmic contact layer 15 is doped with a Si impurity at a concentration of ¹ × ^{10 15} cm ⁻³ to 1 × 10 ²¹ cm ⁻³ to have a resistivity of 1 μm to 1 × 10 ⁻⁴ μm, and the carrier supply layer 14 may contain Si impurities. It was doped at a concentration of ¹ × ^{10 15} cm ⁻³ to 1 × 10 ²¹ cm ⁻³ to have a resistivity of 1 μm cm to 1 × 10 ⁻⁴ μm cm. In the second embodiment, the portion for the growth of the nitride semiconductor layer is the same as or similar to that described in the first embodiment, and thus the detailed description is omitted.
As shown in FIG. 7, the field effect transistor according to the second embodiment forms a source electrode 16, a drain electrode 18, and a gate electrode 17 on the nitride semiconductor layer. In more detail, the source electrode 16 and the drain electrode 18 may include a single layer of any one selected from Ti, Al, Au, Ni, Pt, Cr, or a plurality of layers of a metal combination including any one or more. The gate electrode 17 is formed of an alloy, and the ohmic contact layer 15 is recess etched by RIE or ICP / RIE dry etching to expose the carrier supply layer (or rectifying contact layer) 14. After forming, it is preferable to form a single layer of any one of Ni, Al, Ti, Au, Pt, Cr, or a plurality of layers or alloys of a metal combination including at least one. Then, when etching the sapphire base substrate by depositing SiO ₂ or SOG (spin-on glass) on the nitride semiconductor layer, it is desirable to reduce the damage of the nitride semiconductor layer.
After the sapphire substrate 11 is wrapped to make a thin. Here, the lapping of the sapphire substrate 11 may use mechanical polishing using CMP (chemical mechanical polishing), RIE dry etching, ICP / RIE dry etching, alumina slurry (Al ₂ O ₃ slurry) or diamond slurry (diamond slurry). Alternatively, wet etching may be used in which a mixed solution of sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), or a combination thereof is used as an etching solution. At this time, any one of BCL ₃ , Cl ₂ , HBr, Ar, or a mixed gas thereof is used as an etching gas of ICP / RIE or RIE.
Subsequently, as shown in FIG. 7, in order to form a via hole penetrating up and down on the sapphire base substrate, first, SiO _2, which is used as a mask, is deposited on the sapphire substrate 11, and the lower part of the gate electrode is formed by photolithography. The sapphire substrate 11 is exposed. Thereafter, the sapphire substrate is etched by the following method.
The wet etching of the sapphire substrate 11 for forming the via hole is performed by sapphire substrate 11 by an etching solution in which sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ) are mixed at a temperature of 100 ° C. to 500 ° C. After the etching rate is measured, the sapphire substrate is immersed in the etching solution for a time for which a thickness of about 1 μm to 5 μm more than the thickness of the sapphire substrate 11 to be etched is etched.

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Thereafter, SiO ₂ is deposited on the sapphire substrate 11 to be used as a mask during etching, and the sapphire substrate 11 is exposed under the gate electrode 17 by photolithography. Thereafter, the sapphire substrate is etched to form a via hole in the following manner. Sapphire substrate 11 thickness by measuring the etching rate of the sapphire substrate 11 by the etching solution mixed with any one of sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ) at a temperature of 100 ℃ to 500 ℃ It is immersed in the etching solution for a time enough to etch a thickness of about 1 to 5 ㎛ further.
RIE or ICP / RIE technology may be used for etching the sapphire base substrate 11 to form the via holes, and the wet and dry etching may be used in combination. In order to quickly etch the sapphire substrate 11, it is desirable to increase the ICP and RIE power as much as possible, but care must be taken because it may damage the epi layer.

The nitride semiconductor exposed to the sapphire via hole is then etched using RIR or ICP / RIE to expose the buffer layer under the gate electrode. As the etching gas, it is preferable to use a combination of any one or more of BCl ₃ , Cl ₂ , Ar, HBr. Thereafter, a metal film is deposited to cover the via holes of the sapphire substrate and the sapphire substrate and the via holes of the nitride semiconductor layer. At this time, the metal film is composed of a ground electrode 19 in contact with the channel layer 13 of the nitride semiconductor layer. The ground electrode 19 is preferably formed of a single layer of any one of Ti, Al, Ni, Au, Pt, Cr, or a plurality of layers or alloys of metal combinations containing at least one, and Ti / Au, Pt / It is more preferable to use multiple layers of Au and Ti / Al / Pt / Au. As such, when the ground electrode 19 is formed, not only the heat dissipation is easy, but also the high frequency integrated circuit for the transmission line to be a micro strip line can be easily manufactured.
After the formation of the ground electrode, the elements are separated individually.

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The features of the field effect transistor according to the second embodiment are summarized as follows.

In the field effect transistor according to the second embodiment, the source electrode 16, the drain electrode 18, and the gate electrode 17 are formed on the nitride semiconductor layer as in the first embodiment. In addition, a via hole is formed in the sapphire substrate 11 and the nitride semiconductor layer under the gate electrode 17 to form a ground electrode 19 which contacts the semiconductor layer while covering the formed via hole.

Third Embodiment

8A is a cross-sectional view of the field effect transistor according to the third embodiment of the present invention, and FIG. 8B is a plan view of the field effect transistor according to the third embodiment. 8A and 8B, nitride semiconductor layers 12 and 13 including a buffer layer 12, a channel layer 13, a carrier supply layer 14 and an ohmic contact layer 15 on the sapphire substrate 11. , 14, 15, and at least one source electrode 16, a gate electrode 17, and a drain electrode 18 are formed on the nitride semiconductor layer. More specifically, as shown in FIG. 8A, the source electrode 16 and the drain electrode 18 are any one selected from Ti, Al, Au, Ni, Pt, and Cr on the ohmic contact layer 15. It is formed of a plurality of layers or alloys of metal combinations including layers or any one or more. The gate electrode 17 is recess-etched by the ohmic contact layer 15 by RIE dry etching or ICP / RIE dry etching to expose the carrier supply layer (or rectifying contact layer) 14. It is preferable to form a plurality of layers or alloys of any one single layer selected from among Ni, Al, Ti, Au, Pt, Cr, or a combination of metals including any one or more on the exposed carrier supply layer. In addition, as shown in FIG. 8A, after the gate electrode 17 is formed, the plurality of source electrodes 16 are connected to each other in an air bridge form 21.
After the formation of the source electrode, the gate electrode and the drain electrode, the sapphire substrate is wrapped and thinned.

In the field effect transistor according to the third embodiment, the growth of the nitride semiconductor layer and the lapping of the sapphire substrate are the same as or similar to those described in the first and second embodiments, and thus a detailed description thereof will be omitted.

Then, in order to form a via hole of the sapphire substrate, SiO ₂ is deposited on the sapphire substrate, and the sapphire substrate under the source electrode 16 is exposed by photolithography. The etching of the sapphire substrate for forming the via hole is performed by wet etching with an etching solution containing either sulfuric acid or phosphoric acid at a temperature of 100 ° C. to 500 ° C., or a mixture thereof. The sapphire substrate is immersed in the etching solution for a time to further etch 5 μm. In addition to the wet etching, RIE or ICP / RIE technology may be used to etch the sapphire base substrate 11 to form the via hole, or the wet and dry etching may be used in combination.

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The nitride semiconductor exposed to the sapphire via hole is then etched using RIR or ICP / RIE until the source electrode 16 is exposed. At this time, as the etching gas, it is preferable to use a combination of any one or more of BCl ₃ , Cl ₂ , Ar, HBr. In this manner, after the via holes of the sapphire substrate and the nitride semiconductor layer are formed, a metal film surrounding the sapphire substrate and the via hole of the nitride semiconductor layer and the sapphire substrate is formed to form the ground electrode 19. The ground electrode is preferably formed of a single layer of any one selected from Ti, Al, Ni, Au, Pt, Cr, or a plurality of layers or alloys of metal combinations including any one or more. The via hole configured as described above not only electrically connects the source electrode 16 and the ground 19, but also effectively emits heat generated from the field effect transistor to the outside, and provides a transmission line. By forming a micro strip line (micro strip line) it is possible to easily manufacture a high frequency integrated circuit.

Therefore, heat dissipation is facilitated to the outside by forming the ground electrode 19 penetrating the sapphire via hole and contacting the epi.
After the formation of the ground electrode, the elements are separated individually.

The features of the field effect transistor according to the third embodiment are summarized as follows.

A plurality of source electrodes 16, drain electrodes 18, and gate electrodes 17 are formed on the nitride semiconductor layer. A plurality of gate electrodes 17 are formed on the carrier supply layer (or rectifying contact layer) 14 by recess etching the ohmic contact layer 15. The plurality of source electrodes 16 and the drain electrodes 18 are in ohmic contact with the ohmic contact layer 15, and the plurality of source electrodes 16 are connected to each other by an air bridge. In addition, a via hole penetrating up and down is formed in the sapphire substrate and the nitride semiconductor layer under the source electrode, and a plurality of source electrodes are exposed through the via hole. In addition, a ground electrode is formed by forming a metal film covering the sapphire substrate, the via hole of the nitride semiconductor layer, and the sapphire substrate. The ground electrode is in electrical contact with the source electrode, and the ground electrode facilitates heat dissipation of the device.

Fourth Embodiment

9 is a perspective view of a field effect transistor according to a fourth embodiment of the present invention. As shown in FIG. 9, the field effect transistor according to the fourth embodiment includes a buffer layer 12, a channel layer 13, a carrier supply layer 14, or a rectifying contact layer and an ohmic contact layer 15 on a sapphire substrate. After growing the nitride semiconductor layer comprising a carrier supply layer to form at least one source electrode 16 and drain electrode 18 on the ohmic contact layer 15, the ohmic contact layer is recess-etched to expose At least one gate electrode 17 is formed on the substrate. After the gate electrode 17 is formed, it is preferable to connect the source electrodes 16 to the air bridge form 21. In the field effect transistor according to the fourth embodiment, the growth of the nitride semiconductor layer and the formation of the electrode are the same as or similar to those described in the first to third embodiments, and thus the detailed description thereof will be omitted.

In addition, as shown in FIG. 9, when fabricating field effect transistors for fabricating integrated circuits (ICs) on nitride semiconductor substrates, resistors 27, capacitors 26, 29, inductors, and transmission lines 28, which are passive elements, are fabricated. , 31) can be integrated at the same time.

Thereafter, at least one of SiNx, SiO ₂ , and spin-on-glass (SOG) is deposited to protect devices formed on the nitride semiconductor when the sapphire substrate is etched.

After depositing the protective film, the sapphire substrate is polished to a thickness of 50 µm to 300 µm. Here, the sapphire substrate 11 may be polished by using mechanical mechanical polishing (CMP), RIE dry etching, ICP / RIE dry etching, alumina slurry (Al ₂ O ₃ slurry), or diamond slurry (diamond slurry). , Wet etching using as a etching solution a mixed solution of at least one of sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ) or a combination thereof can be used. At this time, any one of BCL ₃ , Cl ₂ , HBr, Ar, or a mixed gas thereof is used as an etching gas of ICP / RIE or RIE.

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Subsequently, in order to form the via holes 22 and 32 of the sapphire substrate 11, SiO ₂ is deposited on the sapphire substrate, and the sapphire substrate 11 under the source electrode 16 is exposed by photolithography. The sapphire substrate for forming the via holes 22 and 32 may be etched using a mixed solution of at least one or a combination of sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ) at a temperature of 100 ° C. to 500 ° C. After the etching rate of the sapphire substrate 11 is measured in the wet etching using the etching solution, the sapphire substrate 11 is immersed in the etching solution for a time to be etched by a thickness of 0.1 μm to 5 μm more than the thickness to be etched.

In addition to the wet etching, the sapphire base substrate 11 for forming the via holes 22 and 32 may be etched using RIE or ICP / RIE technology, or the wet and dry etching may be used in combination. It is also possible to use. In addition, the via holes 22 and 32 may be formed not only in a circular shape but also in a polygonal shape, and may be formed in the lower portion of the gate electrode 17 in addition to the lower portion of the source electrode 16. When the gate electrode 17 is formed under the gate electrode 17, it is preferable that the electrode to be formed on the sapphire base substrate is in contact with only the high resistance layer of the buffer layer so as not to short-circuit the channel layer when forming the via hole of the nitride semiconductor layer.

Thereafter, the nitride semiconductor exposed to the sapphire via hole is etched using RIR or ICP / RIE to expose the source electrode 16. As the etching gas, it is preferable to use a combination of any one or more of BCl ₃ , Cl ₂ , Ar, HBr. Thereafter, a metal film formed to surround the sapphire substrate, the via hole of the nitride semiconductor layer, and the sapphire substrate is formed, the ground electrode 19 is formed, and then the devices may be separated into individual chips. The ground electrode is preferably formed of a single layer of any one selected from Ti, Al, Ni, Au, Pt, Cr, or a plurality of layers or alloys of metal combinations including any one or more. Here, the via hole not only serves to electrically connect the source electrode 16 and the ground 19, but also effectively discharges heat generated from the field effect transistor to the outside.

Therefore, by forming a ground electrode 19 through the sapphire via hole to contact the epi, heat dissipation can be easily performed to the outside, and the state of the transmission line can be formed as a micro strip line, thereby facilitating a high frequency integrated circuit. I can make it.

The characteristics of the field effect transistor manufactured in the fourth embodiment are as follows.

A plurality of sources 16, drains 18 and gate electrodes 17, resistors 27, capacitors 26 and 30, inductors and transmission lines 31 are formed on the nitride semiconductor layer, and gate electrodes 17 are formed. ) Is formed on the carrier supply layer (or rectifying contact layer) 14 exposed by recess etching the ohmic contact layer 15. The plurality of source and drain electrodes 16 and 18 are in ohmic contact with the semiconductor ohmic contact layer 15, and the gate electrode 17 is in Schottky contact with the semiconductor layer. The source electrode 16, the drain electrode 18, the transmission line and the gate electrode 17 are formed of a metal layer including any one layer or any one or more selected from Ti, Al, Pt, Ni, Au, and Cr. It is formed of multiple layers or alloys. In addition, the field effect transistor may be a ground electrode electrically connected to the semiconductor layer and the source electrode 16 through a via hole formed in the sapphire substrate 11 under the source electrode 16 to facilitate heat dissipation. 19), and the ground electrode 19 is formed of a plurality of layers or alloys of any one of Ti, Al, Pt, Au, Ni, and Cr, and is designed to facilitate heat dissipation.

In the present invention, since the via holes are formed in the sapphire substrate by using dry or wet etching, the productivity is greatly improved, and the ground electrode 19 is the source electrode 16 of the nitride semiconductor layer or the field effect transistor through the via hole passing through the sapphire substrate. ) Can be easily released to the outside heat. In addition, by utilizing the etching selectivity between the sapphire substrate and the nitride semiconductor can be easily improved the reproducibility of the process, and the standardized process is possible to facilitate mass production.

As described above, in the field effect transistor having the structure of the present invention, the via hole is formed in the sapphire substrate to expose the nitride semiconductor layer, thereby thermally forming the semiconductor layer and the via hole with a metal, thereby easily dissipating heat generated from the nitride semiconductor through the via hole. By connecting the source formed on the semiconductor layer through the via-hole, the circuit can be configured to have an integrated circuit having a transmission line of a micro strip line with a ground formed on the sapphire substrate. This enables not only scale down of the chip but also noise suppression of the signal, thus enabling the production of high performance high output / high frequency electronic devices and integrated circuits (MMIC).

In the present invention, the via hole is formed on the sapphire substrate or the semiconductor layer by using back surface polishing and dry or wet etching, so that even if the nitride semiconductor is grown on the sapphire substrate, via holes are formed in the sapphire substrate to form a ground electrode on the sapphire substrate. Since the process can be easily achieved, the integrated circuit fabrication and productivity can be greatly increased, and the reproducibility of the process can be easily improved by utilizing the etching selectivity between the sapphire substrate and the nitride semiconductor, and the standardized process is possible. Mass production becomes easy.

While the invention has been shown and described with respect to particular embodiments, it will be understood that various changes and modifications can be made in the art without departing from the spirit or scope of the invention as set forth in the claims below. It will be appreciated that those skilled in the art can easily know.

Claims (31)

A sapphire base substrate having a via hole formed to penetrate up and down; A nitride semiconductor layer formed on the sapphire base substrate, the nitride semiconductor layer including a buffer layer, a channel layer, a first carrier supply layer, and an ohmic contact layer, and having a via hole penetrating up and down to be connected to the via hole of the sapphire base substrate; A metal film formed to contact the lower surface of the sapphire base substrate, the via hole of the sapphire base substrate, and the via hole of the nitride semiconductor layer; And at least one source electrode, drain electrode, or gate electrode formed on the nitride based semiconductor layer. The field effect transistor of claim 1, wherein the metal layer is electrically connected to at least one of the buffer layer, the first carrier supply layer, and the ohmic contact layer. The field effect transistor of claim 1, wherein the metal layer is electrically connected to the source electrode. The field effect transistor according to claim 1, wherein the source electrode and the drain electrode are in ohmic contact with the ohmic contact layer. The field effect transistor according to claim 1, wherein the gate electrode is in a Schottky contact with a carrier supply layer exposed by recess etching the ohmic contact layer. The plurality of layers of claim 1, wherein the at least one source electrode, the drain electrode, or the gate electrode comprises any one single layer selected from Ti, Al, Pt, Au, Ni, Cr, or any one or more metal combinations. Or a field effect transistor, characterized in that formed of an alloy. delete The field effect transistor of claim 1, wherein the plurality of source electrodes are connected to each other by an air bridge electrode. delete delete The nitride carrier layer of claim 1, further comprising a second carrier supply layer formed between the buffer layer and the channel layer. And the first carrier supply layer or the second carrier supply layer is a rectifying contact layer. The method of claim 11, wherein the buffer layer, the channel layer, the first carrier supply layer, the second carrier supply layer or the ohmic contact layer is In _x (Ga _y Al _1-y ) N (1≥x≥0, 1≥y≥ A field effect transistor composed of a nitride semiconductor of 0, x + y> 0). The field effect transistor according to claim 1, wherein the first carrier supply layer and the ohmic contact layer are n-type semiconductors or p-type semiconductors. 15. The field effect transistor of claim 13, wherein the n-type semiconductor is doped with Si and the p-type semiconductor is doped with Mg. ^{15. The} field effect transistor of claim 14, wherein the doping concentration of the first carrier supply layer and the ohmic contact layer is in the range of 10 ¹⁵ / cm 3 to 10 ¹⁸ / cm 3. The field effect transistor according to claim 1, wherein the buffer layer is a high resistance layer, and the specific resistance of the buffer layer is in the range of 1 Ωcm to 10 ⁶ Ωcm. 13. The field effect transistor of claim 12, wherein a band gap of the channel is smaller than a band gap of the first carrier supply layer or the second carrier supply layer. The field effect transistor of claim 1, wherein the field effect transistor is integrated with a bias line, a capacitor, a resistor, and a transmission line on the semiconductor layer. a. Forming a plurality of nitride semiconductor layers including a buffer layer, a channel layer, a carrier supply layer, and an ohmic contact layer on the sapphire base substrate, and forming a source electrode, a drain electrode, and a gate electrode on the plurality of nitride semiconductor layers; b. Lapping and polishing the sapphire based substrate; c. Forming a protective film on a surface of the base substrate; d. Photo-etching the passivation layer on the sapphire base substrate to partially expose the surface of the base substrate; e. Forming via holes by etching the exposed portions of the sapphire base substrate and the nitride semiconductor layers thereunder; And f. And forming a metal film connected to at least one of the semiconductor layer and the source electrode through the via hole. The method of claim 19, And forming a resistor, a capacitor, an inductor, and a transmission line on the nitride semiconductor layer after step a. The method of claim 19, In step a, in order to form the source electrode and the gate electrode, a plurality of layers or alloys of metal combinations including any one or more than one of Ni, Pt, Ti, Al, Au, and Cr are deposited. And heat-treating at a temperature between 200 ° C and 700 ° C in a furnace containing nitrogen or oxygen. The method of claim 19, In step b, a method of manufacturing a field effect transistor, characterized in that the combination of at least one of chemical mechanical polishing (CMP), mechanical polishing, wet etching to wrap and polish the sapphire base substrate. The method of claim 19, In the step b, when the sapphire base substrate is wrapped and polished, the thickness of the sapphire base substrate is 30 μm to 300 μm. The method of claim 19, In the d and e steps, when wet etching, a mixed solution of any one of sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ) or a combination thereof is used as a main etching solution. A method of manufacturing a field effect transistor. The method of claim 19, In order to form a via hole of the sapphire base substrate in step e, a mixed solution of sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ) or a combination thereof is used as a main etching solution. Method for producing a field effect transistor, characterized in that. The method of claim 25, The etching solution is a method of manufacturing a field effect transistor, characterized in that used in a state heated to a temperature of 100 ℃ to 500 ℃. The method of claim 19, For step e, a mixed solution of any one of sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ) or a combination thereof is used as an etching solution to form via holes in the sapphire base substrate. A method for manufacturing a field effect transistor, comprising wet etching and ICP / RIE or RIE dry etching in parallel. The method of claim 27, The wet etching is used to etch the sapphire base substrate, and the dry etching is used to etch the nitride semiconductor layer. The method of claim 28, Mg-doped In _x (Ga _y Al _1-y ) N (1≥x≥0, 1≥y≥0, x + y> 0) nitride semiconductor layer is used as an etch stop layer of the wet etching. Method for manufacturing a field effect transistor. The method of claim 29, The method for producing a field effect transistor that utilizes the buffer layer as an etch stop layer for the wet etching of SiO ₂ by growth to form the cluster of SiO _2. The method of claim 27, The dry etching is a method of manufacturing a field effect transistor using at least one of BCL ₃ , Cl ₂ , HBr, Ar as an etching gas.

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