KR100602937B1 - Manufacturing method of nonvolatile memory device - Google Patents

Abstract

The present invention relates to a method of manufacturing a nonvolatile memory device, and more particularly, a NOR flash cell in which a manufacturing process uses a conventional floating gate device while having a minimum area without using a conventional SAS process or a SA-STI process. A method of manufacturing a nonvolatile memory device capable of implementing a stacked oxide NOR flash cell, which is much simpler and can effectively reduce manufacturing costs.

According to another aspect of the present invention, there is provided a method of manufacturing a nonvolatile memory device, comprising: forming a tunnel oxide film, a floating gate polysilicon, and a buffer oxide film on a front surface of a semiconductor substrate; Patterning the buffer oxide layer and the first floating gate in a column direction; Forming a first sidewall spacer on a sidewall of the first floating gate; Forming a source / drain region in the substrate; Forming a first silicide in the source / drain region; Forming an insulating film on the substrate and planarizing the gap between the first floating gates; Forming an ONO layer on the substrate; Depositing and patterning polysilicon on the substrate to form a control gate; And forming a second sidewall spacer on sidewalls of the first floating gate, the second floating gate, and the control gate, and selectively forming a second silicide on the control gate. It is achieved by the manufacturing method of.

Therefore, the method of manufacturing the nonvolatile memory device of the present invention does not use the SAS process or the SA-STI process by allowing the separator to be formed by the P well, the common source / drain, and the stacked gate without performing the device isolation process separately. It can effectively reduce the area occupied by NOR flash cells. In addition, the present invention can effectively reduce the area occupied by the NAND flash cell by effectively implementing a NOR flash cell without bit contact. In addition, by selectively forming silicide in a region used as a common source / drain, the common source / drain resistance can be effectively reduced, so that the number of word lines that can be connected to one bit line can be further increased, thereby further increasing the density. It works

NOR Flash, Buffer Oxide, First Floating Gate, Second Floating Gate, FG S / W Oxide Spacer, Gap Fill Oxide

Description

Method for fabricating of non-volatile memory device             

1 is a cross-sectional view of a flash memory cell according to the prior art.

2 is a view comparing the area of a conventional NOR flash unit cell with the area of a unit cell of a nonvolatile memory device of the present invention.

3A and 3B are circuit diagrams illustrating a cell array layout and a cell array of a nonvolatile memory device according to the present invention.

4A to 4G are cross-sectional views of a method of manufacturing a nonvolatile memory device in accordance with the present invention.

The present invention relates to a method of manufacturing a nonvolatile memory device, and more particularly, to minimize the area (4F ² ) without using a conventional Self-Aligned Source (SAS) process or a Self-Aligned STI (SA-STI) process. The present invention relates to a method of manufacturing a nonvolatile memory device capable of implementing a stacked oxide NOR flash cell having a manufacturing process much simpler than that of a conventional NOR flash cell using a floating gate device.

In general, semiconductor memory devices are classified into volatile memory and non-volatile memory. Most of volatile memory is occupied by RAM such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), and data can be input and stored when power is applied, but data cannot be saved because of volatilization when power is removed. Has On the other hand, nonvolatile memory, which is mostly occupied by ROM (Read Only Memory), is characterized in that data is preserved even when power is not applied.

At present, in terms of process technology, a nonvolatile memory device is classified into a floating gate series and a metal insulator semiconductor (MIS) series in which two or more dielectric layers are stacked in two or three layers.

Floating gate-type memory devices realize potential memory characteristics using potential wells, and are a simple stack-type EPROM (EPROM Tunnel Oxide) structure that is currently widely used as flash electrically erasable programmable read only memory (EEPROM). And a split gate structure in which one transistor includes two transistors.

On the other hand, the MIS series performs a memory function by using traps present at the dielectric bulk, the dielectric film-dielectric film interface, and the dielectric film-semiconductor interface. A typical example is the MONOS / SONOS (Metal / Silicon ONO Semiconductor) structure, which is mainly used as a flash EEPROM.

A method of manufacturing a flash memory cell of the prior art will be briefly described with reference to FIG. 1. The gate oxide film 12 is formed on the semiconductor substrate 10 on which the device isolation film 11 is formed, and the first polysilicon layer 13 is formed thereon. Is used as a floating gate. A dielectric layer 15 and a second polysilicon layer 16 are formed on the floating gate 13 to use the second polysilicon layer 16 as a control gate. The metal layer 17 and the nitride film 18 are formed on the control gate 16 and patterned in a cell structure to form a flash memory cell.

In the current NOR flash memory manufacturing process, the SAS process or SA-STI process is mainly used to minimize the NOR flash unit cell area. In addition, even if the SAS process, the SA-STI process, or both processes are used, bit contact must be formed so that the minimum area (4F ² ) of the NAND flash cell mainly used for data flash memory is not reduced.

Therefore, the present invention is to solve the problems of the prior art as described above, the manufacturing process is a conventional floating gate device while having a minimum area (4F ² ) without using a conventional SAS process or SA-STI process It is an object of the present invention to provide a method of manufacturing a nonvolatile memory device which is much simpler than a NOR flash cell that can reduce the manufacturing cost.

According to another aspect of the present invention, there is provided a method of manufacturing a nonvolatile memory device, comprising: forming a tunnel oxide film, a floating gate polysilicon, and a buffer oxide film on a front surface of a semiconductor substrate; Patterning the buffer oxide layer and the first floating gate in a column direction; Forming a first sidewall spacer on a sidewall of the first floating gate; Forming a source / drain region in the substrate; Forming a first silicide in the source / drain region; Forming an insulating film on the substrate and planarizing the gap between the first floating gates; Forming an ONO layer on the substrate; Depositing and patterning polysilicon on the substrate to form a control gate; And forming a second sidewall spacer on sidewalls of the first floating gate, the second floating gate, and the control gate, and selectively forming a second silicide on the control gate. It is achieved by the manufacturing method of.

Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

FIG. 2 is a view comparing the area of a NOR flash unit cell having a conventional bit contact with the area of a unit cell of a non-volatile memory device having no bit contact implemented by the manufacturing process of the present invention.

a shows the area of the NOR flash unit cell with bit contact when neither SAS process nor SA-STI process is used, and occupies approximately 10.5F ² .

b represents the area of the NOR flash unit cell with bit contact when the SAS process is used but the SA-STI process is not used, and occupies approximately 9F ² . Therefore, using the SAS process reduces the cell area by approximately 15% compared to 2a.

c represents the area of the NOR flash unit cell having a bit contact when the SAS process and the SA-STI process are used, and occupies approximately 6F ² . Therefore, by using both SAS and SA-STI processes, the cell area can be reduced by about 43% compared to 2a and by about 33% compared to 2b.

d represents the area of the stacked oxide NOR flash unit cell without bit contact according to the present invention and occupies an area of approximately 4F ² . This is the same as the area of the NAND flash unit cell using the conventional SA-STI process, which can reduce the cell area by about 62% compared to a, and the cell area by about 55% compared to b and compared to c. The cell area can be reduced by approximately 33%.

3A and 3B are circuit diagrams illustrating a cell array layout and a cell array of a nonvolatile memory device according to the present invention. 3A are cross-sectional views in the A-A ', B-B', and C-C 'directions according to the process sequence in FIG.

4A through 4E are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to the present invention.

First, as shown in FIG. 4A, a deep N well 502 and a P well 503 are formed on an entire surface of the P-type semiconductor substrate 501 by an ion implantation process. At this time, when forming the P well, threshold voltage adjustment and ion implantation for preventing punch-through are performed together. Subsequently, the tunnel oxide film 504 is grown on the substrate in the range of 50 kV to 150 kV, and the first floating gate 505 and the buffer oxide film 506 are sequentially deposited on the tunnel oxide film. The first floating gate may use a doped poly or may be doped through an ion implantation process after depositing the undoped poly. The deposition thickness of the first floating gate is preferably deposited in the range of 500 to 3000 Pa. The buffer oxide film is preferably deposited in the range of 100 to 1000 Pa.

Next, as shown in FIG. 4B, the buffer oxide film and the first floating gate are patterned in the direction B-B '.

Next, as shown in FIG. 4C, the LDD region 507 is formed on the silicon substrate in the open region through the ion implantation process using the patterned first floating gate as a mask. Next, after the oxide film is deposited on the entire surface of the wafer, sidewall spacers 509 are formed on the sidewalls of the first floating gate through blanket etching. After forming the sidewall spacer, an ion implantation process is performed again to form a source / drain region 508 on the silicon substrate in the open region. The silicide process is then performed to selectively form the silicide 510 only in the common source / drain regions of the open silicon substrate. Here, the source / drain regions may be formed before the sidewall spacers are formed without forming the LDD regions. The width of the sidewall spacers determines the width of the LDD and if the width of the sidewall spacers is too wide, the sidewall spacer width must be carefully determined because the width of the silicide formed in the common source / drain may decrease and increase the common source / drain resistance. . The sidewall spacer is preferably formed in the range of 100 to 1000 kPa.

Next, as shown in FIG. 4D, etching is performed by filling the voids between the first floating gates using an Atmospheric Pressure Chemical Vapor Deposition (APCVD) process or a High Density Plasma Chemical Vapor Deposition (HDP-CVD) process. Through the process, the gap-filled oxide film 511 is planarized and recessed to the first floating gate surface. In this case, a chemical mechanical polishing (CMP) process may be used instead of the etch back process.

Next, as shown in FIG. 4E, polysilicon is deposited on the entire surface of the substrate and a second floating gate 512 is formed through a patterning / etching process. The polysilicon deposited for forming the second floating gate may use a doped poly or may be doped through an ion implantation process after depositing the undoped poly. The deposition thickness of the second floating gate is preferably deposited in the range of 500 kV to 3000 kV. The second floating gate is to increase the coupling ratio, and when it is not necessary to increase the coupling ratio, the second floating gate forming process may be omitted. After forming the second floating gate as described above, the ONO layer 513 is deposited on the entire surface of the substrate.

Next, as shown in FIG. 4F, polysilicon is deposited on the entire surface of the substrate and the control gate 514 is formed through a patterning / etching process. The polysilicon deposited to form the control gate may use a doped poly or may be doped through an ion implantation process after depositing the undoped poly. The deposition thickness of the control gate is preferably deposited in the range of 1000 ~ 4000 ~.

Next, as shown in FIG. 4G, the sidewall spacers 515 are formed on the sidewalls of the stacked gates, and then the silicide 516 is selectively formed on the control gate (word line) through a silicide process. The process then implements the NOR flash cell without the bit contacts of the present invention using the same process as the conventional MOS transistor fabrication process.

As described above, the separator is formed by the P-well, the common source / drain, and the stacked gate without separately performing the device separator process, thereby effectively reducing the area occupied by the NOR flash cell without using the SAS process or the SA-STI process. Can be. In addition, the present invention can effectively reduce the area occupied by the NAND flash cell by effectively implementing a NOR flash cell without bit contact. In addition, by selectively forming silicide in a region used as a common source / drain, the common source / drain resistance can be effectively reduced, thereby increasing the number of word lines that can be connected to one bit line, thereby further increasing the density. .

It will be apparent that changes and modifications incorporating features of the invention will be readily apparent to those skilled in the art by the invention described in detail. It is intended that the scope of such modifications of the invention be within the scope of those of ordinary skill in the art including the features of the invention, and such modifications are considered to be within the scope of the claims of the invention.

Therefore, the method of manufacturing the nonvolatile memory device of the present invention does not use the SAS process or the SA-STI process by allowing the separator to be formed by the P well, the common source / drain, and the stacked gate without performing the device isolation process separately. It can effectively reduce the area occupied by NOR flash cells. In addition, the present invention can effectively reduce the area occupied by the NAND flash cell by effectively implementing a NOR flash cell without bit contact. In addition, by selectively forming silicide in a region used as a common source / drain, the common source / drain resistance can be effectively reduced, thereby increasing the number of word lines that can be connected to one bit line, thereby further increasing the density. . Therefore, when using the manufacturing process of the present invention it is possible to manufacture a NOR flash cell having both the advantages of NAND flash to minimize the area and the advantages of NOR flash fast operating speed.

Claims (10)

In the method of manufacturing a nonvolatile memory device, Forming a tunnel oxide film, a floating silicon polysilicon, and a buffer oxide film on a front surface of the semiconductor substrate; Patterning the buffer oxide layer and the first floating gate in a column direction; Forming a first sidewall spacer on a sidewall of the first floating gate; Forming a source / drain region in the substrate; Forming a first silicide in the source / drain region; Forming an insulating film on the substrate and planarizing the gap between the first floating gates; Forming an ONO layer on the substrate; Depositing and patterning polysilicon on the substrate to form a control gate; Forming a second sidewall spacer on sidewalls of the first floating gate and the control gate; And Selectively forming a second silicide in the control gate Method of manufacturing a nonvolatile memory device comprising a. The method of claim 1, The tunnel oxide film is a method of manufacturing a nonvolatile memory device, characterized in that formed in a thickness of 50 to 150Å. The method of claim 1, The first floating gate is a manufacturing method of a nonvolatile memory device, characterized in that formed to a thickness of 500 to 3000Å. The method of claim 1, The buffer oxide film is a method of manufacturing a nonvolatile memory device, characterized in that formed in a thickness of 100 to 1000Å. The method of claim 1, The silicide formed in the source / drain region is selectively formed only in a common source / drain region. The method of claim 1, And forming an LDD region on the substrate before forming the first sidewall spacers. The method of claim 1, The first sidewall spacers are formed in a thickness of 100 to 1000 Å. The method of claim 1, And depositing and patterning polysilicon on the substrate to form a second floating gate before forming the ONO layer. The method of claim 8, The second floating gate is a manufacturing method of a nonvolatile memory device, characterized in that formed to a thickness of 500 to 3000Å. The method of claim 1, The control gate is a manufacturing method of a nonvolatile memory device, characterized in that formed to a thickness of 1000 to 4000Å.

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