KR100600049B1 - Semiconductor memory device - Google Patents

Abstract

The present invention is to provide a semiconductor memory device that can adjust the setup / hold time of the signal without modification of the metal layer, the present invention for this control to generate the first to Nth control signal through the connection of the fuse Signal generating means; Default-control signal generating means for activating a default-control signal when all of the first to Nth control signals are deactivated; And delay amount adjusting means for delaying and outputting an input signal by the first to Nth control signals or the default control signal.

Fuse Options, Delay, Metal Layer, Yield, Setup / Hold Time

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}             

1 is a view for explaining the concept of the setup time and hold time.

2 is a diagram illustrating an external signal input device of a general semiconductor memory device.

3 is an internal circuit diagram of an address-delay unit of FIG.

4 is a diagram illustrating an external signal input device of a semiconductor memory device according to an embodiment of the present invention.

5 is an internal circuit diagram of a control signal generator.

6 is a diagram showing an implementation element of a default-control signal generation unit;

7 is an internal circuit diagram of a delay amount adjusting unit.

* Explanation of symbols for the main parts of the drawings

100: control signal generator

200: default control signal generator

300: delay amount adjusting unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to a semiconductor memory device capable of adjusting setup / hold time without modification of a metal layer.

In general, SDRAM (Synchronous Dynimic Random Access Memory) is developing with the goal of high speed and low power. In particular, as CPU speed increases, methods such as DDR and DDR2 are used to increase the processing speed of DRAM.

As described above, despite the increase in the processing speed of DRAM, the basic method of SDRAM which receives command signals, addresses and data from outside in synchronization with the rising of the clock and outputs the data in synchronizing with the rising of the clock remains unchanged. have.

For example, when an external chipset (ChipSet) applies control signals and addresses such as CLK, / RAS, / CAS, / CS, and / WE to the DRAM based on the rising of the clock, the DRAM is transferred through the internal buffer. This is converted into an internal signal. However, since the delay between the external chipset and the pins of the DRAM is different for each pin, the chipset says that the control signals and the address are synchronized to the clock and applied to the DRAM. It can't happen.

Therefore, the input and output signals are not synchronized to the rising of the clock accurately, but time is allowed between the rising edge of the clock and the clock. This time margin is called timing margin, which is specified by the specification.

1 is a view for explaining the concept of the setup time and hold time.

As shown in the figure, in order for the input signal / rasb to be recognized, a setup time (tIS) is set before the rising edge of the clock clk, and a hold time (tIH) after the rising edge of the clock. Must be satisfied.

In other words, the setup time defines the value that the input signal must come in for the clock rising in order to properly recognize the input as a signal, and the hold time defines the value that the signal must keep from the clock rising edge.

On the other hand, if the chipset applies CLK and control signals to the DRAM to meet the specifications, the DRAM receives the input signal by adjusting the delay of the input signal through the metal layer option to meet the specifications of the setup / hold time.

As described above, a process of converting an external input signal of a DRAM into an internal signal will be described in detail with reference to FIG. 2.

2 is a diagram illustrating an external signal input device of a general semiconductor memory device.

Referring to FIG. 2, an external signal input device of a semiconductor memory device includes a plurality of pads 12, 14, 16, and pads 12 for receiving respective (clk, add <0: M>, rasb) external signals. Buffers 22, 24, and 26 for full-swinging and outputting the output signals clkd, an <0: M>, rasbd at the power supply voltage levels 14, 16, and 14 to an internal power supply voltage level, and a clock. A clock trigger section 32, an address buffer section 24 and a control signal buffer section for generating a rising edge clock clkp3b synchronized with the rising edge of the output signal clk2n of the buffer section 22; A delay unit 34, 36 for delaying the output signal of 26 and an output signal of the address-delay unit 34 in response to the rising edge clock clkp3b to latch the internal-address (in_add <0: M>) latches the address-latch portion 42 for outputting the output signal ras2n of the control signal-delay portion 36 in response to the rising edge clock clkp3b. Control scene to output - and a latch (44).

Next, a process in which the semiconductor memory device receives an external signal will be described.

First, the external chipset applies the control signal rasb, the address add <0: M>, and the clock clk to the semiconductor memory device in the form of small-swing pulses from 0 to 0.5V. do. As such, the signals applied to the pads 12, 14, and 16 of the semiconductor memory device are full-swinged to the level of the power supply voltage through the buffer units 22, 24, and 26.

Next, the clock trigger unit 32 generates a rising edge-clock clkp3b by sensing the rising edge of the full-swinging clock clk2n.

The delay units 34 and 36 delay and output the output signals add21b <0: M>, ras2b of the address buffer unit 24 and the control signal buffer unit 26, respectively. Since each has a different delay from the chipset to the DRAM pin as described above, the chipset applies the signal prior to the clock and the semiconductor memory device is synchronized to the rising edge clock (clkp3b) through the delay. It is to adjust the delay amount of the signal.

Subsequently, the address latch unit 42 and the control signal latch unit 44 output an output signal of the corresponding address buffer unit 34 and the control signal buffer unit 36 in response to the rising edge clock clkp3b. add2n <0: M> and rasb2n are latched and output as the internal-address (in_add <0: M>) and the internal-control signal ras4b.

3 is an internal circuit diagram of the address-delay unit 34 of FIG. 2 and is provided in units of address bits. Since all of them are implemented by the same circuit device, the address add2n <0> will be described as an example.

Referring to FIG. 3, the address-delay unit 34 includes a plurality of unit delay elements 34_1,..., 34_X,..., 34_N connected in series between an input node and an output node, and each unit delay element 34_1,... And a plurality of metal options (mt_opt <0>, mt_opt <1>, ..., mt_opt <X>, ..., mt_opt <N>) connected between 34_X, ..., 34_N and an output node.

Therefore, when the output signal of the delay unit is not synchronized with the rising edge clock (clkp3b) and the latch unit does not recognize the signal, the number of unit delay elements through which the input signal passes through the metal option (mt_opt) is adjusted. Adjust the delay amount.

For reference, the control signal-delay section 36 also has the same circuit implementation as the address-delay section 34.

As described above, the semiconductor memory device according to the prior art is reproduced by modifying the mask forming the metal layer in order to adjust the delay amount so that the input signal meets the setup / hold time specification for the clock. , Has time loss.

In addition, even if the tested product is slightly out of specification, it must be discarded because the metal layer option must be adjusted.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a semiconductor memory device capable of adjusting the setup / hold time of a signal without modifying the metal layer.

According to an aspect of the present invention, there is provided a semiconductor memory device, including: control signal generation means for generating first to Nth control signals through connection of a corresponding fuse; Default-control signal generating means for activating a default-control signal when all of the first to Nth control signals are deactivated; And delay amount adjusting means for delaying and outputting an input signal by the first to Nth control signals or the default control signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

FIG. 4 is a diagram illustrating an external signal input device of a semiconductor memory device according to an embodiment of the present invention, which is compared with a conventional device (see FIG. 2) according to the related art. It can be seen that only the delay unit 400 and the control signal-delay unit 500 are changed. Therefore, the same reference numerals are used for blocks other than the delay units 400 and 500, and detailed description thereof will be omitted.

In addition, the address-delay unit 400 and the control signal-delay unit 500 differ only in the signals that are accepted for delay and the implementation elements and operations are the same, so only the address-delay unit 400 will be described as an example. .

Referring to FIG. 4, the address-delay unit 400 may include a control signal generator 100 generating first to Nth control signals ctr <0: N> through whether a corresponding fuse is connected, and a first signal. The default-control signal generator 200 for activating the default-control signal dft_ctr when the N th control signals ctr <0: N> are all deactivated, and the input signal add21b <0: M> Delay delay adjustment unit 300 for delaying and outputting the first to Nth control signals ctr <0: N> or the default-control signals ctr <0: N>.

The circuit implementation of each block will be described with reference to the following drawings.

FIG. 5 is an internal circuit diagram of the control signal generator 100. The control signal generator is provided for each control signal ctr <0: N>, and thus only the first control signal ctr <0> will be described.

The control signal generator 120 includes a fuse 122 connected between the power supply voltage VDD and the node n1, a capacitor C1 connected between the node n1 and the ground voltage GND, and a node n1. An NMOS transistor NM1 having an inverter I1 for inverting a signal caught by the signal, an output signal of the inverter I1 as a gate input, and having a drain-source path between the node n1 and the ground voltage GND; An inverter I2 for inverting the output signal of the inverter I1 and outputting the first control signal ctr <0> is provided.

Therefore, the control signal generator 120 deactivates the control signal ctr <0> to the logic level 'H' when the fuse 122 is connected, and when the fuse 122 is disconnected, the control signal ctr. Activate <0>) to logic level 'L'.

FIG. 6 is a diagram illustrating an implementation element of the default control signal generator 200. The default control signal generator 200 has first to N th control signals ctr <0: N> as inputs. The negative exclusive logic gate XNR1 is provided.

As described above, since the default-control signal generation unit 200 is implemented with the negative exclusive logic gate XNR1, when the control signal ctr <0: N> has at least one logic level, the default-control signal dft_ctr ) Is deactivated to a logic level 'H', and when all control signals ctr <0: N> have the same logic level, the default-control signal dft_ctr is activated to a logic level 'L'.

When the default control signal generator 200 activates the default control signal dft_ctr, fuse cutting is not performed during the initial operation, so that the input signal is delayed and output by the default delay amount, and all the control signals ctr < 0: N>) senses that they have the same logic level. Therefore, the default control signal generator 200 deactivates the default control signal dft_ctr when any control signal is activated by cutting the fuse.

In addition, when the default control signal dft_ctr is activated, the input signal is output with the delay amount expected by design.

7 is an internal circuit diagram of the delay control unit 300, the delay control unit 300 is a plurality of unit delay elements 310_1, ..., 310_X, ..., 310_N + 3 connected in series between the input node and the output node ) And a plurality of switches (SW_1, ..., SW_x, ...) controlled by the first to Nth control signals (ctr <0: N>) and the default-control signal, respectively, and connected between the connection node and the output node of the unit delay element. , SW_n + 3).

The delay amount adjusting unit 300 delays one input signal by a delay corresponding to the control signal and outputs the delayed signal. The delay amount adjusting unit 300 (see FIG. 7) is used to change the address (add21b <0: M>). In order to express a process in which all the bits are delayed, a bit amount delay controller is illustrated.

Next, the process of adjusting the delay amount of the input signal add21b <0: M> through the address-delay unit 400 will be described. For reference, consider only one bit of address.

First, since all the fuses of the control signal generator 100 are connected during the initial operation, the first to Nth control signals ctr <0: N> have a logic level 'H' and are inactivated. Accordingly, the default control signal generator 200 generates a default control signal dft_ctr in response to deactivation of all control signals ctr <0: N>.

Subsequently, since the switch SW_x controlled by the default control signal dft_ctr in the delay amount adjusting unit 300 is connected to the output node, the input signal add2n <0> is a unit located before the switch SW_x. It is output through the delay elements 310_1, and 310_x-1. That is, the input signal add2n <0> has a delay and the output in_add <0> as much as the delay of the unit delay elements 310_1 and 310_x-1 until the previous switch SW_x.

By measuring whether the setup / hold time of the signal (in_add <0>) output through the above process satisfies the specification, and if it does not satisfy, the delay amount to satisfy the measurement signal is measured and the corresponding control signal generator 100 ) Cut the fuse inside. Therefore, the corresponding control signal is activated and the delay amount adjusting unit 300 delays and outputs the input signal add2n <0> in response thereto.

For reference, the delay amount of the input signal in_add <0> due to activation of the default control signal dft_ctr is an expected value at design time.

As described above, since the semiconductor memory device having the delay unit according to the present invention can adjust the setup / hold time of the signal through the fuse, it is possible to modify a product that is out of specification in the wafer test, thereby improving the yield.

Meanwhile, in the above-described present invention, the delay unit adjusts the address or the delay amount of the control signal as an example. However, the present invention is not limited thereto and the present invention is not limited thereto. All parts are applicable.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

Since the semiconductor memory device according to the present invention can adjust the setup / hold time of the signal through the fuse option, it is possible to modify the product out of specification in the wafer test to improve the yield.

Claims (6)

delete Control signal generation means for generating first to Nth control signals through connection of a corresponding fuse; Default-control signal generating means for activating a default-control signal when all of the first to Nth control signals are deactivated; And A delay amount adjusting means for delaying and outputting an input signal corresponding to the first to Nth control signals or the default control signal; And said control signal generating means comprises N control signal generating sections for generating said first to Nth control signals. The method of claim 2, The N control signal generators, respectively A fuse connected between the power supply voltage and the first node; A capacitor connected between the first node and a ground voltage; A first inverter for inverting a signal applied to the first node; An NMOS transistor having a gate input as an output signal of the first inverter and having a drain-source path between the first node and a ground voltage; And a second inverter for inverting the output signal of the first inverter and outputting the same as the control signal. The method of claim 3, And said default-control signal generating means comprises an indeterminate logic logic gate having said first to Nth control signals as input. The method of claim 4, wherein And when the default control signal is activated, the input signal is output with a delay amount expected in design by default. The method of claim 5, The delay amount adjusting means, A plurality of unit delay elements connected in series between their input and output nodes, A plurality of switches controlled by the first to Nth control signals and the default-control signal, respectively, and connected between the connection node of the unit delay element and the output node; A semiconductor memory device comprising: a.

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