KR100583149B1 - Low voltage, high frequency internal column address strobe generation circuit - Google Patents

Abstract

The present invention relates to a stable internal column address strobe generation circuit in SDRAM, in particular during continuous write and read operations of low voltage and high frequency, and generates a cas control signal by receiving an internal clock pulse signal and a continuous operation flag signal. A read signal generation and latching unit in which a read signal is generated and latched in response to a signal generated internally by a cas control signal generator and a read command signal from the outside, and its output terminal is precharged in response to a read precharge signal. And a write signal input and latch unit for generating and latching a write signal in response to a signal generated internally by a write command signal from an external device, and having its output terminal precharged in response to a write precharge signal, and the cas control. A read precharge signal generator configured to generate the read precharge signal in response to a signal and a second write cas signal; A write precharge signal generator for generating a second write precharge signal in response to the cas control signal, and a write cas signal generation for generating the second write cas signal in response to the internal clock pulse signal and the first write cas signal; And a signal output unit receiving the cas control signal, the read signal, and the write signal to generate an internal column address strobe signal.

 CAS control signal, read signal, write signal, read precharge signal, write precharge signal, write cas signal, internal column address signal,

Description

Internal Column Address Strobe Generator for High Frequency and Low Power             

1 is a view showing an internal column address strobe generation circuit according to the prior art;

2 is a diagram showing a simulation result of an internal column address strobe generation circuit for a conventional low voltage and high frequency continuous read command signal.

3 illustrates an internal column address strobe generation circuit according to an embodiment of the present invention;

4 is a diagram showing a simulation result of an internal column address strobe generation circuit for a low voltage, high frequency continuous read command signal according to the present invention;

* Description of the main parts of the drawing

100: casing control signal generator

200: read signal generation and latch unit

300: write signal generation and latch unit

400: read precharge signal generator

500: write precharge signal generator

600: write cas signal generator

700: signal output unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to SDRAM (Synchronous DRAM), and more particularly to an internal column address strobe generation circuit in SDRAM.

The demand for high speed memory devices has led to the emergence of clock synchronous memory. The clock synchronous memory includes a memory such as SDRAM, DDR, etc. In the present invention, the clock synchronous memory will be abbreviated as SDRAM. The present invention has a technical background applied to such clock synchronization memory.

1 is a diagram illustrating an internal column address strobe generation circuit for performing a stable read / write operation of a conventional SDRAM.

Referring to FIG. 1, a conventional internal column address strobe generation circuit receives an internal clock pulse signal clkp4 and a continuous operation flag signal ybst, and receives the internal clock pulse signal clkp4 and the continuous operation flag signal ybst. ) Are all high, the cas control signal generator 10 generating the cas control signal icasp4 that is enabled, and the internal signal generated from the internal signal generated by the read command signal from the outside are read. A read signal generation and latch unit 20 for latching after generating a signal rdshield_b and an internal signal generated internally by a write command from the outside are input to generate a latch after generating a write signal wtshild_b in a low state. After receiving the signal generating and latching unit 30, the latched read signal rdshield_b and the latched write signal wtshield_b, a predetermined time delay occurs, the read signal rdshield_b and the write signal wtshield_b are applied. The precharge signal generator 40 generating the precharge signal pcg_shld_b for precharging, the cas control signal icasp, the read signal rdshield_b, and the write signal wtshield_b are all high. It is provided with a signal output section 50 for generating an internal column address strobe signal (internal_cas) that is enabled high only when enabled.

FIG. 2 is a diagram showing a simulation result of an internal column address strobe generation circuit for a conventional low voltage and high frequency continuous read command signal.

A detailed configuration and operation of the internal column address strobe circuit will be described with reference to FIGS. 1 and 2.

The cas control signal generation unit 10 outputs a negative logical gate NAND1 for negative logical multiplication of the continuous operation flag signal ybst and the internal clock pulse signal clkp4, and an output of the negative logical gate NAND1. It is composed of inverters INV1, INV2, and INV3 connected in series for inverting the signal and a predetermined delay, and is enabled when the continuous operation flag signal ybst and the internal clock pulse signal clkp4 are both high. The cas control signal icasp4 is generated.

The read signal generation and latch unit 20 includes a read signal generation unit 20A for generating the read signal rdshield_b and a latch unit 20B for latching the read signal rdshield_b.

The read signal generator 20A includes a first PMOS transistor MP1 connected to a source-drain path between a power supply voltage terminal and a read signal shield_b output terminal and receiving the precharge signal pcg_shld_b as a gate input; A first end of the first PMOS transistor MP1 is connected to a drain terminal thereof, and receives a cas signal cas4z (high active signal) generated internally by a read command signal from an external source through a gate input. A write enable signal we4 (high active) generated internally by a read command signal from an external device is connected to a source transistor of the MOS transistor MN1 and a source terminal of the first N-MOS transistor MN1. Signal < RTI ID = 0.0 > (NN2) < / RTI > MN2, and its drain terminal is connected to a source terminal of the second N & M transistor MN2, and a read command from the outside is applied to the source input. Inputs an inverted signal of the chip select signal (cs4z) generated internally by a call and a ras signal (ras4 (high active signal) generated internally by a read command from the outside through a gate input; And a latch portion 20B from a read signal rdshield_b output terminal which is a common drain terminal of the first PMOS transistor MP1 and the first NMOS transistor MN1. A first inverter (INV6) for receiving an output signal and inverting the output signal of the first inverter (INV6) and the output terminal is composed of a second inverter (INV5) connected to the input terminal of the first inverter (INV6) do.

Here, the read signal generation and latch unit 20 receives the cas signal (cas4z, high active signal), the write enable signal (we4, high active signal), and the las signal generated internally when a read command is received from the outside. When the ras4 (high active signal) and the chip select signal (cs4z, high active signal) are all input in a high state, the first, second, and third NMOS transistors MN1, MN2, and MN3 are turned on. The read signal rdshield_b, which is turned on and the source terminal of the third NMOS transistor MN3 is turned low, is outputted and latched by the latch unit 20B.

On the other hand, when the precharge signal pcg_shld_b in the high state becomes low after a predetermined time delay in response to the output signal of the latch unit 20B, the first PMOS transistor MP1 is turned on to read the read signal ( rdshield_b) is precharged to a high state.

The write signal generation and latch unit 30 includes a write signal generation unit 30A for generating the write signal wtshield_b and a latch unit 30B for latching the write signal wtshield_b.

The write signal generator 30A includes a first PMOS transistor MP2 and a first PMOS transistor MP2 connected to a power source voltage terminal and receiving the precharge signal pcg_shld_b through a gate terminal. Is connected to the drain terminal of the source and its source terminal, and receives the internal clock signal (clkp4) and the write cas signal (casp_wt) generated internally by a write command from the outside, and negates the negative logical gate (NAND2). The second PMOS transistor MP3, which is logically multiplied and receives the inverted signal to the inverter INV7, is connected to the ground power supply terminal and the drain terminal of the second PMOS transistor MP3, and the gate terminal is connected to the second PMOS transistor MP3. The first NMOS transistor MN4 is connected to the gate terminal of the MOS transistor MP3, and the latch unit 30B has a common configuration between the second PMOS transistor MP3 and the first NMOS transistor MN4. Write signal at drain stage (wtshi eld_b) The second inverter connected to the input terminal of the first inverter (INV9) and the output terminal of the first inverter (INV9) and the output signal of the first inverter (INV9) for receiving and inverting the output signal from the output terminal It consists of (INV8).

Here, the write signal generation and latch unit 30 is the second PMOS when both the write cas signal (casp_wt) and the internal clock pulse signal (clkp4) generated internally when a write command is received from the outside The transistor MP3 and the first NMOS transistor MN4 are turned on to output the write signal wtshield_b which is low and latched by the latch unit 30B.

Meanwhile, when the precharge signal pcg_shld_b in the high state becomes low after a predetermined time delay in response to the output signal of the latch unit 30B, the PMOS transistor MP2 is turned on and the write signal wtshield_b is turned on. Is precharged to a high state.

The precharge signal generator 40 is negative logic logic gate NOR1 for negating and logic the latched read signal rdshield_b and the write signal wtshield_b output from the latch units 20B and 30B and the negation. Inverters INV10, INV11, and INV12 connected in series for inverting and delaying the output signal from the logic sum gate NOR1, a source terminal and a drain terminal are commonly connected to a power supply voltage terminal, and a gate terminal is an output terminal of the inverter INV12. A negative logic gate NAND3 that receives a first input MOS transistor MP4 connected to the input signal, an output signal of the inverter INV12, and receives an output signal of the inverter INV10, and the negative logic product. An inverter INV13 for inverting the output signal of the gate NAND3, a second PMOS transistor MP5 having a source terminal and a drain terminal commonly connected to a power supply voltage terminal, and a gate terminal connected to an output terminal of the inverter INV13; Wow, the inver Negative logical gate NAND4 receiving one input signal from INV13 and receiving the output signal of inverter INV10, and two directly connected to invert the output signal of negative logical gate NAND4. The inverters INV14 and INV15 are configured to generate a low precharge signal pcg_shld_b after a predetermined delay after the read signal rdshield_b or the write signal wtshield_b is generated, and the read signal rdshield_b in the low state is generated. ) And the write signal wtshield_b in the low state is precharged high.

The signal output unit 50 includes a negative logic gate NAND8 and a negative logic gate NAND8 for negative logic multiplying the cas control signal icasp4, the read signal rdshield_b, and the write signal wtshield_b. And an inverter INV16 for inverting the output signal of the circuit, and enabling high only when the cas control signal icasp4, the read signal rdshield_b, and the write signal wtshield_b are all enabled high. To generate the internal column address strobe signal internal_cas.

If the low voltage and high frequency continuous read command is input, the read signal rdshield_b becomes low by the first read command and is low voltage. Therefore, if the precharge signal pcg_shld_b becomes low after a long delay, the read signal becomes low. (rdshield_b) is precharged to a high state and the read signal (rdshield_b) becomes low by a second new read command. At this time, the read signal (rdshield_b) is applied to the precharge signal (pcg_shld_b) when the first read command is performed. This causes a conflict between going high and going low due to the second new read command.

After the collision, the read signal rdshield_b goes high until the precharge signal pcg_shld_b goes high and the read signal rdshield_b does not completely block the cas control signal icasp. The internal column address strobe signal internal_cas, which should not be generated, is generated.

In FIG. 2, it can be seen that the internal column address strobe signal internal_cas is generated due to an internal collision of the read signal rdshield_b in the continuous read command.

The above problem is caused because the delay of the precharge signal is generated by the delay circuit when the continuous read or write command of the low voltage and high frequency is performed, and the clock period is reduced by the high voltage property. Also, even if the read signal rdshield_b or the write signal wtshield_b blocks the cas control signal icasp, the read signal rdshield_b and the write signal wtshield_b are independent of the cas control signal icasp. Because it is a signal, a margin is needed at the blocking portion.

The present invention has been made to solve the problems of the prior art as described above, when pre-charging the signal enabled in the low state by the low voltage, high frequency continuous read and write commands from the outside to the high state By precharging the precharge signal logically using an internal casing signal and a light strobe signal without using a delay circuit, it prevents the collision of the internal signal and suppresses the occurrence of unnecessary internal column address strobe signals. The purpose is to provide an internal column address strobe generation circuit.

According to an aspect of the present invention, there is provided an internal column address strobe generation circuit of an SDRAM, comprising: a cas control signal generation means for receiving an internal clock pulse signal and a continuous operation flag signal to generate a cas control signal; Read signal generation and latching means for generating and latching a read signal in response to a signal generated therein by a read command signal from an external source and precharging in response to a read precharge signal; Write signal input and latch means for generating and latching a write signal in response to a signal generated therein by a write command signal from the outside and precharging in response to the write precharge signal; Read precharge signal generation means for generating the read precharge signal in response to the cas control signal and the second write cas signal; Write precharge signal generation means for generating the write precharge signal; Write cas signal generating means for generating a second write cas signal in response to the internal clock pulse signal and the first write cas signal; And signal output means for receiving the cas control signal, the read signal, and the write signal to generate an internal column address strobe signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

FIG. 3 is a diagram illustrating an internal column address strobe generation circuit according to an embodiment of the present invention, and FIG. 4 is a simulation result of an internal column address strobe generation circuit for a low voltage and high frequency continuous read command signal according to the present invention. Drawing.

3 and 4, the internal column address strobe signal generation circuit of the SDRAM according to the present embodiment receives an internal clock pulse signal clkp4 and a continuous operation flag signal ybst, and a cas control signal icasp4. In response to the signal generated internally by the cas control signal generation unit 100 and a read command signal from the outside, a read signal rdshield_b is generated and latched and responds to the read precharge signal pcg_shld_b_rd. A write signal wtshield_b is generated and latched in response to a signal generated internally by the read signal generation and latch unit 200 at which the output terminal of the output terminal is precharged, and a write command signal from the outside, and the write precharge signal pcg_shld_b_wt In response to the write signal generation and latch unit 300 whose output terminal is precharged, the read precharge signal pc in response to the cas control signal icasp4 and the second write cas control signal casp4_wt. a read precharge signal generator 500 for generating g_shld_b_rd, a write precharge signal generator 500 for generating the write precharge signal (pcg_shld_b_wt) in response to the cas control signal and a write cas signal; A write cas signal generator 600 generating the second write cas signal casp_wt4 delayed in response to a clock pulse signal clkp4 and the first write cas signal casp_wt, and the cas control signal icaap4 And a signal output unit 700 which receives the read signal rdshield_b and the write signal wtshield_b and generates an internal column address strobe signal internal_cas.

The cas control signal generator 100 is configured to perform negative logic multiplication on the negative operation of the continuous operation flag signal ybst and the internal clock pulse signal clkp4 and output signals of the negative logic gate NAND6 and the negative logic gate NAND6. It consists of inverters INV17, INV18, and INV19 connected in series for the delay, and the cas control signal icasp4 enabled high when both the continuous operation flag signal ybst and the internal clock pulse signal clkp4 are high. Will occur).

The read signal generation and latch unit 200 generates a read signal rdshield_b and a read signal rdshield_b in response to an internal signal generated internally by a read command from the outside. It consists of a latch portion (200B) for latching.

The read signal generator 200A includes a source terminal connected to a power supply voltage terminal and a first PMOS transistor MP6 receiving a read precharge signal pcg_shld_b_rd from the read precharge signal generator 400 to a gate terminal. ), And a source-drain path is connected between the first PMOS transistor MP6 and the output terminal of the read signal rdshield_b, and a cas signal cas4z (high) generated internally by a read command from the outside through a gate input. A second PIM transistor MP7 receiving an active signal), a drain terminal of the second PMOS transistor MP7 and its drain terminal are connected, and a gate terminal thereof is connected to the gate terminal of the second PMOS transistor MP7. The first N-MOS transistor MN5 and its drain terminal are connected to the source terminal of the first N-MOS transistor MN5 and generated internally by a read command from the outside as a gate input. A second N-MOS transistor MN6 receiving the enable enable signal we4 and a high drain signal are connected to a source terminal of the second N-MOS transistor MN6, and an external read command is applied to the gate input. A third NMOS transistor MN7 that receives the ras signal ras4 (high active signal) generated therein and receives the chip select signal cs4 (high active signal) inverted by the inverter INV20 as a source input. It consists of.

In addition, the latch unit 200B inverts the output signal rdshield_b from the common drain terminal of the second PMOS transistor MP7 and the first N-MOS transistor MN5 to the first inverter INV21. It is inverted again by the second inverter INV22 and the output terminal of the second inverter INV22 is connected to the input terminal of the first inverter INV23.

The write signal generation and latch unit 300 may generate a write signal generation unit 300A and the write signal wtshield_b which generate the write signal wtshield_b by an internal signal generated internally by a write command from the outside. It consists of a latch part 300B for latching.

The write signal generator 300A includes a first PMOS transistor MP8 connected to a source voltage terminal and receiving a write precharge signal pcg_shld_b_wt from the write precharge signal generator 500. A source-drain path is connected between the drain terminal of the first PMOS transistor MP8 and the output terminal of the write signal wtshield_b, and the write cas signal generated internally by the internal clock pulse signal clkp4 and a write command from the outside. a second PMOS transistor (MP9), a ground power supply terminal, and the second P, which receive (casp_wt, high active signal) a negative logic multiplied by a negative logic gate (NAND7) and receive a signal inputted by the inverter INV23. A source-drain path is connected between the drain terminals of the MOS transistor MP9 and a gate terminal is formed of the first N-MOS transistor MN8 connected to the gate terminal of the second PMOS transistor MP9.

In addition, the latch unit 300B receives the output signal rdshield_b from the common drain terminal of the second PMOS transistor MP9 and the first N-MOS transistor MN8 and inverts the inverter INV24. The inverter is inverted back to the INV25 and the output terminal of the inverter INV25 is connected to the input terminal of the inverter INV24.

The write cas signal generator 600 negatively multiplies the internal clock pulse signal clkp4 and the first write cas signal (casp_wt) by a negative logic gate NAND7 and then converts the signal inverted by the inverter INV23. It consists of inverters INV29, INV30, INV31, and INV32 connected in series for a predetermined delay, and the second write cas signal casp4_wt output from the last stage inverter INV32 controls the read precharge signal pcg_shld_b_rd. That is, the second write cas signal casp4_wt is a predetermined delayed signal of the first cas signal casp_wt.

The read precharge signal generator 400 outputs the negative logic gate NOR2 and the negative logic gate NOR2 for negative logic on the cas control signal icasp4 and the write casca signal casp4_wt. The read precharge signal pcg_shld_b_rd is generated through an inverter INV26 for inverting and controls the precharge of the read signal rdshield_b.

The write precharge signal generator 500 receives the cas control signal icasp4 and generates the write precharge signal pcg_shld_b_wt through the inverters INV21 and INV22 connected in series, and frees the write signal wtshield_b. Control the charge.

The signal output unit 700 receives the cas control signal icasp4, the read signal rdshield_b, and the write signal wtshield_b, and performs a negative logical multiplication gate NAND8 and the negative logical multiplication gate for negative logic multiplication. And an inverter INV33 for inverting the output signal of NAND8, and is turned high when the cas control signal icasp4, the read signal rdshield_b, and the write signal wtshield_b are all enabled high. Outputs the internal column address strobe signal (internal_cas) that is enabled.

3 and 4, a continuous read operation will be described in detail.

When the first read command is input from the read signal generator 200A, the cas signal cas4z, the write enable signal we4, the ras signal ras4, and the chip select signal are generated internally. cs4) is input in a high state so that the second PMOS transistor MP7, the first N-MOS transistor MN5, the second N-MOS transistor MN6, and the third N-MOS transistor MN7 are turned on. On, the source terminal of the third N-MOS transistor MN7 is turned low, and the read signal rdshield_b is output in a low state and latched by the latch unit 200B.

Next, when the cas control signal icasp4 goes from high to low after the first read command is finished in the read precharge signal generator 400, the read precharge signal pcg_shld_b_rd also becomes low and the first blood The second MOS transistor MP7, the first, the second, and the MOS transistor MP6 are turned on and the read precharge signal pcg_shld_b_rd is low and the second new read command is not received. The third and MOS transistors MN5, MN6, and MN7 are turned off and the read signal rdshield_b that is low is precharged high.

In addition, referring to the continuous write operation, when the first write signal is input from the outside, the write signal signal casp-wt generated internally is inputted as high and the second PMOS transistor is input. MP9 and the first NMOS transistor MN8 are turned on so that the write signal wtshield_b is latched low.

Next, when the cas control signal icasp4 goes from high to low after the first write command is completed, the write precharge signal pcg_shld_b_wt also goes low and the first PMOS transistor MP8 is turned on. In the region where the write precharge signal pcg_shld_b_wt is low and the second new write command does not come in, the second PMOS transistor MP9 and the first N-MOS transistor MN8 are turned off to be low. wtshield_b) is precharged high.

As described above, the precharge signal generation according to the present invention is generated by the cas control signal and the write cas control signal output in response to the continuous operation flag signal without the delay of the read signal / write signal. In continuous read command execution, there is no conflict between precharging high after completion of the read command and going low by the new read command.

The cas control signal icasp and the write cas signal casp4_wt are also used to precharge the read signal rdshield_b enabled in a low state when the continuous read or write command is performed in a high state. When precharging the enabled write signal wtshield_b to a high state, a logic implementation without using a delay circuit may improve the column address access time because the margin for the delay circuit may not be considered. Since there is no collision between the region where the read precharge signal pcg_shld_b_rd is low and enabling the low state by a new read command, the column interrupt operation is stabilized.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention provides a column address access time by logically generating a precharge signal without using a delay circuit when performing low voltage and high frequency continuous read and write commands in the internal column address strobe signal generation circuit of the SDRAM. It is possible to perform stable read and write operation by preventing internal signal collision and generating unnecessary internal column address strobe signal.

Claims (10)

A stable internal column address strobe generation circuit according to low voltage, high frequency consecutive read and write commands in SDRAM, A cas control signal generation means for receiving an internal clock pulse signal and a continuous operation flag signal to generate a cas control signal; Read signal generation and latching means for generating and latching a read signal in response to a signal generated therein by a read command signal from the outside and precharging its output terminal in response to the read precharge signal; Write signal generation and latching means for generating and latching a write signal in response to a signal generated therein by a write command signal from the outside and precharging its output terminal in response to the write precharge signal; Read precharge signal generation means for generating the read precharge signal in response to the cas control signal and the second write cas signal; Write precharge signal generation means for generating the write precharge signal in response to the cas control signal; Write cas signal generating means for generating said second write cas signal in response to said internal clock pulse signal and a first write cas signal; And Signal output means for receiving the cas control signal, the read signal, and the write signal to generate an internal column address strobe signal SDRAM configured to include. The method of claim 1, The cas control signal generating means, A negative logic gate for negative logic multiplying the continuous operation flag signal and the internal clock pulse signal; And A number of inverters for inverting and delaying the output signal of the negative logic gate SDRAM comprising: a. The method of claim 1, The read signal generation and latch means, A read signal generator for generating a low read signal in response to an internal signal generated by a read command from the outside; And A latch unit for latching the read signal SDRAM comprising: a. The method of claim 1, The write signal generation and latch means, A write signal generator for generating a low write signal in response to an internal signal generated by an external write command; And A latch unit for latching the write signal SDRAM comprising: a. The method of claim 3, The read signal generator, A first PMOS transistor connected to a power source voltage terminal and receiving a read precharge signal from the read precharge signal generating means to a gate terminal; A second PMOS transistor connected to a source-drain path between a drain terminal of the first PMOS transistor and an output terminal of the read signal, and receiving a CAS signal generated internally by a read command from the outside to a gate input; A first N-MOS transistor having a drain end thereof connected to a drain end of the second PMOS transistor and a gate end thereof connected to a gate end of the second PMOS transistor; A second N-MOS transistor connected to a source terminal of the first N-MOS transistor and receiving a write enable signal generated therein by a read command from the outside as a gate input; And A third terminal connected to a source terminal of the second N-MOS transistor and receiving a lath signal generated internally by an external read command through a gate input, and receiving a chip select signal inverted by an inverter as a source input; An MOS transistor; SDRAM comprising: a. The method of claim 4, wherein The write signal generation unit, A first PMOS transistor connected to a source voltage terminal and receiving a write precharge signal from the write precharge signal generating means as a gate input; A source-drain path is connected between the drain terminal of the first PMOS transistor and the output terminal of the write signal, and a write cas signal generated internally by the internal clock pulse signal and a write command from the outside is connected to a negative logic gate. A second PMOS transistor which receives the signal inverted by the inverter after being negatively multiplied by the gate; And A first N-MOS transistor having a source-drain path connected between a ground power supply terminal and a drain terminal of the second PMOS transistor, and having a gate terminal commonly connected to the gate terminal of the second PMOS transistor. SDRAM comprising: a. The method according to claim 3 to 4, The latch unit, A first inverter receiving the read signal output from the common drain terminal of the second PMOS transistor and the first N-MOS transistor and outputting an inverted signal; And A second inverter connected to the input terminal of the first inverter by receiving the output signal of the first inverter SDRAM comprising: a. In claim 5, The read precharge signal generating means, A negative logical sum gate for negative logical sum of the second write cas signal and the cas control signal; And A number of inverters connected in series to invert the output signal of the negative logic gate SDRAM comprising: a. The method of claim 6, The write precharge signal generating means includes: And a predetermined number of inverters connected in series to receive the cas control signal. The method of claim 1, The signal output means, A negative logical gate to negatively multiply the cas control signal, the read signal, and the write signal; And A certain number of inverters for inverting the output signal of the negative logical gate SDRAM comprising: a.

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