[go: up one dir, main page]

KR100582370B1 - Method for manufacturing gate electrode using damascene process - Google Patents

Method for manufacturing gate electrode using damascene process Download PDF

Info

Publication number
KR100582370B1
KR100582370B1 KR1019990058739A KR19990058739A KR100582370B1 KR 100582370 B1 KR100582370 B1 KR 100582370B1 KR 1019990058739 A KR1019990058739 A KR 1019990058739A KR 19990058739 A KR19990058739 A KR 19990058739A KR 100582370 B1 KR100582370 B1 KR 100582370B1
Authority
KR
South Korea
Prior art keywords
film
word line
manufacturing
semiconductor device
polishing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019990058739A
Other languages
Korean (ko)
Other versions
KR20010057016A (en
Inventor
이상익
오찬권
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1019990058739A priority Critical patent/KR100582370B1/en
Publication of KR20010057016A publication Critical patent/KR20010057016A/en
Application granted granted Critical
Publication of KR100582370B1 publication Critical patent/KR100582370B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 워드라인의 부식을 방지하도록 한 반도체 소자의 제조 방법에 관한 것으로, 이를 위한 본 발명은 반도체기판 상부에 연마방지막을 포함하는 제1워드라인을 형성하는 제1 단계, 상기 연마방지막 및 제1워드라인의 양측면에 접하는 측벽을 형성하는 제 2 단계, 상기 측벽 및 제1워드라인을 포함한 전면에 평탄화 대상 절연막을 형성하고 열처리하는 제 3 단계, 상기 연마방지막이 드러나도록 산화막용 슬러리를 이용한 연마공정으로 상기 절연막을 연마하는 제 4 단계, 상기 연마방지막과 제1워드라인을 제거하여 상기 측벽내부를 노출시키는 제 5 단계, 상기 노출된 측벽내부에 게이트절연막, 배리어메탈, 전도막을 형성하고 패터닝하여 제2워드라인을 형성하는 제 6 단계를 포함하여 이루어진다.The present invention relates to a method of manufacturing a semiconductor device to prevent the corrosion of the word line, the present invention for this is the first step of forming a first word line including an anti-polishing film on the semiconductor substrate, the anti-polishing film and the A second step of forming sidewalls in contact with both sides of one word line, a third step of forming an insulating film to be planarized on the entire surface including the sidewalls and the first wordline and heat treatment, and polishing using an oxide film slurry to expose the anti-polishing film A fourth step of polishing the insulating film by a process, a fifth step of removing the anti-polishing film and the first word line to expose the inside of the sidewall, and forming and patterning a gate insulating film, a barrier metal, and a conductive film inside the exposed sidewall. And a sixth step of forming the second word line.

다마신 공정, 워드라인, 산화막슬러리, 화학적기계적연마Damascene process, word line, oxide slurry, chemical mechanical polishing

Description

다마신공정을 이용한 게이트전극의 제조 방법{METHOD FOR FABRICATING GATE ELECTRODE USING DAMASCENE PROCESS} Method for manufacturing gate electrode using damascene process {METHOD FOR FABRICATING GATE ELECTRODE USING DAMASCENE PROCESS}             

도 1a 내지 도 1d는 종래기술에 따른 반도체 소자의 제조 방법을 나타낸 도면,1A to 1D illustrate a method of manufacturing a semiconductor device according to the prior art;

도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 나타낸 도면. 2A to 2D illustrate a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

21 : 반도체 기판 22 : 패드산화막21 semiconductor substrate 22 pad oxide film

23 : 폴리실리콘 24 : 제1질화막23 polysilicon 24 first nitride film

24 : 측벽 26 : 평탄화대상절연막24 sidewalls 26 planarization target insulating film

27 : 게이트산화막 28 : 배리어메탈27: gate oxide film 28: barrier metal

29 : 전도막 30 : 제3질화막29: conductive film 30: third nitride film

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 다마신( Damascene) 공정을 이용하여 균일한 두께의 게이트전극을 형성하도록 한 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a gate electrode having a uniform thickness is formed using a damascene process.

이하 종래기술에 따른 반도체 소자의 제조 방법에 대해 첨부도면을 참조하여 설명하기로 한다.Hereinafter, a method of manufacturing a semiconductor device according to the prior art will be described with reference to the accompanying drawings.

도 1a 내지 도 1d는 종래기술에 따른 반도체 소자의 제조 방법을 나타낸 도면으로서, 듀얼다마신 공정을 이용한 게이트전극의 형성을 나타낸다.1A to 1D illustrate a method of manufacturing a semiconductor device according to the prior art, which illustrates the formation of a gate electrode using a dual damascene process.

도 1a에 도시된 바와 같이, 반도체 기판(11) 상부에 패드산화막(12)과 폴리실리콘을 증착한 다음, 상기 폴리실리콘 상에 감광막을 도포하고 노광 및 현상 공정으로 패터닝한다. 이어 상기 패터닝된 감광막을 마스크로 이용하여 상기 폴리실리콘을 선택적으로 제거하여 다수개의 워드라인(13a,13b,13c,13d)을 형성한다.As shown in FIG. 1A, a pad oxide layer 12 and polysilicon are deposited on the semiconductor substrate 11, and then a photoresist is coated on the polysilicon and patterned by an exposure and development process. The polysilicon is selectively removed using the patterned photoresist as a mask to form a plurality of word lines 13a, 13b, 13c, and 13d.

이어 상기 워드라인(13a,13b,13c,13d)들 상부에 측벽형성용 질화막을 증착하고 전면식각하여 질화막측벽(14)을 형성한 후, 상기 질화막측벽(14) 및 워드라인 (13a,13b,13c,13d)을 포함한 전면에 평탄화용 산화막(15)을 증착하고 열처리한다.Subsequently, a nitride layer for forming a sidewall is deposited on the word lines 13a, 13b, 13c, and 13d and then etched to form a nitride film side wall 14, and then the nitride film side wall 14 and the word lines 13a, 13b, The planarization oxide film 15 is deposited on the entire surface including 13c and 13d and heat treated.

도 1b에 도시된 바와 같이, 알칼리계열(Alkali)의 안정제가 첨가된 산화막연마용 슬러리를 이용하여 워드라인(13a,13b,13c,13d)이 드러날때까지 상기 평탄화용 산화막(15)을 연마한다.As shown in FIG. 1B, the planarization oxide film 15 is polished until the word lines 13a, 13b, 13c, and 13d are exposed using an oxide polishing slurry to which an alkali-based stabilizer is added. .

상기 워드라인(13a,13b,13c,13d)이 드러날때까지 산화막(15) 연마 공정을 진행하면 셀중심부 지역의 워드라인(13b,13c)이 다량 손실되므로써(16) 불균일한 두 께의 워드라인이 형성된다. When the oxide film 15 is polished until the word lines 13a, 13b, 13c, and 13d are exposed, a large amount of word lines 13b and 13c in the cell center region are lost (16), resulting in uneven thickness of the word lines. Is formed.

도 1c 에 도시된 바와 같이, 다마신(Damascene)공정을 이용하여 게이트전극을 형성하기 위해 워드라인(13a,13b,13c,13d)인 폴리실리콘과 패드산화막(12)을 제거하고, 도 1d에 도시된 바와 같이, 게이트산화막(17), 배리어메탈(18)을 증착한다. 이어 상기 배리어메탈(18) 상부에 게이트전극용 전도막으로서 텅스텐을 증착한 다음, 리세스(Recess)하면 다수개의 게이트전극(19)이 형성된다.As shown in FIG. 1C, the polysilicon and the pad oxide film 12, which are word lines 13a, 13b, 13c, and 13d, are removed to form a gate electrode using a damascene process. As shown, the gate oxide film 17 and the barrier metal 18 are deposited. Subsequently, a plurality of gate electrodes 19 are formed when the tungsten is deposited as a conductive film for the gate electrode on the barrier metal 18 and then recessed.

이 때 셀중심부 지역의 게이트전극(19)의 두께는 셀모서리 지역의 게이트전극(19)에 비해 크게 낮아진다.At this time, the thickness of the gate electrode 19 in the cell center region is significantly lower than that of the gate electrode 19 in the cell edge region.

이어 상기 게이트전극(19) 상부에 마스크질화막(20)을 형성한다.Subsequently, a mask nitride film 20 is formed on the gate electrode 19.

이와 같이 종래기술에 따른 반도체 소자의 제조 방법은 게이트전극의 전기적 특성이 불균일하게 되어 소자의 효율을 저하시킨다.As described above, in the method of manufacturing a semiconductor device according to the related art, the electrical characteristics of the gate electrode become nonuniform, thereby reducing the efficiency of the device.

본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로서, 평탄화용 절연막으로서 산화막에 비해 연마속도가 6 배 이상 느린 질화막을 이용하므로써 워드라인의 패터닝특성을 향상시키는데 적합한 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.
The present invention has been made to solve the above problems, and provides a method of manufacturing a semiconductor device suitable for improving the patterning characteristics of the word line by using a nitride film having a polishing rate 6 times slower than that of an oxide film as a planarization insulating film. There is a purpose.

상기의 목적을 달성하기 위한 본 발명의 반도체 소자의 제조 방법은 반도체 기판 상부에 연마방지막을 포함하는 제1워드라인을 형성하는 제1 단계, 상기 연마방지막 및 제1워드라인의 양측면에 접하는 측벽을 형성하는 제 2 단계, 상기 측벽 및 제1워드라인을 포함한 전면에 평탄화 대상 절연막을 형성하고 열처리하는 제 3 단계, 상기 연마방지막이 드러나도록 산화막용 슬러리를 이용한 연마공정으로 상기 절연막을 연마하는 제 4 단계, 상기 연마방지막과 제1워드라인을 제거하여 상기 측벽내부를 노출시키는 제 5 단계, 상기 노출된 측벽내부에 게이트절연막, 배리어메탈, 전도막을 형성하고 패터닝하여 제2워드라인을 형성하는 제 6 단계를 포함하여 이루어짐을 특징으로 한다.The semiconductor device manufacturing method of the present invention for achieving the above object is a first step of forming a first word line including an anti-polishing film on the semiconductor substrate, sidewalls in contact with both sides of the anti-polishing film and the first word line A second step of forming, a third step of forming a planarization insulating film on the entire surface including the sidewalls and the first word line, and a heat treatment; and a fourth step of polishing the insulating film by a polishing process using an oxide film slurry to expose the anti-polishing film. A fifth step of removing the polishing layer and the first word line to expose the inside of the sidewall; and a sixth step of forming and patterning a gate insulating film, a barrier metal, and a conductive film inside the exposed sidewall. Characterized by comprising a step.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 2a 내지 도 2d 는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 나타낸 도면으로서, 다마신공정(Damascene Process)을 이용하여 게이트전극을 형성하는 방법을 나타낸다.2A to 2D illustrate a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, which illustrates a method of forming a gate electrode using a damascene process.

도 2a 에 도시된 바와 같이, 반도체 기판(21) 상부에 저압(Low Pressure; LP) 또는 플라즈마인핸스드(Plasma Enhanced; PE) 방법을 이용하여 400∼1300℃에서 40∼100Å 두께의 패드산화막(22)을 증착한다. 이어 상기 패드산화막(22) 상에 도핑실리콘, 비정질실리콘 또는 폴리실리콘(23)을 400∼1200℃ 온도에서 500∼3000Å 두께로 증착한다.As shown in FIG. 2A, a pad oxide film 22 having a thickness of 40 to 100 占 에서 at 400 to 1300 ° C. using a low pressure (LP) or plasma enhanced (PE) method is formed on the semiconductor substrate 21. E). Subsequently, doped silicon, amorphous silicon, or polysilicon 23 is deposited on the pad oxide layer 22 to a thickness of 500 to 3000 kPa at a temperature of 400 to 1200 ° C.

이어 난반사(anti-reflective) 방지 및 연마정지막(Polishing stop layer)으 로서 제1질화막(24)을 저압 또는 플라즈마인핸스드 방법을 이용하여 400∼1300℃에서 200∼800Å 두께로 증착한다.Subsequently, as an anti-reflective prevention and polishing stop layer, the first nitride film 24 is deposited to a thickness of 200 to 800 占 에서 at 400 to 1300 ° C. using a low pressure or plasma enhanced method.

이어 상기 제1질화막(24) 상부에 감광막을 도포하고 노광 및 현상 공정으로 패터닝한 후, 상기 패터닝된 감광막을 마스크로 이용하여 상기 제1질화막(24), 폴리실리콘(23) 그리고 패드산화막(22)을 식각하므로써 워드라인영역을 형성한다.Subsequently, after the photoresist is coated on the first nitride film 24 and patterned by an exposure and development process, the first nitride film 24, the polysilicon 23, and the pad oxide film 22 are formed using the patterned photoresist as a mask. ) Is formed to form a word line region.

이어 상기 제1질화막(24) 및 폴리실리콘(23)을 포함한 전면에 측벽형성용 절연막으로서 제2질화막을 증착한다. 이어 상기 제2질화막을 전면식각하여 상기 제1질화막(24)을 포함한 폴리실리콘(23) 및 패드산화막(22)의 양측면에 접하는 측벽(25)을 형성한다.Subsequently, a second nitride film is deposited on the entire surface including the first nitride film 24 and the polysilicon 23 as an insulating film for forming sidewalls. Subsequently, the second nitride layer is etched entirely to form sidewalls 25 contacting both sides of the polysilicon 23 including the first nitride layer 24 and the pad oxide layer 22.

이어 상기 측벽(25)을 포함한 전면에 워드라인 평탄화용절연막(26)으로서 BPSG(Boro Phospho Silicate Glass), PSG(Phospho Silicate Glass), FSG(Fluoro Silicate Glass), PETEOS(Plasma Enhanced Tetra ethyl Ortho Silicate), PESiH4(Plasma Enhanced SiH4), HDP USG(High Density Plasma Undoped Silicate Glass), HDP PSG 또는 APL(Advanced Planarization Layer) 산화막을 3000∼10000Å 께로 증착하고 선택적으로 300∼ 1000℃ 로 열처리한다.Subsequently, the word line planarization insulating layer 26 is formed on the entire surface including the sidewalls 25. , PESiH 4 (Plasma Enhanced SiH 4 ), HDP USG (High Density Plasma Undoped Silicate Glass), HDP PSG or APL (Advanced Planarization Layer) oxide film is deposited at 3000-10000 Å and optionally heat-treated at 300 ~ 1000 ℃

도 2b에 도시된 바와 같이, 50∼500㎚ 크기의 실리카(Silica)계 산화막슬러리(Oxide Slurry)를 수소이온지수(pH) 8∼11 로 유지하면서 상기 제1질화막(24) 상부까지 화학적기계적연마(Chemical Mechanical Polishing;CMP) 공정을 진행한다.As shown in FIG. 2B, chemical mechanical polishing of silica-based oxide slurry of 50-500 nm size to the upper portion of the first nitride layer 24 while maintaining a hydrogen ion index (pH) of 8-11. Chemical Mechanical Polishing (CMP) process.

이 때 상기 제1질화막(24)의 표면이 드러나게 되고, 상기 제1질화막(24)이 연마정지막으로 이용되기 때문에 제1질화막(24) 하부의 폴리실리콘(23)의 손실이 발생되지 않는다. 이를 이용하면 웨이퍼의 중심부와 모서리부분에서 균일한 두께의 워드라인을 형성할 수 있고, 워드라인물질의 부식 또는 침식을 방지하는 효과가 크다.At this time, the surface of the first nitride film 24 is exposed, and since the first nitride film 24 is used as the polishing stop film, the loss of the polysilicon 23 under the first nitride film 24 does not occur. By using this, a word line having a uniform thickness can be formed at the center and corners of the wafer, and the effect of preventing corrosion or erosion of the word line material is large.

도 2c에 도시된 바와 같이, 인산을 이용하여 상기 제1질화막(24)을 제거하고 상기 폴리실리콘(23)및 패드산화막(22)을 습식식각하여 완전히 제거하므로써, 상기 측벽(25) 내부에 공간이 형성되고 반도체 기판(21)의 표면이 노출된다.As shown in FIG. 2C, the first nitride film 24 is removed using phosphoric acid, and the polysilicon 23 and the pad oxide film 22 are wet-etched to completely remove the space. Is formed and the surface of the semiconductor substrate 21 is exposed.

도 2d에 도시된 바와 같이, 상기 노출된 반도체기판(21) 상부를 포함한 전면에 게이트산화막(Gate Oxide)(27)으로서 열산화막(Thermal Oxide), 고온산화막 (High Temperature Oxide ;HTO) 또는 금속산화막인 Al2O3, Ta2O5 를 40∼100Å 두께로 형성한다.As shown in FIG. 2D, a thermal oxide film, a high temperature oxide film (HTO), or a metal oxide film is formed as a gate oxide film 27 on the entire surface including the exposed semiconductor substrate 21. Phosphorus Al 2 O 3 and Ta 2 O 5 are formed to a thickness of 40 to 100 GPa.

그리고 상기 게이트산화막(27) 상부에 배리어메탈(Barrier Metal)(28)로서 Ti, TiN, TiAlN, TaN, TiSiN, WN 또는 TiSi2 를 스퍼터링(Sputtering) 또는 화학적기상증착(Chemical Vapor Deposition;CVD) 방법으로 50∼800Å 두께로 증착한다. 이어 상기 배리어메탈(28)을 질소가스(N2) 분위기에서 400∼800℃ 온도로 열처리한다.And sputtering or chemical vapor deposition (CVD) of Ti, TiN, TiAlN, TaN, TiSiN, WN, or TiSi 2 as a barrier metal 28 on the gate oxide layer 27. To a thickness of 50 to 800 mm3. Subsequently, the barrier metal 28 is heat-treated at a temperature of 400 to 800 ° C. in a nitrogen gas (N 2 ) atmosphere.

이어 게이트전극용 전도막(29)으로서 텅스텐(W), 구리(Cu)등을 스퍼터링 또는 CVD 방법을 이용하여 300∼1000℃ 에서 2000∼5000Å 두께로 증착한 다음, 상기 게이트전극용 전도막(29)을 1500∼2000Å 타겟으로 리세스에치백(Recess Etchback)한다.Subsequently, tungsten (W), copper (Cu), or the like is deposited as a gate electrode conductive film 29 at a thickness of 2000 to 5000 kPa at 300 to 1000 ° C. by sputtering or a CVD method, and then the conductive film for the gate electrode 29 Recess etch back to 1500 ~ 2000 1500 target.

이어 상기 전도막(29)을 포함한 전면에 저압 또는 플라즈마인핸스드 방법으로 400∼1300℃ 온도에서 200∼800Å 두께의 제3질화막(30)을 증착한다.Subsequently, a third nitride film 30 having a thickness of 200 to 800 kPa is deposited on the entire surface including the conductive film 29 at a temperature of 400 to 1300 ° C. by a low pressure or plasma enhanced method.

이어 50∼500㎚ 크기의 실리카계 산화막슬러리를 수소이온지수(pH) 8∼11로 유지하면서 워드라인영역들 사이에 매립되었던 워드라인 평탄화용 절연막(26)이 드러날때까지 화학적기계적연마 공정을 진행하여 제3질화막(30)을 연마하므로써 상기 전도막(29) 상에 마스크질화막(31)을 포함하는 다마신 게이트전극을 형성한다.Subsequently, a chemical mechanical polishing process is performed while maintaining a 50-500 nm silica oxide slurry at a hydrogen ion index (pH) of 8 to 11 until the insulating film 26 for word line planarization, which was buried between the word line regions, is exposed. The third nitride film 30 is polished to form a damascene gate electrode including the mask nitride film 31 on the conductive film 29.

도면에 도시되지 않았지만, 본 발명은 다마신 또는 듀얼다마신공정을 이용하여 비트라인 형성시에도 동일하게 적용가능하다.Although not shown in the drawings, the present invention is equally applicable to bit line formation using a damascene or dual damascene process.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명의 반도체 소자의 제조 방법은 산화막에 비해 연마속도가 6배 이상 느린 질화막을 연마정지막으로 이용하므로써 게이트전극의 부식현상을 90%이상 향상시킬 수 있으며, 또한 웨이퍼내 연마균일도를 향상시킬 수 있고 게이트전극물질의 손실이 발생하지 않으므로 게이트전극 형성후 안정되고 균일한 소자 특성을 얻을 수 있다.In the method of manufacturing a semiconductor device of the present invention described above, by using a nitride film having a polishing rate that is six times or more slower than an oxide film as the polishing stop film, corrosion of the gate electrode can be improved by 90% or more, and the polishing uniformity in the wafer can be improved. Since no loss of gate electrode material occurs, stable and uniform device characteristics can be obtained after the formation of the gate electrode.

Claims (14)

반도체소자의 제조 방법에 있어서,In the manufacturing method of a semiconductor device, 반도체기판 상부에 연마방지막을 포함하는 제1워드라인을 형성하는 제1 단계;A first step of forming a first word line including an anti-polishing film on the semiconductor substrate; 상기 연마방지막 및 제1워드라인의 양측면에 접하는 측벽을 형성하는 제 2 단계;Forming a sidewall contacting both sides of the anti-polishing film and the first word line; 상기 측벽 및 제1워드라인을 포함한 전면에 평탄화 대상 절연막을 형성하고 열처리하는 제 3 단계;Forming a planarization insulating film on an entire surface including the sidewalls and the first word line and performing heat treatment; 상기 연마방지막이 드러나도록 산화막용 슬러리를 이용한 연마공정으로 상기 절연막을 연마하는 제 4 단계;A fourth step of polishing the insulating film by a polishing process using an oxide film slurry so that the anti-polishing film is exposed; 상기 연마방지막과 제1워드라인을 제거하여 상기 측벽내부를 노출시키는 제 5 단계; 및A fifth step of removing the polishing layer and the first word line to expose the inside of the sidewall; And 상기 노출된 측벽내부에 게이트절연막, 배리어메탈, 전도막을 형성하고 패터닝하여 제2워드라인을 형성하는 제 6 단계A sixth step of forming a second word line by forming and patterning a gate insulating film, a barrier metal, and a conductive film in the exposed sidewalls 를 포함하여 이루어짐을 특징으로 하는 반도체 소자의 제조 방법.Method of manufacturing a semiconductor device comprising the. 제 1 항에 있어서,The method of claim 1, 상기 제1 단계는,The first step, 상기 반도체기판 상에 패드산화막, 폴리실리콘, 질화막을 차례로 형성하는 단계; 및Sequentially forming a pad oxide film, a polysilicon, and a nitride film on the semiconductor substrate; And 워드라인마스크를 이용하여 상기 질화막, 폴리실리콘, 패드산화막을 패터닝하여 상기 연마방지막을 포함하는 제1워드라인을 형성하는 단계Patterning the nitride layer, the polysilicon layer, and the pad oxide layer using a word line mask to form a first word line including the anti-polishing layer 를 포함하여 이루어짐을 특징으로 하는 반도체 소자의 제조 방법.Method of manufacturing a semiconductor device comprising the. 제 2 항에 있어서,The method of claim 2, 상기 패드산화막은 저압 또는 플라즈마인핸스드 방법을 이용하여 400∼1300℃에서 40∼100Å 두께로 형성되는 것을 특징으로 반도체 소자의 제조 방법.The pad oxide film is a method of manufacturing a semiconductor device, characterized in that formed using a low pressure or plasma enhanced method at a thickness of 40 ~ 100Å at 400 ~ 1300 ℃. 제 1 항에 있어서,The method of claim 1, 상기 제 1 단계에서,In the first step, 상기 연마방지막은 저압 또는 플라즈마인핸스드 방법으로 400∼1300℃에서 200∼800Å 두께로 형성되는 것을 특징으로 반도체 소자의 제조 방법.The anti-polishing film is a method of manufacturing a semiconductor device, characterized in that formed in a low pressure or plasma enhanced method at a thickness of 200 ~ 800 Å at 400 ~ 1300 ℃. 제 1 항에 있어서,The method of claim 1, 상기 제 1 단계에서,In the first step, 상기 제1워드라인은 도핑실리콘, 비정질실리콘 또는 폴리실리콘을 이용하고 400∼1200℃에서 500∼3000Å 두께로 형성되는 것을 특징으로 반도체 소자의 제조 방법.The first word line is formed using a doped silicon, amorphous silicon or polysilicon and is formed to a thickness of 500 ~ 3000Å at 400 ~ 1200 ℃. 제 1 항에 있어서,The method of claim 1, 상기 제 3 단계에서,In the third step, 상기 평탄화대상절연막은 BPSG,PSG,FSG,PETEOS,PESiH4,HDP USG,HDP PSG, 또는 APL산화막 중 어느 하나를 이용하고 3000∼10000Å 두께로 형성되는 것을 특징으로 하는 반도체 소자의 제조 방법.The planarization insulating film is a semiconductor device manufacturing method characterized in that formed using any one of BPSG, PSG, FSG, PETEOS, PESiH 4 , HDP USG, HDP PSG, or APL oxide film to a thickness of 3000 ~ 10000Å. 제 1 항에 있어서,The method of claim 1, 상기 제 3 단계에서,In the third step, 상기 열처리는 300∼1000℃범위에서 이루어지는 것을 특징으로 하는 반도체 소자의 제조 방법.The heat treatment is a method of manufacturing a semiconductor device, characterized in that made in the range 300 to 1000 ℃. 제 1 항에 있어서,The method of claim 1, 상기 제 4 단계는,The fourth step, 50∼500㎚ 크기의 실리카계 슬러리를 pH 8∼11 로 유지하면서 상기 평탄화대상절연막을 연마하는 것을 특징으로 하는 반도체 소자의 제조 방법.A method of manufacturing a semiconductor device, wherein the planarization insulating film is polished while maintaining a silica-based slurry having a size of 50 to 500 nm at a pH of 8 to 11. 제 1 항에 있어서,The method of claim 1, 상기 제 5 단계에서,In the fifth step, 상기 연마방지막은 인산으로 제거되는 것을 특징으로 하는 반도체 소자의 제조 방법.The anti-polishing film is a manufacturing method of a semiconductor device, characterized in that removed with phosphoric acid. 제 1 항에 있어서,The method of claim 1, 상기 제 5 단계에서,In the fifth step, 상기 제1워드라인은 습식식각으로 제거되는 것을 특징으로 하는 반도체 소자의 제조 방법.The first word line is removed by wet etching. 제 1 항에 있어서,The method of claim 1, 상기 제 6 단계에서,In the sixth step, 상기 게이트산화막으로 열산화막, 고온산화막 또는 금속산화막을 40∼100Å 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.A thermal oxide film, a high temperature oxide film, or a metal oxide film is formed with the gate oxide film to a thickness of 40 to 100 kHz. 제 1 항에 있어서,The method of claim 1, 상기 제 6 단계에서,In the sixth step, 상기 전도막은 텅스텐, 구리를 포함한 금속을 이용하고 스퍼터링 또는 화학적기상증착법으로 300∼1000℃에서 2000∼5000Å 두께로 증착되는 것을 특징으로 하는 반도체 소자의 제조 방법.The conductive film is a semiconductor device manufacturing method using a metal containing tungsten, copper, and is deposited to a thickness of 2000 ~ 5000Å at 300 ~ 1000 ℃ by sputtering or chemical vapor deposition. 제 1 항에 있어서,The method of claim 1, 상기 제 6 단계에서,In the sixth step, 상기 배리어메탈은 Ti, TiN, TiAlN, TaN, TiSiN, WN 또는 TiSi2 중 어느 하나를 이용하고 스퍼터링 또는 화학적기상증착법으로 50∼800Å 두께로 증착되는 것을 특징으로 하는 반도체 소자의 제조 방법.The barrier metal is any one of Ti, TiN, TiAlN, TaN, TiSiN, WN or TiSi 2 using a sputtering or chemical vapor deposition method is a semiconductor device manufacturing method characterized in that the deposition to a thickness of 50 ~ 800Å. 제 1 항에 있어서,The method of claim 1, 상기 배리어메탈은 질소분위기에서 400∼800℃ 온도로 열처리되는 것을 특징으로 하는 반도체 소자의 제조 방법.The barrier metal is a method of manufacturing a semiconductor device, characterized in that the heat treatment at 400 ~ 800 ℃ temperature in a nitrogen atmosphere.
KR1019990058739A 1999-12-17 1999-12-17 Method for manufacturing gate electrode using damascene process Expired - Fee Related KR100582370B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019990058739A KR100582370B1 (en) 1999-12-17 1999-12-17 Method for manufacturing gate electrode using damascene process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019990058739A KR100582370B1 (en) 1999-12-17 1999-12-17 Method for manufacturing gate electrode using damascene process

Publications (2)

Publication Number Publication Date
KR20010057016A KR20010057016A (en) 2001-07-04
KR100582370B1 true KR100582370B1 (en) 2006-05-23

Family

ID=19626717

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019990058739A Expired - Fee Related KR100582370B1 (en) 1999-12-17 1999-12-17 Method for manufacturing gate electrode using damascene process

Country Status (1)

Country Link
KR (1) KR100582370B1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100350056B1 (en) * 2000-03-09 2002-08-24 삼성전자 주식회사 Method of forming a self-aligned contact pad in a damascene gate process
KR100456319B1 (en) * 2000-05-19 2004-11-10 주식회사 하이닉스반도체 Method for forming gate of semiconductor device by using polishing selectivity difference between polymer and oxide layer
KR100807521B1 (en) * 2006-08-23 2008-02-26 동부일렉트로닉스 주식회사 Semiconductor device manufacturing method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5856225A (en) * 1997-11-24 1999-01-05 Chartered Semiconductor Manufacturing Ltd Creation of a self-aligned, ion implanted channel region, after source and drain formation
JPH11121745A (en) * 1997-10-20 1999-04-30 Nec Corp Method for manufacturing semiconductor device
US5960270A (en) * 1997-08-11 1999-09-28 Motorola, Inc. Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions
KR20010032448A (en) * 1998-09-28 2001-04-25 롤페스 요하네스 게라투스 알베르투스 Method of manufacturing a semiconductor device with a field effect transistor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5960270A (en) * 1997-08-11 1999-09-28 Motorola, Inc. Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions
JPH11121745A (en) * 1997-10-20 1999-04-30 Nec Corp Method for manufacturing semiconductor device
US5856225A (en) * 1997-11-24 1999-01-05 Chartered Semiconductor Manufacturing Ltd Creation of a self-aligned, ion implanted channel region, after source and drain formation
KR20010032448A (en) * 1998-09-28 2001-04-25 롤페스 요하네스 게라투스 알베르투스 Method of manufacturing a semiconductor device with a field effect transistor

Also Published As

Publication number Publication date
KR20010057016A (en) 2001-07-04

Similar Documents

Publication Publication Date Title
KR100587635B1 (en) Manufacturing Method of Semiconductor Device
TW200535990A (en) Forming method of self-aligned contact for semiconductor device
US7875547B2 (en) Contact hole structures and contact structures and fabrication methods thereof
KR100670662B1 (en) Semiconductor device manufacturing method
KR100492898B1 (en) Method for fabricating semiconductor device
KR100252039B1 (en) Method for forming a self-aligned contact hole
KR100505450B1 (en) Method for fabricating semiconductor device using damascene process
KR100582370B1 (en) Method for manufacturing gate electrode using damascene process
KR100553517B1 (en) Method of forming contact plug of semiconductor memory device
KR100643568B1 (en) Deep contact hole formation method of semiconductor device
KR100456318B1 (en) Method for forming plug of semiconductor device
KR100307968B1 (en) Method of forming interlevel dielectric layers of semiconductor device provided with plug-poly
KR101073123B1 (en) Method for fabrication of semiconductor device
KR100529381B1 (en) Method for forming capacitor bottom electrode of semiconductor device by using blanket etch and polishing
KR100578230B1 (en) Bit line formation method using dual damascene process
KR100546111B1 (en) Manufacturing Method of Semiconductor Device
KR100589498B1 (en) Semiconductor device and manufacturing method thereof
KR100681209B1 (en) Deep contact hole formation method of semiconductor device
KR20010005107A (en) Method for forming plug of semiconductor device
KR100338827B1 (en) Method for forming a storage node electrode of memory device
KR20020002538A (en) Method for forming contact plug in semiconductor device
KR20020002569A (en) Method for forming contact plug in semiconductor device
KR20020002524A (en) Method for forming contact plug in semiconductor device
KR20010045426A (en) Method for forming capacitor bottom electrode of semiconductor device by using siliconoxynitride hard mask
KR20020072370A (en) Method of forming gate electrode using damascene process and gate electrode using the same

Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19991217

PG1501 Laying open of application
A201 Request for examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20040504

Comment text: Request for Examination of Application

Patent event code: PA02011R01I

Patent event date: 19991217

Comment text: Patent Application

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20051031

Patent event code: PE09021S01D

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 20060427

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 20060515

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 20060511

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20090427

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 20100423

Start annual number: 5

End annual number: 5

FPAY Annual fee payment

Payment date: 20110429

Year of fee payment: 6

PR1001 Payment of annual fee

Payment date: 20110429

Start annual number: 6

End annual number: 6

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee