KR100581213B1 - Shift register of liquid crystal display device - Google Patents

Abstract

The present invention relates to a stage of a redundant shift register cascaded with a plurality of substantially identical stages, comprising: a first delay circuit for receiving an input signal and delaying the output signal for a predetermined time; and the same configuration and function as the first delay circuit. A shift register of a liquid crystal display device comprising: a second delay circuit having a voltage; and an output controller configured to generate an output by detecting voltage levels of specific nodes of the first and second delay circuits. Even if it occurs, there is an advantage that can be economically and time-saving in the process because the operator does not need to cut the laser on purpose. In addition, there is an advantage in simplifying the process because the shift register does not need to separately check for line defects.

Shift register

Description

SHIFT REGISTER FOR LIQUID CRYSTAL DISPLAY}             

1 is a circuit diagram schematically showing a conventional redundant shift register in a liquid crystal display device.

2 is a graph for explaining the three-phase clock signal shown in FIG.

FIG. 3 is a graph showing a signal input to the shift register shown in FIG. 1 and an output signal according to time; FIG.

4 is a circuit diagram schematically illustrating a shift register of a liquid crystal display device according to a first embodiment of the present invention.

5 is a graph showing waveforms of various signals input and output to a redundant shift register of a liquid crystal display according to a first embodiment of the present invention.

6 is a circuit diagram schematically illustrating a redundant shift register of a liquid crystal display according to a second exemplary embodiment of the present invention.

7 is a graph illustrating waveforms of various signals input and output to a shift register of a liquid crystal display according to a second exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

INPUT; Input signal C1; First clock

C2; Second clock C3; Third clock

VDD; Drain voltage 20a; A part of the stage

20b; Part B of the stage 20c; Output control part

The present invention relates to a shift register, and more particularly, to a shift register of a liquid crystal display device in which a separate repair operation is not required even if a line break occurs.

In general, a large number of thin film transistors (hereinafter referred to as TFTs) for controlling and transmitting image signals are formed in liquid crystal display devices. The TFT consists of a gate electrode, a source electrode, and a drain electrode. Each gate electrode is connected to each other in the horizontal axis direction to form a gate line, and each source electrode is connected to each other in the vertical axis direction to form a data line. That is, the gate line and the data line are arranged to cross each other.

When a specific gate line is selected by an external control circuit, image information corresponding to the line is supplied through the data line.

The liquid crystal display device does not display a single image at the same time because of the image display system described above, and uses a method of displaying one line at a time. That is, in the liquid crystal display device, a circuit used for time-division displaying one image data and time-dividing the image data is a shift register. The shift register is generally used for storing or moving externally input data (0 or 1) and performs an operation of moving data from one stage in another register to another stage or outside of the register.

Such a shift register is composed of a plurality of stages, and moves predetermined data according to a clock signal and a reset signal input from the outside, and as a result, it appears that the input data signal is delayed and outputted for a predetermined time. At this time, each stage has an input and an output connected in series.

On the other hand, the image data has a large capacity, and the space of the circuit area is further reduced due to the recent tendency toward light and small size. Since the phenomenon in which the inter-device space is miniaturized is applied to all semiconductor devices, the shift register can not avoid a decrease in process yield unless such problems are solved.

Therefore, there is an urgent need to study a circuit configuration that can structurally prevent disconnection or short circuit.

Hereinafter, a shift register of a general liquid crystal display device will be described with reference to the accompanying drawings. In practice, the shift register is composed of a plurality of stages, but since the configuration and function are the same, only the unit stage will be described.

FIG. 1 is a circuit diagram showing a conventional redundant shift register of a liquid crystal display device, in which two portions 10a and 10b having the same configuration are formed in one stage. Each part includes an input part, an intermediate part, and an output part, wherein the first input part includes first and second transistors, the first intermediate part includes third and fourth transistors, and the first output part includes fifth and sixth transistors. It consists of each.

The shift register receives an input signal, a clock signal, and a drain voltage, respectively, and outputs a signal delayed by one period from the input signal. At this time, two different clock signals are input to the shift register from among the three-phase clock signals as shown in FIG. 2, wherein the first three-phase clock, the third three-phase clock, the first three-phase clock and the second three-phase clock, Combination of three three-phase clocks followed by two three-phase clocks and a third three-phase clock.

The function and operation of the shift register having such a configuration will be described with reference to the accompanying drawings.

FIG. 3 is a graph showing input and output signal waveforms of a conventional shift register for each time interval in a general liquid crystal display device, in which the horizontal axis represents time and the vertical axis represents voltage level. The parts A and B of the stage have the same configuration and function, so the description will focus on the part A.

는 로우상태가 된다.In the first time period T0 to T1, the first transistor and the fourth transistor U1 and U4 are turned on by the input signal INPUT, and the third transistor U3 is turned on by the first clock signal C1. Is turned on. In addition, the input signal precharges the gate electrode of the fifth transistor U5 while passing through the first transistor U1. At this time, the third and fourth transistors U3 and U4 are simultaneously turned on, but the fourth signal is turned on. The ratio of length VS width (hereinafter, referred to as W / L ratio) of the transistor U4 is set to be sufficiently larger than the ratio of W / L of the third transistor,

Goes low.

는 로우상태가 된다. 그리고, 출력단(OUT)은 제2 클럭신호(C2)가 로우상태이기 때문에 로우상태가 된다.Thus, node Q1 goes high and node

Goes low. The output terminal OUT is in a low state because the second clock signal C2 is in a low state.

In the second time period T1 to T2, since the second clock signal C2 is supplied, the second clock signal C2 is output through the fifth transistor U5, and the output terminal OUT becomes high. At this time, the node Q1 is maintained at a voltage level much higher than the high level of the clock signal due to the bootstrap phenomenon.

은 제3 트랜지스터(U3) 및 제4 트랜지스터(U4)가 턴오프되어 있기 때문에 로우상태가 유지된다.On the other hand, the node

The low state is maintained because the third transistor U3 and the fourth transistor U4 are turned off.

The A and B portions of the stage not only have the same configuration, but also generate the same output OUT. Therefore, there is no problem when two parts are operating at the same time, but in order to perform a normal function even when only one of them is operated, the output terminal of the defective part must be cut by laser cutting method.

As a result, one stage receives the data signal and generates a delayed output signal.

The plurality of waveforms output from the shift register are used to display image information of the liquid crystal display device line by line.

As described above, although the shift register is manufactured to have the stages of the same structure, some achievements have been made in improving the yield, but there is a hassle for the operator to detect defects one by one.

In addition, the time and economic loss that the operator takes to detect each one has a problem that the rise in manufacturing costs.

Therefore, there is a need for a shift register having a structure that can continue to perform its function when the output of the remaining part is normal even if there is a part in which a defect occurs even if the operator does not inspect it individually.

In order to solve the above-mentioned problems and to satisfy the above-mentioned problem, the present invention provides a shift of a liquid crystal display device in which a defect occurs in one of two parts of a redundant stage so that only the remaining part of the redundant stage continues operation. The purpose is to provide a register.

According to an aspect of the present invention, there is provided a stage of a redundant shift register cascaded with a plurality of substantially identical stages, comprising: a first delay circuit for receiving an input signal and delaying the output signal for a predetermined time; The second delay circuit having the same configuration and function as the first delay circuit and the voltage level of the specific node corresponding to each other of the first and second delay circuits are detected, and at least one voltage of the specific node corresponding to each other is predetermined. It is a feature of the present invention to provide a shift register of a liquid crystal display device including an output control unit for generating an output signal when the level or more.

Another feature of the present invention is a stage of a redundant shift register cascaded with a plurality of substantially identical stages, the first input unit receiving an input signal and precharging the voltage to a predetermined level, and receiving a three-phase clock signal. The first output unit outputs a signal delayed by the predetermined time by the precharged voltage by a predetermined time, and the output of the first output unit is not generated while the input signal is supplied by receiving a three-phase clock signal and a drain voltage. A first delay circuit including a first intermediate portion to prevent the first delay circuit; A second delay circuit having the same configuration as the first delay circuit and having the same input / output, a second delay circuit, a second intermediate section, and a second output section; The present invention provides a shift register of a liquid crystal display device including an output control unit for generating an output signal when at least one voltage of an output node of the first input unit and the second input unit is greater than or equal to a predetermined level.

Another feature of the present invention is a stage of a redundant shift register cascaded with a plurality of substantially identical stages, the first input unit receiving an input signal and precharging the voltage to a predetermined level, and a three-phase clock signal. A first output unit outputting a signal delayed by the pre-charged voltage by a predetermined time and a three-phase clock signal and a drain voltage to generate an output of the first output unit while the input signal is supplied. A first branch banquet comprising a first intermediate portion to prevent the first branch from being banned; A second delay circuit having the same configuration as the first delay circuit and having the same input / output, a second delay circuit, a second intermediate section, and a second output section; A shift register of a liquid crystal display device including an output control unit for generating an output signal when at least one voltage of an output node of the first intermediate part and the second intermediate part is less than or equal to a predetermined level.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. And, the description of the same parts as described above will be described schematically.

First embodiment

The first embodiment is configured to generate an output of the shift register when at least one of the voltage levels of the specific nodes of the A and B portions of the stage is normal.

FIG. 4 is a circuit diagram illustrating a shift register of a liquid crystal display device according to a first embodiment of the present invention. In the first transistor U1, an input signal is simultaneously supplied to a gate and a drain, and a second transistor U2 is provided. The drain is connected to the source of the first transistor and the source is grounded. The third transistor U3 is supplied with a first three-phase clock to a gate, a voltage of a predetermined level is supplied to a drain, the fourth transistor U4 is supplied with an input signal to a gate, and the drain is supplied to the third transistor ( Connected to the source of U3), and the source is grounded. In the fifth transistor U5, a gate is connected to the source of the first transistor U1, a second three-phase clock is supplied to a drain, and a capacitor is connected in parallel with the fourth transistor U4. A drain of the sixth transistor U6 is connected to the source of the fifth transistor U5, and the source is grounded. The first to sixth transistors U1 to U6 and the capacitor A form part 20a.

In addition, an input signal is simultaneously supplied to the gate and the drain of the seventh transistor U7, the drain of the eighth transistor U8 is connected to the source of the seventh transistor U7, and the source is grounded. A first three-phase clock is supplied to a gate of the ninth transistor U9, a voltage of a predetermined level is supplied to a drain thereof, an input signal is supplied to a gate of the tenth transistor U10, and a drain of the ninth transistor U9 of the ninth transistor ( Connected to the source of U9), and the source is grounded.

A gate of the eleventh transistor U11 is connected to a source of the seventh transistor U7, a second three-phase clock is supplied to a drain, and a drain of the twelfth transistor U12 has a drain of the eleventh transistor U11. The source is connected and the source is grounded. The capacitor is connected in parallel with the tenth transistor U10.

As such, the B portion 20b is formed of the seventh through twelfth transistors U7-U12 as a capacitor.

In addition, the thirteenth transistor U13 is supplied with a first three-phase clock C1 to a gate, a voltage of a predetermined level is supplied to a drain, and the gate of the fourteenth transistor U14 is connected to the gate of the first transistor U1. The source is connected to the source, the drain is connected to the source of the thirteenth transistor U13, and the source is grounded. The drain of the fifteenth transistor U15 is connected to the source of the thirteenth transistor U13, the gate is connected to the source of the seventh transistor U7, and the source is grounded. The capacitor is connected in parallel with the fifteenth transistor U15. The output control unit 20c is formed of the thirteenth to fifteenth transistors U13 to U15.

In this way, the stage is composed of the A portion and the B portion 20a and 20b and the output control portion 20c, and the plurality of stages are assembled to form a shift register. In addition, each stage is connected to the input and output terminals in series, the function and operation of the stage of the shift register will be described as follows.

One stage includes an A portion having a first input portion, a first output portion, a first intermediate portion, a B portion having a second input portion, a second output portion, a second intermediate portion, and an output for controlling the outputs of the A portion and the B portion. It consists of a controller.

The A part 20a receives an input signal INPUT, a first clock signal C1, a drain voltage VDD, and a second clock signal C2 and outputs an output signal OUT delayed by a predetermined time. The B part 20b also receives the same input signal and outputs the same output signal. That is, part A is part B, and part B is a defect compensation circuit in case a defect occurs.

The A portion 20a may include a first input part including the first transistor U1 and the second transistor U2, a first intermediate part including the third transistor U3 and the fourth transistor U4, and a fifth part. The first output unit includes a transistor U5 and a sixth transistor U6.

In addition, the B portion 20b includes a second input portion including a seventh transistor U7 and an eighth transistor U8, a second intermediate portion consisting of a ninth transistor U9 and a tenth transistor U10, and The second output unit includes an eleventh transistor U11 and a twelfth transistor U12.

The output controller 20c includes thirteenth to fifteenth transistors U13 to U15.

However, the output signal generated at the stage of the shift register is a signal output from the A portion 20a or the B portion 20b, and if either of the A portion and the B portion is normal, the shift register is configured to operate normally. have. For example, even if the output of the A part is abnormal and the output of the B part is normal, the shift register is not affected by the defect of the A part because the shift register outputs the normal B part.

And, even if the voltage level of the Q1 node of the A part and the Q2 node of the B part is more than a predetermined level, the output control unit 20c performs a function of outputting only the output of the corresponding part.

In other words, the condition in which the portion A or the portion B outputs the signal is when the fifth and eleventh transistors U5 and U11 are turned on and the sixth and twelfth transistors U6 and U12 are turned off. The shift register generates a normal output by turning the sixth or twelfth transistor to the turn-off state even when the voltage of Q1 or Q2 is higher than a predetermined level at the time when the shift register is generated.

Referring to the operation of the output control unit of the shift register having such a configuration as follows.

When the input signal INPUT and the first clock signal C1 are supplied, the first and fourth transistors U1 and U4 are turned on in the A portion, and the fifth and fourteenth transistors U5 are turned on through the node Q1. The gate electrode of (U14) is precharged.

At the same time, the seventh transistor U7 and the tenth transistor U10 are turned on in the portion B, and the gate electrodes of the eleventh transistor U11 and the fifteenth transistor U15 are precharged through the node Q2. Here, the capacitor connected in parallel with the fourteenth and fifteenth transistors U14 and U15 serves to preserve charge for a predetermined time.

Thus, the precharged fifth transistor and the eleventh transistors U5 and U11 output the second clock signal C2 through the output terminal OUT. That is, the shift register generates an output signal delayed by a predetermined time compared to the input signal INPUT.

If the node Q1 of the A portion is normal and a defect occurs in the B portion and the signal of the node Q2 is abnormal as shown in FIG. 5, the fifteenth transistor U15 is turned off, but the fourteenth transistor U14 is Because it is turned on, node R drops low, resulting in a normal output.

This is true even when a defect occurs in the A part, so that the shift register can generate the output normally unless the A and B parts have a defect. That is, since any one of the A and B portions can bring the node R low at the time of generating the output of the shift register, the shift register can generate the output normally.

및

의 전압레벨을 검출하여 쉬프트레지스터의 출력을 제어할 수도 있는데, 이것은 다른 실시예에서 설명하도록 한다.As described above, the node is not detected without detecting the voltage levels of the nodes Q1 and Q2.

And

It is also possible to control the output of the shift register by detecting the voltage level, which will be described in another embodiment.

Second embodiment

및 B부분의

가 소정레벨 이하인지를 검출해서 출력을 제어하도록 한 출력제어부를 구성한 쉬프트레지스터에 관한 것이고, 제1 실시예와 유사한 부분의 설명은 개략적으로 설명하도록 한다.The second embodiment of the stage A

And part B

Is related to a shift register configured by an output control unit which detects whether or not is equal to or less than a predetermined level, and controls the output. A description of a portion similar to the first embodiment will be described schematically.

FIG. 6 is a circuit diagram schematically showing a shift register according to a second embodiment of the present invention, in which part A and part B of the stage are the same as the first embodiment described above, and only the output control unit is configured differently.

As shown, the output control unit is comprised of sixteenth to eighteenth transistors.

A sixteenth transistor has a gate connected to the source of the third transistor, a drain supplied with a predetermined level of voltage, a seventeenth transistor has a gate connected to the source of the ninth transistor, and a drain connected to the source of the sixteenth transistor .

An eighteenth transistor has an input signal supplied to a gate, a drain thereof is connected to a source of the seventeenth transistor, a source is grounded, and a capacitor is connected in parallel with the eighteenth transistor.

및 B부분의

의 전압이 소정레벨 이하인지를 검출해서 출력신호를 발생시키는 출력제어부로 이루어져 있다.That is, part A, part B, and part A

And part B

And an output control section for detecting whether or not the voltage is below a predetermined level and generating an output signal.

및

의 전압을 검출해서 출력하기 때문이다.The circuit configurations of the A and B sections of the stage are the same as in the first embodiment, but the output control sections are different from each other, unlike the first embodiment, which does not detect the voltages of the nodes Q1 and Q2, but rather the nodes.

And

This is because the voltage is detected and output.

및

의 전압이 둘중 하나라도 소정레벨 이하일 경우에만 쉬프트레지스터의 출력이 발생되도록 구성되어 있다.The output control unit is connected to the input signal, the drain voltage, and ground, respectively, and the node

And

The output of the shift register is generated only when either of the voltages is less than or equal to the predetermined level.

및

와 노드 Q1 및 Q2는 서로 상반된 전압레벨을 가지기 때문에 제2 실시예의 출력제어부는 상기

및

중 하나가 소정레벨 이하일 경우에만 쉬프트레지스터의 출력을 발생시킨다.That is, the node as described above

And

Since the nodes Q1 and Q2 have voltage levels that are opposite to each other, the output control unit of the second embodiment is

And

The output of the shift register is generated only when either one is less than or equal to the predetermined level.

및

노드가 모두 소정레벨 이상의 전압을 유지하게 되고, 이때의 제16 트랜지스터 및 제17 트랜지스터는 동시에 턴온되므로 노드 R이 하이상태가 된다. 따라서, 제6 트랜지스터와 제12 트랜지스터가 턴온되어 로우출력을 발생시킨다.If the input signal does not come in (although most of the time)

And

All nodes maintain a voltage higher than or equal to a predetermined level. At this time, the sixteenth transistor and the seventeenth transistor are turned on at the same time, so that the node R becomes high. Thus, the sixth and twelfth transistors are turned on to generate a low output.

A waveform of the shift register configured as described above will be described with reference to FIG. 7.

When the input signal comes in, the eighteenth transistor U18 is turned on so that the R node becomes low level once.

와

가 모두 로우상태에 있으므로 제16 트랜지스터(U16), 제17 트랜지스터(U17)이 턴오프되어 R 노드 전압은 계속 로우레벨에 있다. 이때, 제2 3상클럭이 들어오면 출력단이 하이레벨로 된다.If both A and B parts of the stage are normal,

Wow

Are both in the low state, the sixteenth transistor U16 and the seventeenth transistor U17 are turned off, and the R node voltage remains at the low level. At this time, when the second three-phase clock enters, the output stage becomes a high level.

은 로우상태가 되고,

는 하이 상태가 된다. 즉, 제17 트랜지스터(U17)가 턴온되더라도 제16 트랜지스터(U16)가 턴오프되어 있기 때문에 R 노드 전압은 계속 로우레벨이 되는 것이다.If part B of the stage is abnormal,

Goes low,

Goes high. That is, even when the seventeenth transistor U17 is turned on, the R node voltage continues to be at a low level because the sixteenth transistor U16 is turned off.

와

가 모두 하이상태가 되기 때문에 R 노드 전압이 하이상태로 변하기 때문에 로우전압을 출력하게 되므로, 스테이지는 불량이 된다.Of course, if parts A and B are abnormal,

Wow

Since all of the high states cause the R node voltage to change to a high state and output a low voltage, the stage is defective.

와

가 모두 하이상태가 되기 때문에 R 노드 전압이 하이상태를 유지하는데, 이는 제6 트랜지스터 및 제12 트랜지스터가 턴온되기 때문이며, 출력단은 로우상태가 된다.However, when no input signal comes in

Wow

R node voltage remains high because both are high, since the sixth and twelfth transistors are turned on, and the output terminal is turned low.

및

중에서 하나는 정상적으로 출력을 발생시키고, 다른 하나는 비정상적인 출력을 내보낼 때에도 쉬프트레지스터의 출력은 정상적인 것을 볼 수 있다.As such, two-part nodes

And

The output of the shift register is normal even when one of them generates a normal output and the other outputs an abnormal output.

On the other hand, in the circuits of the first and second embodiments as described above, the shift register does not generate an output signal because the transistor which passes the second three-phase clock signal does not operate in most of the time intervals in which the input signal is not supplied. .

를 검출하는가 하는점이다.The commonality between the first and second embodiments described above is that the output of the shift register is easily brought to a low state during the time period when the shift register outputs a high voltage. Detect Q node

Is to be detected.

The central idea of the present invention as described above is not limited to the disclosed first and second embodiments because it detects the node state of two parts in the shift register and generates the output of the shift register, and can be inferred from the present invention. Modified embodiments should also be considered to be within the scope of the present invention.

According to the embodiment of the present invention as described above has the following advantages.

First, even if line defects occur in the stage of the shift register, the operator does not need to deliberately cut the laser, and thus, there is an advantage in that the process can reduce economic and time costs.

Second, there is an advantage in simplifying the process because the shift register does not need to separately check for line defects.

Claims (9)

A plurality of substantially identical stages are stages of a cascaded redundant shift register, A first delay circuit which receives an input signal and delays it for a predetermined time and outputs the delayed signal; A second delay circuit having the same configuration and function as the first delay circuit, And an output control unit for detecting a voltage level of a specific node corresponding to each other of the first and second delay circuits, and generating an output signal when at least one voltage of the specific node corresponding to each other is higher than a predetermined level. Shift register. A stage of a redundant shift register in which a plurality of identical stages are cascaded and use first and second three-phase clock signals, A first input unit configured to receive an input signal and precharge it to a voltage having a predetermined level, and a first output unit configured to receive the second three-phase clock signal and output a signal delayed by the precharged voltage by a predetermined time by the precharged voltage; A first delay circuit including a first intermediate portion to receive the first three-phase clock signal and a VDD voltage so that an output of the first output portion is not generated while an input signal is supplied; A second delay circuit having the same configuration as the first delay circuit and having the same input / output, a second delay circuit having a second input portion, a second intermediate portion, and a second output portion; An output control unit for generating an output signal when at least one voltage of the output node of the first input unit and the second input unit A shift register of a liquid crystal display device comprising. The method of claim 2, The first delay circuit includes a first transistor having an input signal simultaneously supplied to a gate and a drain, a second transistor having a drain connected to a source of the first transistor, and having a source grounded, and a gate having the first three-phase clock. A third transistor supplied with a predetermined voltage to a drain, an input signal supplied to a gate, a drain connected to a source of the third transistor and a gate of the second transistor, and having a source grounded; A transistor, a capacitor connected in parallel with the fourth transistor, a gate connected to a source of the first transistor, a drain connected to a source of the second three-phase clock signal, and a drain connected to a source of the fifth transistor; A shift of the liquid crystal display device including a sixth transistor connected to the source, a source connected to a ground, and a gate connected to the output controller; Requesters. The method of claim 2, The second delay circuit includes a seventh transistor in which an input signal is simultaneously supplied to a gate and a drain, a drain connected to a source of the seventh transistor, an eighth transistor having a source grounded, and a gate of the first three phase clock. A ninth transistor receiving a signal, a voltage of a predetermined level supplied to a drain, an input signal supplied to a gate, a drain connected to a source of the ninth transistor and a gate of the eighth transistor, and having a source grounded; A tenth transistor, a capacitor connected in parallel with the tenth transistor, an eleventh transistor having a gate connected to a source of the seventh transistor, a drain of which receives the second three-phase clock signal, and a drain of a source of the eleventh transistor And a source connected to the ground, and a gate connected to the output control unit. Prestige. The method of claim 2, The output controller includes a thirteenth transistor supplied with a first three-phase clock signal to a gate, a voltage of a predetermined level to a drain, a gate connected to a source of the first transistor, and a drain of the thirteenth transistor A fourteenth transistor connected to the source, the source of which is grounded, a drain connected to the source of the thirteenth transistor, a gate connected to a source of the seventh transistor, and a source of the fifteenth transistor; 15. A shift register of a liquid crystal display device comprising a capacitor connected in parallel with a transistor. A stage of a redundant shift register in which a plurality of identical stages are cascaded and use first and second three-phase clock signals, A first input unit configured to receive an input signal and precharge it to a voltage having a predetermined level, and a first output unit configured to receive the second three-phase clock signal and output a signal delayed by the precharged voltage by a predetermined time by the precharged voltage; A first delay circuit including a first intermediate portion to receive the first three-phase clock signal and a VDD voltage so that an output of the first output portion is not generated while an input signal is supplied; A second delay circuit having the same configuration as the first delay circuit and having the same input / output, a second delay circuit having a second input portion, a second intermediate portion, and a second output portion; An output control unit for generating an output signal when at least one voltage of the output node of the first intermediate part and the second intermediate part is equal to or less than a predetermined level; A shift register of a liquid crystal display device comprising. The method of claim 6, The first delay circuit includes a first transistor having an input signal supplied to a gate and a drain in one direction, a second transistor having a drain connected to a source of the first transistor, a source grounded, and a gate of the first three phase A third transistor receiving a clock signal, supplied with a predetermined voltage to a drain, an input signal supplied to a gate, a drain connected to a source of the third transistor and a gate of the second transistor, and having a source grounded A fourth transistor, a capacitor connected in parallel with the fourth transistor, a fifth transistor having a gate connected to a source of the first transistor, a drain of which receives the second three-phase clock signal, and a drain of the fifth transistor A liquid crystal display device comprising a sixth transistor connected to a source, a source of which is grounded, and a gate of which is connected to the output controller. Theft register. The method of claim 6, The second delay circuit includes a seventh transistor in which an input signal is supplied in one direction to a gate and a drain, a drain connected to a source of the seventh transistor, an eighth transistor having a source grounded, and a gate in the first three phase A ninth transistor receiving a clock signal, a voltage having a predetermined level supplied to a drain; an input signal supplied to a gate; a drain connected to a source of the ninth transistor and a gate of the eighth transistor; A tenth transistor, a capacitor connected in parallel with the tenth transistor, a gate connected to a source of the seventh transistor, a drain of which receives the second three-phase clock signal, and a drain of the eleventh transistor A liquid crystal display device comprising a twelfth transistor connected to a source, a source of which is grounded, and a gate of which is connected to the output controller; Shift register. The method of claim 6, The output controller includes a sixteenth transistor whose gate is connected to a source of a third transistor, a drain is supplied with a predetermined level of voltage, a gate thereof is connected to a source of a ninth transistor, and a drain thereof is connected to a source of the sixteenth transistor. A seventeenth transistor, an input signal supplied to a gate, a drain of which is connected to a source of the seventeenth transistor, a source of which is grounded, and a capacitor connected in parallel with the eighteenth transistor of the liquid crystal display device. Shift register.

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