KR100577144B1 - Frame synchronization detection method of binary code - Google Patents
Frame synchronization detection method of binary code Download PDFInfo
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- KR100577144B1 KR100577144B1 KR1019980033309A KR19980033309A KR100577144B1 KR 100577144 B1 KR100577144 B1 KR 100577144B1 KR 1019980033309 A KR1019980033309 A KR 1019980033309A KR 19980033309 A KR19980033309 A KR 19980033309A KR 100577144 B1 KR100577144 B1 KR 100577144B1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
- H04L7/042—Detectors therefor, e.g. correlators, state machines
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
- H04L27/2656—Frame synchronisation, e.g. packet synchronisation, time division duplex [TDD] switching point detection or subframe synchronisation
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Abstract
본 발명은 정확한 이원부호의 동기 검출 방법을 제공하기 위한 것으로, 수신되는 이원부호 a에 수신기에 내장된 상기 수신된 이원부호와 동일 이원부호 a를 곱한 후 1주기(N)구간 동안 적분하여 제 1자기 상관값을 구함과 동시에 상기 수신되는 이원부호 a에 이 이원부호보다 D만큼 지연되고 반전되는 이원부호 를 곱한 후 1주기 구간에 걸처 적분하여 제 2자기 상관값을 구하는 단계와, 상기 제 1자기 상관값과 제 2자기 상관값을 합산하는 단계와, 상기 각 상관값의 합산값을 기설정 임계치와 비교하여 이원부호의 프레임 동기를 검출하는 단계를 구비한다.The present invention is to provide a method of detecting the synchronization of the binary code is correct, multiply the received binary code a and the same binary code a and the integrated binary code a built in the receiver and then integrate for one period (N) period to the first magnetic The binary code is delayed and inverted by the D binary code a to the received binary code a at the same time. Multiplying to obtain a second autocorrelation value by integrating over one period, summing the first autocorrelation value and the second autocorrelation value, and adding the sum of the correlation values to a preset threshold; And detecting frame synchronization of the binary code by comparison.
Description
본 발명은 이원부호의 프레임 동기 검출 방법에 관한 것으로, 특히 한 번 수신되는 이원부호에 대하여 두 번의 임계치를 적용하여 이원부호의 프레임 동기상태를 검출하도록 하는 이중 임계치 적용에 의한 이원부호의 프레임 동기 검출 방법에 관한 것이다.The present invention relates to a frame synchronization detection method of a binary code, and more particularly, to a frame synchronization detection method of a binary code by applying a double threshold value to detect a frame synchronization state of a binary code by applying two thresholds to a binary code received once. will be.
종래의 이원부호 프레임 동기 검출방법은 도 1에 도시된 바와 같다.The conventional binary coded frame synchronization detection method is shown in FIG.
상기 도 1에서 사용하는 이원부호 a는 a=(a1, a2...aN-1, aN)(단 N은 주기)이라 정의 되고 이원부호 a의 자기 상관함수는 수학식 1과 같이 표현된다.The binary code a used in FIG. 1 is defined as a = (a 1 , a 2 ... a N-1 , a N ) (where N is a period) and the autocorrelation function of the binary code a is It is expressed as
상기 이원부호 a중에서 지연이 영일 때 최대값 "N"을 갖고, 지연이 N/2일 때 음의 최대값 "-B"을 가지며 그 이외의 지연에서는 영의 자기 상관값을 갖는 이원부호가 존재한다.Among the binary codes a, there is a binary code having a maximum value "N" when the delay is zero, a negative maximum value "-B" when the delay is N / 2, and a zero autocorrelation value at other delays. .
이러한 특성을 갖는 이원부호는 유럽 이동 통신 시스템인 GSM(Group Special Mobile)시스템 등에서 동기용으로 사용한다.The binary code having such characteristics is used for synchronization in a GSM (Group Special Mobile) system, which is a European mobile communication system.
그리고 이러한 이원부호의 자기 상관함수 특성을 수학식 2로 나타내진다.In addition, the autocorrelation function of the binary code is represented by Equation 2.
여기서 N > B > 0의 관계가 있다.Where N> B> 0.
종래에 의한 이원부호의 프레임 동기 검출 방법은 도 1에서 도시된 바와 같이, 곱셈기(11)에서 수신되는 이원부호 a에 수신기에 내장된 동일이원 부호 a를 곱한 후 1주기 구간에 걸처 적분기(12)에서 적분함으로써 자기 상관값을 구한다.In the conventional frame synchronization detection method of binary code, as shown in FIG. 1, the binary code a received by the multiplier 11 is multiplied by the same binary code a built in the receiver, and then the integrator 12 is spread over one period. Find the autocorrelation value by integrating at.
이와같은 자기 상관값은 임계치 비교기(13)에서 비교되어 임계치 이상값을 취함으로써 이원부호의 동기가 검출되며, 이와같은 이원부호의 동기를 이용하여 수신신호와 프레임 동기를 맞추게 된다.This autocorrelation value is compared in the threshold comparator 13 to take a threshold value or more and the synchronization of the binary code is detected, and the synchronization of the received signal and the frame is synchronized using the synchronization of the binary code.
그러나 종래의 이원부호의 프레임 동기 검출 방법은 수신되는 이원부호에 대하여 한 번의 임계치를 적용하여 이원부호의 프레임 동기를 검출하기 때문에 잡음이나 에러가 발생될 때 정확한 이원부호의 동기 상태를 검출할 수 없다는 문제점이 있었다.However, the conventional binary coded frame synchronization detection method has a problem that it is impossible to detect the exact binary coded synchronization state when a noise or an error occurs because the frame synchronization of the binary code is detected by applying one threshold to the received binary code. .
따라서 본 발명은 이와 같은 종래 기술의 문제점을 감안하여 발명한 것으로 정확한 이원부호의 동기 검출 방법을 제공함을 목적으로 한다.Accordingly, the present invention has been made in view of the above problems of the prior art, and an object of the present invention is to provide an accurate detection method for synchronization of binary codes.
이와 같은 목적을 달성하기 위한 본 발명의 이원 부호의 프레임 동기 검출방법은, 수신되는 이원부호 a에 수신기에 내장된 상기 수신된 이원부호와 동일 이원부호 a를 곱한 후 1주기(N)구간에 걸쳐 적분하여 제 1자기 상관값을 구함과 동시에 상기 수신되는 이원부호 a에 이 이원부호보다 D만큼 지연되고 반전되는 이원부호 를 곱한후 역시 1주기 구간에 걸처 적분하여 제 2자기 상관값을 구하는 단계와, 상기 제 1자기 상관값과 제 2자기 상관값을 합산하는 단계와, 상기 각 상관값의 합산값을 기설정 임계치와 비교하여 이원부호의 프레임 동기를 검출하는 단계를 구비함을 특징으로 한다.In the frame synchronization detection method of the binary code of the present invention for achieving the above object, the received binary code a multiplied by the received binary code built in the receiver and the same binary code a over a period (N) period Integrate to obtain the first autocorrelation value by integrating and simultaneously invert the received binary code a by D than this binary code and invert it. Multiplying and integrating over one period to obtain a second autocorrelation value, summing the first autocorrelation value and the second autocorrelation value, and adding the sum of each correlation value to a preset threshold; And detecting frame synchronization in binary code.
이하 첨부 도면을 참조하여 본 발명의 실시예에 대하여 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명에 따른 이원부호의 프레임 동기 검출 방법을 설명하기 위한 도면으로서, 본 발명에 따른 이원부호의 프레임 동기 검출방법은, 먼저 수신되는 이원부호 a=(a1, a2, .... aN-1, aN)에 수신기에 내장된 상기 이원부호와 동일한 이원부호 a를 곱셈기(21)에서 곱한 후 1주기 기간(T)동안 걸처 적분기(23)에서 적분하여 자기 상관값 P3를 구한다.2 is a view for explaining a frame synchronization detection method of a binary code according to the present invention, the frame synchronization detection method of a binary code according to the present invention, first received binary code a = (a 1 , a 2 , .... a N-1 , a N ) is multiplied by a multiplier 21 with the same binary code a embedded in the receiver, and then integrated in the integrator 23 over one period T to obtain the autocorrelation value P 3 . Obtain
또한 곱셈기(22)에서 수신되는 동일 이원부호 a에 이 이원부호와는 N/2(단 N은 주기)만큼 지연되고 반전되는 이원부호 을 곱한 후 적분기(24)에서 1주기 기간(T)동안 적분하여 자기 상관값 P4를 구한다.In addition, the binary code a received by the multiplier 22 is a binary code which is delayed and inverted by N / 2 (where N is a period) from the binary code a. After multiplying by and integrating integrator 24 for one period period (T) to obtain the autocorrelation value P 4 .
이렇게 구한 각 상관값(P3, P4)을 덧셈기(25)에서 합산하여 합산값 P5를 구한다.The correlation values P 3 and P 4 thus obtained are summed in the adder 25 to obtain a sum P 5 .
이어 임계치 비교기(28)에서 상기 합산값 P5를 기 설정된 2개의 임계치를 적용, 비교하여 출력값 P6을 얻으므로써 이원부호의 프레임 동기를 검출한다.The threshold comparator 28 detects the frame synchronization of the binary code by applying and comparing the sum value P 5 with two preset threshold values to obtain an output value P 6 .
이와 같은 본 발명의 동기 검출 방법에 따르면, 먼저 수신되는 이원부호 a에 이원부호와 동일한 수신기 내장 이원부호 a를 곱한 후 1주기(N) 기간에 대하여 적분하면, 도 2에 도시된 P3의 자기 상관값을 구하게 된다.According to the synchronization detection method of the present invention, if the first binary signal a received is multiplied by the same receiver internal binary code a as the binary code, and then integrated over one period (N) period, the magnetism of P 3 shown in FIG. The correlation value is obtained.
그리고 상기 수신되는 이원부호 a에 수신기에 내장된 이원부호 보다 N/2(단 N은 주기)만큼 지연되고 반전되는 이원부호 를 곱한 후 1주기 기간에 대하여 적분하면 도 2에 도시된 P4의 상관값을 구하게된다. The binary code is delayed and inverted by N / 2 (where N is a period) than the binary code embedded in the receiver in the received binary code a. After multiplying and integrating over one period, the correlation value of P 4 shown in FIG. 2 is obtained.
이들 상관값(P3, P4)을 합산하면 도 2에 도시된 P5의 상관값을 얻을 수 있고 이 상관값 p5를 임계치 비교기를 통하여 2중의 임계치를 적용 비교하여 출력하면, P6의 결과값을 얻게되고 이 결과값 P6은 이원부호의 프레임 동기상태를 지연이 없는 상태와 N/2만큼 지연된 상태에서의 동기상태를 구할 수 있게되어 2중으로 프레임 동기를 체크할 수 있게 된다.The correlation value (P 3, P 4) is achieved by a correlation value of the P 5 shown in Figure 2, the sum of, and if the output as compared to applying the threshold value of the second through the threshold comparator to the correlation value p 5, the P 6 The result value is obtained, and the result value P 6 can obtain the synchronization status of the binary coded frame synchronization state with no delay and delayed by N / 2, so that the frame synchronization can be checked twice.
본 발명의 상기 실시예에는 제 2자기 상관값을 구함에 있어서, 수신되는 이원부호 a에, 이 수신 이원부호 a와는 N/2 지연되고 반전되는 수신기 내장 이원부호 를 이용하였으나, 본 발명은 이것에 한정되는 것이 아니고 상기 이원부호의 자기 상관값이 수학식 3과 같은 특성을 나타내는 이원부호를 사용함과 동시에In the above embodiment of the present invention, in obtaining a second autocorrelation value, a receiver built-in binary code is delayed and inverted to a received binary code a by N / 2 with the received binary code a. However, the present invention is not limited thereto, and at the same time using a binary code in which the autocorrelation value of the binary code exhibits the same characteristics as in Equation (3).
수신되는 이원부호 a에 대하여 D만큼 지연되고 반전되는 인 수신기 내장 이원부호를 이용하여 제 2자기 상관값을 구하여도 된다.Delayed and inverted by D with respect to the received binary code a The second autocorrelation value may be obtained using the binary coder built-in receiver.
이상과 같이 본 발명은 2중의 임계값을 적용하여 이원부호의 프레임 동기를 검출하기 때문에 잡음이나 오신호에 대하여 2중으로 체크할 수 있어 보다 정확한 이원부호의 동기 검출을 할 수 있다는 효과가 있다.As described above, the present invention has the effect of double-checking noise or false signals by detecting the double-valued frame synchronization by applying a double threshold value, thereby enabling more accurate double-sided synchronization detection.
도 1은 종래에 의한 이원부호의 프레임 동기 검출방법을 설명하기 위한 도면,1 is a view for explaining a conventional frame synchronization detection method of binary code;
도 2는 본 발명에 의한 이원부호의 프레임 동기 검출방법을 설명하기 위한 도면이다.2 is a view for explaining a frame synchronization detection method of binary code according to the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
11,21,22 : 곱셈기 12,23,24 : 적분기11,21,22 Multiplier 12,23,24 Integrator
13,25 : 덧셈기 14,26 : 임계치 비교기13,25 Adder 14,26 Threshold Comparator
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06244829A (en) * | 1993-02-16 | 1994-09-02 | N T T Idou Tsuushinmou Kk | Correlation detection circuit |
| JPH06252966A (en) * | 1993-02-26 | 1994-09-09 | Matsushita Electric Ind Co Ltd | Frame signal processor |
| JPH0818548A (en) * | 1994-06-28 | 1996-01-19 | Kokusai Electric Co Ltd | Frame synchronization method |
| US5732114A (en) * | 1994-11-07 | 1998-03-24 | Alcatel Telspace | Method of detecting reference symbols for a digital data receiver |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06244829A (en) * | 1993-02-16 | 1994-09-02 | N T T Idou Tsuushinmou Kk | Correlation detection circuit |
| JPH06252966A (en) * | 1993-02-26 | 1994-09-09 | Matsushita Electric Ind Co Ltd | Frame signal processor |
| JPH0818548A (en) * | 1994-06-28 | 1996-01-19 | Kokusai Electric Co Ltd | Frame synchronization method |
| US5732114A (en) * | 1994-11-07 | 1998-03-24 | Alcatel Telspace | Method of detecting reference symbols for a digital data receiver |
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