KR100574478B1 - Repair circuit of memory device - Google Patents

Abstract

The present invention relates to a repair circuit of a memory device, and more particularly, by reducing the number of redundancy word lines by half, selectively controlling one redundancy word line through two fuse boxes, and forming the fuse box as an antifuse. In addition to maximizing chip area usage and efficiency, repairs can be performed at the package level.

Memory Device Repair Circuit Anti-Fuse Redundancy Word Line

Description

Repair circuit of memory device             

1 is a block diagram illustrating a repair circuit of a conventional memory device.

FIG. 2 is a circuit diagram illustrating a programming state of a fuse constituting the fuse box of FIG. 1.

3 is a block diagram illustrating a repair circuit of a memory device according to the present invention.

4 is a diagram illustrating an anti-fuse programming circuit of the fuse box of FIG. 3.

   -Explanation of symbols for the main parts of the drawings-

10, 210: operation switch unit 20, 220: address input unit

30, 260: Output AF: Anti-fuse

230: breakdown voltage supply unit 240: current blocking unit

250 latch part

The present invention relates to a repair circuit of a memory device, and more particularly, by reducing the number of redundancy word lines by half, selectively controlling one redundancy word line through two fuse boxes, and forming the fuse box as an antifuse. The present invention relates to a repair circuit of a memory device capable of maximizing chip area use and efficiency as well as performing repair at a package level.

If a defect occurs even in one cell in a memory device composed of many fine cells, it cannot be treated as a memory and thus is treated as a defective product. However, as the technology of DRAM advances, it is inefficient to reduce the yield of discarding defective products even though there is a high probability that defects occur only in a small number of cells. Therefore, in this case, a method of increasing the yield by adopting a redundant memory cell installed in the DRAM in advance is replaced. As redundancy circuits are installed, the area of the chip increases and the number of tests necessary for remedy of defects becomes a problem, but in DRAM, the area of the chip does not increase so much that it is adopted from 64K to 256K DRAM in earnest.

The redundancy circuit of memory cells is installed for each sub-array block, and spare ROW and COLUMN are installed in advance so that defects occur and replace defective memory cells with redundancy memory cells in ROW / COLUMN units. When the wafer processor is terminated, the internal circuit performs programming that selects the defective memory cell through the test and replaces the corresponding address with the address signal of the spare cell. Therefore, when an address corresponding to the defective line is input during actual use, a spare is instead provided. The selection changes to the line. These programming methods include electric fuses that melt and blow fuses due to overcurrent, burned fuses by laser beams, and programming into EPROM memory cells. Among these methods, a laser cutting method is widely used because of its simple, reliable and easy layout, and polysilicon wiring or metal wiring is used as the fuse material.

By using the fuse, the fuse corresponding to the address of the defective cell is cut and replaced with the redundant cell by pointing to the redundant row address or the redundancy column address.

As chips become more integrated and design rules become smaller, word lines can be used from metal strapping to sub-word lines to ensure process margins for word lines. I was a master.

1 is a block diagram illustrating a repair circuit of a conventional memory device.

As shown here, the redundancy word lines in each cell block (cell block 0, ..., cell block 7) have two four at the top (rwl_up0, rwl_up1) and two at the bottom (rwl_dn0, rwl_dn1). . Therefore, in the cell array method of eight cell blocks (cell block 0, ..., cell block 7), there are 24 redundancy word lines. One redundancy word line control circuits rwl00, rwl01, ..., rwl70, and rwl71 are provided for each of the two redundancy word lines, and 16 fuse boxes 0, fuse box 15, and fuse box 15 are provided.

FIG. 2 is a circuit diagram illustrating a programming state of a fuse constituting the fuse box of FIG. 1.

As shown here is connected between the operation switch unit 10 for precharging to the power supply voltage (VCC) by the operation signal (A), the operation switch unit 10 and the ground via the fuse unit (PF) Turned on to the address signal ADDR of the defective circuit to output the address input unit 20 for detecting the cutting state of the fuse unit PF, and the voltage value of one end of the operation switch unit 20 and the fuse unit PF. It consists of an output unit 30 for.

Referring to the general repair circuit made as described above is as follows.

When the operation signal A is input at a low potential, the operation switch unit 10 is turned on so that the power supply voltage VCC is applied to the fuse unit PF. In this state, when the address signal ADDR is input to the address input unit 20, the NMOS transistor of the bit having the high potential value is turned on so that the power supply voltage VCC supplied through the operation switch unit 10 is turned on to supply the NMOS transistor. The pass is formed so that the potential of the node 'a' has a low potential. This value is inverted through the inverter of the output unit 30 so that the output value nrdb maintains the high potential in the normal state.

In this state, when the fuse formed of the resistive material is cut by the laser beam, the current path formed with the address input unit 20 through the fuse unit PF through the operation switch unit 10 is blocked, so that the potential of the node 'a' High potential This value is inverted by the inverter of the output unit 30 so that the output value nrdb changes to a low potential.

When an address indicating the defective cell is input by receiving the output value nrdb, a redundancy cell is replaced to perform a normal operation.

When repairing a bad word line in the above manner, although many row address defects do not occur more than the column addresses that dominate the defects, more redundancy word lines than necessary are installed and the number of fuse boxes is large. This becomes complicated.

For this reason, there is a problem that the circuit for operating the redundancy word line becomes complicated and the layout area of the fuse boxes is large.

In addition, there is a problem in that the repair cannot be performed in the package step because the fuse is cut by the equipment such as a laser to repair the redundancy word line.

The present invention has been made to solve the above problems, and an object of the present invention is to reduce the number of redundancy word lines in half and to selectively control one redundancy word line through two fuse boxes and to control the fuse box. By forming a fuse, it is possible to maximize chip area use and efficiency, and to provide a repair circuit of a memory device that can perform repairing at a package level.

According to the present invention for realizing the above object, a plurality of redundancy word lines formed in a plurality of cell blocks constituting a cell array block and any one redundancy word line formed in the plurality of cell blocks are fixed as well as other adjacent cells. A plurality of redundancy word line control circuits for selectively controlling another redundancy word line in the block, a first fuse box for setting redundancy word lines fixedly controlled by the plurality of redundancy word line control circuits, and a plurality of redundancy And a second fuse box configured to operate a redundancy word line selectively controlled by the word line control circuit.

In addition, the first fuse box and the second fuse box is characterized in that the anti-fuse is made of an anti-fuse which is broken by an electrical shock and changes as a resistance.

Referring to the operation of the present invention made as described above are as follows.

When a word line of a cell block constituting the cell array block is to be replaced with a redundancy word line, the antifuse of the first fuse box is programmed to be replaced with a redundancy word line fixed to and controlled by the first fuse box. If one word line is to be replaced with a redundancy word line, one is programmed with an antifuse of the first fuse box and replaced with a redundancy word line fixed to and controlled by the first fuse box. The fuses of the first fuse box and the second fuse box are programmed to be replaced by a selectively controlled redundancy word line to perform the repair.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only, and the same parts as in the conventional configuration use the same symbols and names.

3 is a block diagram illustrating a repair circuit of a memory device according to the present invention.

The cell array block of the present embodiment is composed of the 0th cell block 0 to 8th cell block 7, and the top and bottom of each of the 0th cell block 0 to 8th cell block 7. There is one redundancy word line (rwl_up, rwl_dn). Then, the operation of the zero redundancy word line control circuit rwl0 and the zero redundancy word line control circuit rwl0 for controlling the upper redundancy word line rwl_up of the zero cell block 0 is fixed. The 30th fuse box 30 and the upper redundancy word line rwl_up of the first cell block 1 are fixedly controlled, and the lower redundancy word line rwl_dn of the 0th cell block 0 is selectively selected. The first redundancy word line control circuit rwl1 controlled by the control unit and the first redundancy word line control circuit rwl1 by the first redundancy word line rwl_up_ A fuse box 31 and a forty-th fuse box 40 for setting an operation of the lower redundancy word line rwl_dn of the zeroth cell block rwl0 by the first redundancy word line control circuit rwl1. .

And a second redundancy word line control for fixedly controlling the upper redundancy word line rwl_up of the second cell block (cell block2) and selectively controlling the lower redundancy word line rwl_dn of the first cell block (cell block1). A thirty-second fuse box 32 for setting the operation of the upper redundancy word line rwl_up of the second cell block 2 by the second redundancy word line control circuit rwl2; And a forty-first fuse box 31 for setting an operation of the lower redundancy word line rwl_dn of the first cell block 1 by the redundancy word line control circuit rwl2.

In addition, the third redundancy word line control to control the upper redundancy word line rwl_up of the third cell block (cell block3) and to selectively control the lower redundancy word line rwl_dn of the second cell block (cell block2). A thirty-third fuse box 33 for setting the operation of the upper redundancy word line rwl_up of the third cell block 3 by the third redundancy word line control circuit rwl3; A third fuse box 42 for setting the operation of the lower redundancy word line rwl_dn of the second cell block 2 by the redundancy word line control circuit rwl3.

The eighth redundancy word line configured in the same manner from the fourth cell block 4 to the seventh cell block 7 and controlling the lower redundancy word line rwl_dn of the seventh cell block 7 is the same. A control circuit rwl8 and a 38th fuse box 38 for controlling the operation of the eighth redundancy word line control circuit rwl8 are further included.

4 is a diagram illustrating an anti-fuse programming circuit of the fuse box of FIG. 3.

As shown here, the operation switch unit 210 for precharging with the power supply voltage VCC, the anti-fuse AF, which is connected to the operation switch unit 210 and breaks down when an overcurrent flows, and the anti-fuse Connected between AF) and ground to enable the anti-fuse (AF) to be programmed according to the input of the faulted address, and turn on the detection signal to confirm the programmed state to detect the state of the anti-fuse (AF). The programming state of the anti-fuse AF according to the signal of the address input unit 220, the breakdown voltage supply unit 230 for supplying the high voltage HV for the total edge destruction of the anti-fuse AF, and the address input unit 220 An output block 260 for outputting the signal, and a current cut-off unit 140 for controlling a current path supplied from the breakdown voltage supply unit 230 to the antifuse AF by receiving a signal from the output unit 260, and an output unit ( 260) is input to the anti-fuse (AF) stage It consists of a latch portion 250 which is strongly stabilized by the voltage.

In the above, the antifuse AF is set such that the insulation state is maintained at the power supply voltage VCC and the insulation breakdown occurs at the high voltage HV.

That is, in the normal state, since no programming signal is input, the power supply voltage VCC is supplied to the programming circuit through the operation switch unit 210 and is precharged, and the latch unit 250 precharges the power supply voltage VCC to the power supply voltage VCC. It remains strong when the voltage is unstable.

In this state, when a programming signal for programming the antifuse AF is input, when a high voltage is supplied to the antifuse AF by the breakdown voltage supply unit 230, insulation breakdown occurs and is programmed.

After the antifuse AF is programmed in this way, when a defective address is input, the address input unit 220 is turned on according to the programmed state of the antifuse AF, and the antifuse AF is output through the output unit 260. The insulation breakdown state is output through the output unit 260.

In addition, as the anti-fuse AF breaks down, a current path through which the high voltage is supplied through the breakdown voltage supply unit 230 is formed, and the current blocking unit 240 receives a signal from the output unit 260 to block the current path. This prevents further current from being consumed.

As described above, anti-fuse is used to replace redundancy word lines with word lines that are caused by programming signals at the package level. Further, the redundancy word line control circuits for setting the operation of the redundancy word lines are selectively shared with each other to operate to control the operation of adjacent redundancy word lines.

As described above, the present invention reduces the number of redundancy word lines installed in the cell block and selectively shares and controls the redundancy word line control circuit for controlling the operation of the redundancy word line between adjacent cell blocks. The advantage is that the area of the chip for installation can be secured.

In addition, there is an advantage that the circuit can be easily configured by reducing the number of redundancy word line control circuits for controlling the operation of the redundancy word line.

On the other hand, by configuring the anti-fuse repair fuse to replace the redundant word line has the advantage that the repair can be performed at the package level.

Claims (3)

delete A plurality of redundancy word lines formed in the plurality of cell blocks constituting the cell array block; A plurality of redundancy word line control circuits for not only controlling the first redundancy word lines formed in the plurality of cell blocks but also selectively controlling second redundancy word lines of other adjacent cell blocks; A first fuse box configured to operate a redundancy word line fixedly controlled by the plurality of redundancy word line control circuits; A second fuse box configured to operate a redundancy word line selectively controlled by the plurality of redundancy word line control circuits, The first fuse box and the second fuse box may include an operation switch unit for precharging with a power supply voltage, an anti-fuse connected to the operation switch unit to cause an insulation breakdown when an overcurrent flows, and the anti-fuse and a ground connection. And an address input unit configured to detect the state of the anti-fuse by turning on a detection signal for checking the programmed state by allowing the anti-fuse to be programmed according to an input of a defective address. A breakdown voltage supply unit for supplying a high voltage, an output unit for outputting a programming state of the antifuse according to a signal of the address input unit, and a current path supplied from the breakdown voltage supply unit to the antifuse by receiving a signal of the output unit An anti-current blocking unit for intercepting the A memory device configured to include a latch which strongly stabilize the power supply voltage to the circuit jeudan repair. A first redundancy word line formed at one end of the first cell block; A second redundancy word line formed at one end of a second cell block adjacent to the first cell block; A redundancy word line control circuit which not only controls the first redundancy word line but also selectively controls a second redundancy word line of the second cell block; A first fuse box including an antifuse programmed to operate the first redundancy word line by control of a redundancy word line control circuit; And a second fuse box including an antifuse programmed to operate the second redundancy wordline under control of a redundancy wordline control circuit.

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