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KR100557923B1 - Manufacturing Method of Semiconductor Memory Device - Google Patents

Manufacturing Method of Semiconductor Memory Device Download PDF

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KR100557923B1
KR100557923B1 KR1019990024620A KR19990024620A KR100557923B1 KR 100557923 B1 KR100557923 B1 KR 100557923B1 KR 1019990024620 A KR1019990024620 A KR 1019990024620A KR 19990024620 A KR19990024620 A KR 19990024620A KR 100557923 B1 KR100557923 B1 KR 100557923B1
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film
photoresist
cell region
acid
photoresist film
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KR20010004035A (en
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마원광
이동호
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
    • H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
    • H10D84/212—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/696—Electrodes comprising multiple layers, e.g. comprising a barrier layer and a metal layer

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 셀영역의 단차로 인한 포토레지스트막의 스컴발생을 방지하여 소자의 수율을 향상시킬 수 있는 반도체 메모리 소자의 제조방법을 제공한다.The present invention provides a method of manufacturing a semiconductor memory device capable of improving the yield of the device by preventing the scum of the photoresist film due to the step of the cell region.

본 발명에 따라, 스크라이브 라인 및 셀영역이 정의되고, 상부에 절연막이 형성된 반도체 기판 상에 제 1 폴리실리콘막 및 코어 산화막을 순차적으로 형성하고, 코어산화막 및 제 1 폴리실리콘막을 패터닝하여 캐패시터 노드를 형성한다. 그런 다음, 절연막 및 캐패시터 노드의 표면에 제 2 폴리실리콘막을 형성하고, 제 2 폴리실리콘막 상에 산을 발생하는 구조가 다른 제 1 및 제 2 포토레지스트막을 순차적으로 형성한 후, 제 2 및 제 1 포토레지스트막을 순차적으로 각각 패터닝하여 스크라이브 라인을 마스킹하는 포토레지스트 패턴을 형성한다. 본 실시예에서, 제 1 포토레지스트막은 가열에 의해 산을 발생시키고, 제 2 포토레지스트막은 빛에 의해 산을 발생시킨다. 또한, 포토레지스트 패턴은 제 2 포토레지스트막을 노광한 후 현상하여 셀영역의 제 1 포토레지스트막을 노출시킨 후, 노출된 제 1 포토레지스트을 가열한 후 현상하여 셀영역을 노출시킴으로써 형성한다.According to the present invention, a capacitor layer is formed by sequentially forming a first polysilicon film and a core oxide film on a semiconductor substrate having a scribe line and a cell region and having an insulating film formed thereon, and patterning the core oxide film and the first polysilicon film. Form. Then, a second polysilicon film is formed on the surfaces of the insulating film and the capacitor node, and the first and second photoresist films having different structures for generating acid are sequentially formed on the second polysilicon film, and then the second and second Each photoresist film is sequentially patterned to form a photoresist pattern for masking a scribe line. In this embodiment, the first photoresist film generates an acid by heating, and the second photoresist film generates an acid by light. Further, the photoresist pattern is formed by exposing the second photoresist film and then developing to expose the first photoresist film of the cell region, and then heating and exposing the exposed first photoresist to expose the cell region.

Description

반도체 메모리 소자의 제조방법{Method of manufacturing semiconductor memory device}Method of manufacturing semiconductor memory device

도 1은 종래의 반도체 메모리 소자의 캐패시터 형성방법을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a method of forming a capacitor of a conventional semiconductor memory device.

도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 메모리 소자의 캐패시터 형성방법을 설명하기 위한 단면도.2A to 2D are cross-sectional views illustrating a method of forming a capacitor of a semiconductor memory device according to an embodiment of the present invention.

(도면의 주요부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)

20 : 반도체 기판 21 : 절연막20 semiconductor substrate 21 insulating film

22 : 제 1 폴리실리콘막 23 : 코어산화막22: first polysilicon film 23: core oxide film

24 : ARC막 25 : 제 2 폴리실리콘막24: ARC film 25: second polysilicon film

26 : 제 1 포토레지스트막 26: first photoresist film

27 : 제 2 포토레지스트막27: second photoresist film

300 : 캐패시터 노드300: capacitor node

본 발명은 반도체 메모리 소자의 제조방법에 관한 것으로, 특히 셀영역의 단 차로 인한 포토레지스트막의 스컴발생을 방지할 수 있는 반도체 메모리 소자의 캐패시터 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of forming a capacitor of a semiconductor memory device capable of preventing scum of a photoresist film due to a step in a cell region.

메모리 소자의 집적도가 증가됨에 따라, 셀면적 및 셀 사이의 간격은 축소되는 반면, 캐패시터는 일정용량을 보유해야 하기 때문에, 좁은 면적에 큰 용량을 가지는 캐패시터가 요구된다. 이러한 캐패시터의 용량을 극대화하기 위하여, 유전막으로서 고유전율을 가지는 절연체를 이용하거나, 스토리지 전극을 실린더 구조로 형성하여 전극의 면적을 증가시켰다.As the degree of integration of memory elements increases, the cell area and the spacing between cells decrease, while the capacitors must have a certain capacity, so a capacitor having a large capacity in a small area is required. In order to maximize the capacity of such a capacitor, an insulator having a high dielectric constant is used as the dielectric film, or a storage electrode is formed in a cylindrical structure to increase the area of the electrode.

도 1은 종래의 실린더형 캐패시터 형성방법을 설명하기 위한 단면도이다.1 is a cross-sectional view illustrating a conventional cylindrical capacitor forming method.

도 1을 참조하면, 셀영역(C) 및 스크라이브 라인(미도시)이 정의되고, 상부에 절연막(11)이 형성된 반도체 기판(10) 상에 제 1 폴리실리콘막(12), 코어 산화막(13) 및 ARC(Anti-Reflective Coating)막(14)을 순차적으로 증착한다. 그런 다음, ARC막(14), 코어산화막(13) 및 제 1 폴리실리콘막(12)을 패터닝하여 캐패시터 노드(100)를 형성하고, 절연막(11) 및 캐패시터 노드(100) 표면에 제 2 폴리실리콘막(15)을 증착한다. 그리고 나서, 제 2 폴리실리콘막(15) 상에 포토레지스트막(미도시)을 도포하고 노광 및 현상하여 상기 스크라이브 라인을 마스킹함과 더불어 셀영역(C)을 노출시키는 포토레지스트 패턴(미도시)을 형성한다. Referring to FIG. 1, a first polysilicon film 12 and a core oxide film 13 are defined on a semiconductor substrate 10 having a cell region C and a scribe line (not shown) and an insulating film 11 formed thereon. ) And ARC (Anti-Reflective Coating) film 14 is sequentially deposited. Then, the ARC film 14, the core oxide film 13 and the first polysilicon film 12 are patterned to form the capacitor node 100, and the second poly on the surface of the insulating film 11 and the capacitor node 100 The silicon film 15 is deposited. Then, a photoresist film (not shown) is applied on the second polysilicon film 15, and the photoresist pattern (not shown) is exposed and developed to mask the scribe line and to expose the cell region C. To form.

그 후, 도시되지는 않았지만, 제 2 폴리실리콘막(15)을 블랭킷식각하여 캐패시터 노드(100)의 측벽에 스페이서를 형성하고, 상기 포토레지스트막, ARC막(14) 및 코어산화막(13)을 제거하여 실린더형 스토리지 전극을 형성한다. 그 후, 유전막 및 플레이트 전극을 형성한다.After that, although not shown, the second polysilicon film 15 is blanket-etched to form a spacer on the sidewall of the capacitor node 100, and the photoresist film, the ARC film 14, and the core oxide film 13 are formed. To form a cylindrical storage electrode. Thereafter, a dielectric film and a plate electrode are formed.

즉, 스크라이브 라인을 마스킹하는 것 없이 제 2 폴리실리콘막(15)의 전면식각을 진행하게 되면, 스크라이브 라인에서 제 2 폴리실리콘막 스페이서의 떨어짐으로 인하여 다량의 파티클(particle)이 발생되므로, 스크라이브 라인을 포토레지스트 패턴으로 마스킹한 후 진행한다. That is, when the entire surface etching of the second polysilicon film 15 is performed without masking the scribe line, a large amount of particles are generated due to the drop of the second polysilicon film spacer from the scribe line. After masking with a photoresist pattern, it proceeds.

그러나, 상기한 바와 같이, 폴리실리콘막 스페이서 형성시 스크라이브 라인 을 마스킹하는 포토레지스트 패턴을 적용함으로써 스크라이브 라인에서의 파티클 발생을 방지할 수 있는 반면, 셀영역(C)에서는 고집적화에 따른 높은 어스펙트비 (aspect ratio)에 따른 단차로 인하여, 도 1에 도시된 바와 같이, 제 2 폴리실리콘막(15)이 형성된 캐패시터 노드(100) 사이에 포토레지스트막의 미반응으로 인한 스컴(200)이 발생된다. 이러한 스컴(200)은 상기한 포토레지스트 패턴의 제거시에도 완전히 제거되지 않고 남아서, 캐패시터 노드(100) 사이의 브리지 및 결함을 유발하여 소자의 신뢰성 및 수율을 저하시킨다.However, as described above, particle formation in the scribe line can be prevented by applying a photoresist pattern for masking the scribe line when forming the polysilicon film spacer, while in the cell region C, a high aspect ratio due to high integration Due to the step according to the aspect ratio, as shown in FIG. 1, the scum 200 is generated between the capacitor nodes 100 on which the second polysilicon film 15 is formed due to unreacted photoresist film. The scum 200 remains unremoved even when the photoresist pattern is removed, causing bridges and defects between the capacitor nodes 100 to lower the reliability and yield of the device.

또한, 상기한 스컴(200)을 방지하기 위하여, 노광 에너지를 증가시키게 되면 노광 시간이 길어지는 단점이 있다.In addition, in order to prevent the scum 200, when the exposure energy is increased, the exposure time is long.

따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로서, 셀영역의 단차로 인한 포토레지스트막의 스컴발생을 방지하여 소자의 수율을 향상시킬 수있는 반도체 메모리 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor memory device capable of improving the yield of the device by preventing the occurrence of scum of the photoresist film due to the step of the cell region. have.

상기한 본 발명의 목적을 달성하기 위하여, 본 발명에 따라, 스크라이브 라인 및 셀영역이 정의되고, 상부에 절연막이 형성된 반도체 기판 상에 제 1 폴리실리콘막 및 코어 산화막을 순차적으로 형성하고, 코어산화막 및 제 1 폴리실리콘막을 패터닝하여 캐패시터 노드를 형성한다. 그런 다음, 절연막 및 캐패시터 노드의 표면에 제 2 폴리실리콘막을 형성하고, 제 2 폴리실리콘막 상에 산을 발생하는 구조가 서로 다른 제 1 및 제 2 포토레지스트막을 순차적으로 형성한 후, 제 2 및 제 1 포토레지스트막을 상기 셀영역 내의 캐패시터 노드 사이에 잔류되지 않도록 순차적으로 각각 패터닝하여 스크라이브 라인을 마스킹하는 포토레지스트 패턴을 형성한다.In order to achieve the above object of the present invention, according to the present invention, the first polysilicon film and the core oxide film are sequentially formed on a semiconductor substrate having a scribe line and a cell region defined thereon and an insulating film formed thereon, and a core oxide film. And patterning the first polysilicon film to form a capacitor node. Then, a second polysilicon film is formed on the surfaces of the insulating film and the capacitor node, and the first and second photoresist films having different structures of generating acid on the second polysilicon film are sequentially formed, and then the second and The first photoresist film is sequentially patterned so as not to remain between the capacitor nodes in the cell region, thereby forming a photoresist pattern for masking a scribe line.

본 실시예에서, 제 1 포토레지스트막은 가열에 의해 산을 발생시키고, 제 2 포토레지스트막은 빛에 의해 산을 발생시킨다. 또한, 포토레지스트 패턴은 제 2 포토레지스트막을 노광한 후 현상하여 셀영역의 제 1 포토레지스트막을 노출시킨 후, 노출된 제 1 포토레지스트막을 가열한 후 현상하여 셀영역을 노출시켜 형성한다.In this embodiment, the first photoresist film generates an acid by heating, and the second photoresist film generates an acid by light. In addition, the photoresist pattern is formed by exposing the second photoresist film and then developing to expose the first photoresist film of the cell region, and then heating and exposing the exposed first photoresist film to expose the cell region.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 캐패시터 형성방법을 설명하기 위한 단면도이다.2A through 2D are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device in accordance with an embodiment of the present invention.

도 2a를 참조하면, 스크라이브 라인(미도시) 및 셀영역(C)이 정의되고, 상부에 절연막(21)이 형성된 반도체 기판(20) 상에 제 1 폴리실리콘막(22), 코어 산화막(23) 및 ARC막(24)을 순차적으로 증착한다. 그런 다음, ARC막(24), 코어산화막 (23) 및 제 1 폴리실리콘막(22)을 패터닝하여 캐패시터 노드(300)를 형성하고, 절연막(21) 및 캐패시터 노드(300)의 표면에 제 2 폴리실리콘막(25)을 증착한다. Referring to FIG. 2A, a first polysilicon film 22 and a core oxide film 23 are formed on a semiconductor substrate 20 on which a scribe line (not shown) and a cell region C are defined, and an insulating film 21 is formed thereon. ) And the ARC film 24 are sequentially deposited. Then, the ARC film 24, the core oxide film 23, and the first polysilicon film 22 are patterned to form the capacitor node 300, and the second insulating film 21 and the capacitor node 300 are formed on the surface of the second. The polysilicon film 25 is deposited.

그리고 나서, 제 2 폴리실리콘막(25) 상에 산을 발생하는 구조가 다른 제 1 및 제 2 포토레지스트막(26, 27)을 순차적으로 형성한다. 즉, 도 2b에 도시된 바와 같이, 먼저 제 2 폴리실리콘막(25) 상에 가열에 의해 산을 발생시키는 제 1 포토레지스트막(26)을 형성하고, 도 2c에 도시된 바와 같이, 제 1 포토레지스트막 (26) 상부에 빛에 의해 산을 발생시키는 제 2 포토레지스트막(27)을 형성한다. Then, on the second polysilicon film 25, first and second photoresist films 26 and 27 having different structures of generating acid are sequentially formed. That is, as shown in FIG. 2B, first, a first photoresist film 26 which generates an acid by heating on the second polysilicon film 25 is formed, and as shown in FIG. 2C, the first On the photoresist film 26, a second photoresist film 27 for generating acid by light is formed.

도 2d를 참조하면, 제 2 포토레지스트막(27)을 노광한 후 현상하여, 셀영역(C)의 제 1 포토레지스트막(26)을 노출시킨 후, 노출된 제 1 포토레지스트막 (26)을 가열한 후 현상하여 셀영역(C)을 노출시킨다. 이에 따라, 도시되지는 않았지만, 스크라이브 라인 상에는 제 1 및 제 2 포토레지스트막(26, 27)의 이중막으로 이루어진 포토레지스트 패턴이 형성된다.Referring to FIG. 2D, the second photoresist film 27 is exposed and developed to expose the first photoresist film 26 in the cell region C, and then the exposed first photoresist film 26 is exposed. After heating, it is developed to expose the cell region (C). Accordingly, although not shown, a photoresist pattern including double layers of the first and second photoresist films 26 and 27 is formed on the scribe line.

그 후, 도시되지는 않았지만, 제 2 폴리실리콘막(25)을 블랭킷식각하여 셀영역(C)의 캐패시터 노드(300)의 측벽에 스페이서를 형성하고, 상기 포토레지스트 패턴, ARC막(24) 및 코어산화막(23)을 제거하여 실린더형 스토리지 전극을 형성한다. 그 후, 유전막 및 플레이트 전극을 형성한다.Thereafter, although not shown, the second polysilicon film 25 is blanket-etched to form a spacer on the sidewall of the capacitor node 300 of the cell region C, and the photoresist pattern, the ARC film 24 and The core oxide film 23 is removed to form a cylindrical storage electrode. Thereafter, a dielectric film and a plate electrode are formed.

상기한 본 발명에 의하면, 폴리실리콘막 스페이서 형성시 스크라이브 라인을 마스킹하는 포토레지스트 패턴을 가열에 의해 산을 발생하는 제 1 포토레지스트막과 노광에 의해 산을 발생하는 제 2 포토레지스트막을 가열 또는 노광으로 각각 패터닝하여 형성한다. 이에 따라, 포토레지스트막의 미반응에 의한 패턴 사이의 스컴발생이 방지되어 캐패시터 노드 사이의 브리지 및 결함발생이 방지됨으로써, 소자의 신뢰성 및 수율이 향상된다. 또한, 비교적 낮은 노광 에너지, 예컨대 종래의 1/5 정도의 노광에너지로 노광이 진행되기 때문에, 노광시간이 단축되는 효과를 얻을 수 있다.According to the present invention described above, heating or exposing a first photoresist film that generates acid by heating a photoresist pattern that masks a scribe line when forming a polysilicon film spacer and a second photoresist film that generates acid by exposure It is formed by patterning each. Accordingly, the occurrence of scum between patterns due to unreacted photoresist film is prevented, and the occurrence of bridges and defects between capacitor nodes is prevented, thereby improving the reliability and yield of the device. In addition, since the exposure proceeds at a relatively low exposure energy, for example, about 1/5 of the conventional exposure energy, the effect of shortening the exposure time can be obtained.

또한, 본 발명읕 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.
In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

Claims (5)

스크라이브 라인 및 셀영역이 정의되고, 상부에 절연막이 형성된 반도체 기판 상에 제 1 폴리실리콘막 및 코어 산화막을 순차적으로 형성하는 단계;Sequentially forming a first polysilicon film and a core oxide film on a semiconductor substrate having a scribe line and a cell region defined thereon and an insulating film formed thereon; 상기 코어산화막 및 제 1 폴리실리콘막을 패터닝하여 캐패시터 노드를 형성하는 단계;Patterning the core oxide layer and the first polysilicon layer to form a capacitor node; 상기 절연막 및 캐패시터 노드의 표면에 제 2 폴리실리콘막을 형성하는 단계;Forming a second polysilicon film on surfaces of the insulating film and the capacitor node; 상기 제 2 폴리실리콘막 상에 산을 발생하는 구조가 서로 다른 제 1 및 제 2 포토레지스트막을 순차적으로 형성하는 단계; 및Sequentially forming first and second photoresist films having different structures of generating acid on the second polysilicon film; And 상기 제 2 및 제 1 포토레지스트막을 상기 셀영역 내의 캐패시터 노드 사이에 잔류되지 않도록 순차적으로 각각 패터닝하여 상기 스크라이브 라인을 마스킹하는 포토레지스트 패턴을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 메모리 소자의 제조방법.And sequentially patterning the second and first photoresist films so as not to remain between the capacitor nodes in the cell region, thereby forming a photoresist pattern for masking the scribe lines. Way. 제 1 항에 있어서, 상기 제 1 포토레지스트막은 가열에 의해 산을 발생시키는 것을 특징으로 하는 반도체 메모리 소자의 제조방법.The method of claim 1, wherein the first photoresist film generates an acid by heating. 제 1 항에 있어서, 상기 제 2 포토레지스트막은 빛에 의해 산을 발생시키는 것을 특징으로 하는 반도체 메모리 소자의 제조방법.The method of claim 1, wherein the second photoresist film generates an acid by light. 제 1 항에 있어서, 상기 제 1 포토레지스트막은 가열에 의해 산을 발생시키고, 상기 제 2 포토레지스트막은 빛에 의해 산을 발생시키는 것을 특징으로 하는 반도체 메모리 소자의 제조방법.The method of claim 1, wherein the first photoresist film generates an acid by heating, and the second photoresist film generates an acid by light. 제 1 항 또는 제 4 항에 있어서, 상기 포토레지스트 패턴을 형성하는 단계는 The method of claim 1, wherein the forming of the photoresist pattern is performed. 상기 제 2 포토레지스트막을 노광한 후 현상하여 상기 셀영역의 제 1 포토레지스트막을 노출시키는 단계; 및 Exposing and developing the second photoresist film to expose the first photoresist film in the cell region; And 상기 노출된 제 1 포토레지스트막을 가열한 후 현상하여 상기 셀영역을 노출시키는 단계를 포함하는 것을 특징으로 하는 반도체 메모리 소자의 제조방법.And heating and exposing the exposed first photoresist film to expose the cell region.
KR1019990024620A 1999-06-28 1999-06-28 Manufacturing Method of Semiconductor Memory Device Expired - Fee Related KR100557923B1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990016771A (en) * 1997-08-19 1999-03-15 윤종용 Capacitor Manufacturing Method for Dynamic Memory Cells

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