KR100552810B1 - Metal wiring formation method of semiconductor device - Google Patents

Abstract

Stacking a first etch stop film, an interlayer insulating film, a second etch stop film, and a wiring insulating film on a semiconductor substrate having a predetermined substructure, forming a contact hole pattern on the wiring insulating film, and exposing the contact hole pattern as a mask. Etching the formed wiring insulating film, the first etch stop film, and the interlayer insulating film to form a contact hole, removing the contact hole pattern, and then forming a trench pattern on the wiring insulating film, wherein the wiring insulating film is exposed using the trench pattern as a mask. Etching to form a trench, and after removing the trench pattern, removing the exposed first etch stop layer and the second etch stop layer, wherein the first etch stop layer and the second etch stop layer are 5 to 30. A metal wiring formation method for a semiconductor device, which is an oxynitride film containing% silicon.

Etch stop layer, oxynitride layer

Description

Metal wire formation method of semiconductor device {METAL LINE FORMATION METHOD OF SEMICONDUCTOR DEVICE}

1 to 6 are diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention for each manufacturing process.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming metal wirings in semiconductor devices using a dual damascene process.

Generally, the metal wiring of a semiconductor element connects the circuit formed in the semiconductor substrate through the electrical connection and pad connection between semiconductor elements using metal thin films, such as aluminum, its alloy, and copper.

In order to connect the device electrodes and pads separated by an insulating film such as an oxide film, the metal wiring is first formed by selectively etching the insulating film to form a contact hole, and using a barrier metal and tungsten to form a metal plug through the contact hole. Form. Then, a metal thin film is formed on the upper portion, and patterned to form a metal wiring for connecting the device electrode and the pad.

In order to pattern the metal wiring, a photolithography process is mainly used, and as the semiconductor device becomes smaller, the CD (critical dimension) of the metal wiring is gradually smaller, making it difficult to form a fine pattern of the metal wiring. have. Therefore, a damascene process is introduced to prevent such a problem and form a fine pattern metal wiring.

The damascene process forms a tungsten plug in the contact hole of the insulating film, and then deposits an upper insulating film such as an oxide film on the insulating film, and removes only the upper insulating film at the portion where the metal wiring pattern is to be formed by the photolithography process. By depositing a metal thin film and then planarizing the metal thin film, a fine pattern metal wiring layer is formed.

In recent years, a dual damascene process for forming metal wirings integrally connected to the lower conductive film without the formation of metal plugs such as tungsten plugs has been introduced.

An etch stop layer used in the dual damascene process in which an etch stop layer and an insulating layer are stacked in a double layer and then etched using the etch selectivity of the etch stop layer and the insulating layer is used as a nitride layer (SiN) or an oxynitride layer. (SiON) is mainly used, and Florin silicate glass (FSG) is mainly used as the insulating film.

However, when such an etch stop film and the FSG are stacked, stress between the films increases and poor contact between the interfaces occurs. Therefore, a bubbling defect is likely to occur in a subsequent metal wiring process, and thus a problem occurs that yield, characteristics, and reliability of a semiconductor device are deteriorated.

SUMMARY OF THE INVENTION An aspect of the present invention provides a method for forming a metal wiring in a semiconductor device in which a contact hole and a trench can be easily formed in a damascene process, and an etch stop film is formed to improve a difference in etching rate between an interlayer insulating film and a wiring insulating film. To provide.

In the method of forming a metal wiring of a semiconductor device according to the present invention, the first etching stop layer, the interlayer insulating film, the second etch stop film and the wiring insulating film are stacked on a semiconductor substrate having a predetermined substructure, and the contact hole pattern is formed on the wiring insulating film. Forming a contact hole by etching the exposed wiring insulating layer, the first etch stop layer, and the interlayer insulating layer by using the contact hole pattern as a mask, removing the contact hole pattern, and then forming a trench on the wiring insulating layer. Forming a pattern, etching the exposed wiring insulating layer using the trench pattern as a mask to form a trench, removing the trench pattern, and then removing the exposed first etch stop layer and the second etch stop layer And the first etching stop film and the second etching stop film are oxynitride films containing 5 to 30% of silicon. It is preferred.

In addition, the silicon is preferably one of amorphous silicon or polysilicon.

The first etch stop layer and the interlayer insulating layer may be formed in the same chamber, and the second etch stop layer and the wiring insulating layer may be formed in the same chamber.

In addition, after forming the first etch stop layer, it is preferable to form an interlayer insulating film without a vacuum state, and after forming the second etch stop layer, a wiring insulation layer may be formed without a vacuum state.

The first etch stop film and the second etch stop film are preferably contained oxynitride films of 30% or more and 70% or less of Si-N.

In addition, the first etch stop layer and the second etch stop layer is preferably formed by a PECVD method using a high frequency power source of 13.56 MHz or 100 Hz to 1 MHz.

In addition, the PECVD method preferably applies a substrate bias with a plasma generation power of 0 to 2 KW.

In addition, the PECVD method is preferably carried out under a pressure of 0.5 to 20 torr.

Also, the PECVD method is preferably used in a gas a mixture of SiH _4, from 0 to 5000 sccm of N ₂ O, 0 to 50000 sccm N ₂ in the range of 0 to 500 sccm.

In addition, the PECVD method preferably uses a mixed gas for deposition diluted by adding an inert gas.

In addition, the inert gas is preferably any one of He, Ne or Ar.

In addition, depositing a barrier metal film on the lower structure including the contact hole and the inner wall of the trench, depositing a metal seed film on the barrier metal film, depositing a metal thin film in the contact hole and the trench, chemical metallic polishing The method may further include removing the metal thin film, the metal seed film, and the barrier metal film on the wiring insulating film by the process.

Then, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A method of forming metal wirings of a semiconductor device according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 to 6 are cross-sectional views illustrating a method of forming metal wires in a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 1, a method of forming metal wires in a semiconductor device according to an embodiment of the present invention is first performed by a conductive layer and a subsequent process on a semiconductor substrate 1 including a thin film on which a device electrode or a conductive layer is formed. The first etch stop layer 2 is formed in order to prevent reaction with the metal lines to be formed and to use it as an etch stop point when the interlayer insulating layer is etched in a subsequent process. When the interlayer insulating layer 3 is deposited on the first etch stop layer 2, and the wiring insulating layer is etched on the interlayer insulating layer 3 in a subsequent process, the second etch stop layer may be used as an etch stop point. 4) form. Subsequently, a wiring insulating layer 5 for forming a metal wiring layer is deposited on the second etch stop layer 4.

In this case, the first etch stop layer 2 and the second etch stop layer 4 may be formed of an oxynitride layer (SiON) using PECVD (Plasma Enhanced CVD) equipment.

When the first etch stop film 2 and the second etch stop film 4 are formed of an oxynitride film, amorphous silicon or the like is controlled by adjusting equipment factors such as the mixing ratio of the deposition gas, the plasma excitation power, the substrate temperature, and the chamber pressure. A first etch stop film 2 and a second etch stop film 4 having specifically polysilicon, Si-N, and Si-O contents are formed.

The oxynitride film is made of amorphous silicon or polysilicon, Si-N, and Si-O, and the first etch stop film 2 and the second etch stop film 4 made of the oxynitride film are 5 to 30% of amorphous material. Refractive index (n), absorption constant formed of oxynitride film containing silicon or polysilicon and containing 30% or more and 70% or less of Si-N and usable as Inter later Dielectric (ILD) or Inter Metal Dielectric (IMD) It is desirable to maintain the value (k). Here,% means volume%.

The first etch stop film 2 and the second etch stop film 4 are preferably formed by a PECVD method using a high frequency power source of 13.56 MHz or 100 Hz to 1 MHz. In the PECVD method, the substrate bias may be applied at a plasma generation power of 0 to 2 KW, and the pressure may be increased under a pressure of 0.5 to 20 torr to increase the thin film density.

In the PECVD method, a mixture of 0 to 500 sccm of SiH ₄ , 0 to 5000 sccm of N ₂ O and 0 to 50000 sccm of N ₂ is used, and an inert gas such as He, Ne, or Ar is added thereto. The thin film uniformity can be improved by using the diluted mixed gas for deposition.

The first etch stop film 2 and the interlayer insulating film 3 are formed in the same chamber, and the second etch stop film 4 and the wiring insulating film 5 are formed in the same chamber. That is, after the first etch stop layer 2 is formed, the interlayer insulating layer 3 is formed in the same chamber without the vacuum state, and after the second etch stop layer 4 is formed, the wiring insulation layer 3 is formed in the same chamber without the vacuum state. It is preferable to form 5). This is accomplished by precisely controlling PECVD equipment parameters such as the mixing ratio of the deposition gas, plasma excitation power, substrate temperature, chamber pressure, etc. forming the first etch stop film 2 and the second etch stop film 4. In order to have a specific Si-N and Si-O content.

The first etch stop layer 2 and the second etch stop layer 4 thus formed may be subjected to over-etching due to a difference in etching rates between the interlayer insulating layer 3 and the wiring insulating layer 5 in a subsequent etching process. It is possible to prevent pattern defects and damage to the lower thin film which are likely to occur.

In addition, by adjusting the volume% of the amorphous silicon or polysilicon, the stress of the thin film may be improved and the adhesion to the upper and lower layers may be improved.

Next, as shown in FIG. 2, after forming the contact hole pattern 6 for forming the contact hole on the wiring insulating layer 5, the contact hole pattern 6 is exposed by dry etching using plasma as a mask. The wiring insulating film 5 is etched and removed, and the second etch stop film 4 again exposed is etched and removed, and the exposed interlayer insulating film 3 is etched and removed, thereby contacting the interlayer insulating film 3 with the contact hole 7. To form.

3, after the contact hole pattern 6 is removed, a trench pattern 8 for forming a trench in which metal wiring is formed is formed on the wiring insulating film 5. The trench insulating film 5 is removed by etching the wiring insulating film 5 exposed by the dry etching using the plasma as a mask to form a trench in which the metal wiring is formed in the wiring insulating film 5. In this case, the second etch stop layer 4 serves to prevent the etching of the upper surface portion of the interlayer insulating layer 3 from being etched exactly on the upper surface of the interlayer insulating layer 3. As such, by depositing the second etch stop layer 4 on the interlayer insulating layer 3, the phenomenon of additional etching from the surface of the interlayer insulating layer 3 when the wiring insulating layer 5 is etched can be prevented.

Next, as shown in FIG. 4, after the surface of the second etch stop film 4 is exposed and the etching of the wiring insulating film 5 is completed, the trench pattern 8 on the wiring insulating film 5 is removed. The first etch stop film 2 and the second etch stop film 4 exposed in the contact hole 8 of the interlayer insulating film 3 and the lower portion of the trench insulating film 5 are simultaneously etched and removed. At this time, since the first etch stop film 2 and the second etch stop film 4 are insulating films, in order to conduct current from the metal wiring to the conductive layer of the lower thin film 1, and to obtain a desired dielectric capacitance. It is desirable to remove.

Then, as shown in FIG. 5, a barrier is formed on the entire upper surface of the lower thin film of the semiconductor substrate 1 to prevent a reaction between the metal thin film and the conductive layer of the lower thin film of the semiconductor substrate 1 before the deposition of the metal thin film. A metal film 9 is deposited. At this time, the barrier metal film 9 is formed by depositing TaN to a thickness of several hundred microwatts. In addition, an EPD (electroplating process deposition) metal thin film having excellent throughput and filling capability must be filled in the contact hole 7 of the interlayer insulating film 3 and the trench of the wiring insulating film 5. At this time, in order to grow the EPD metal thin film, the ionized metal ions must be moved to the surface of the thin film, and electrons are smoothly supplied to the metal to reduce the metal to the metal to smoothly grow on the thin film surface. However, since the barrier metal film 9 has a high resistivity, the metal seed (CVD) is deposited on the barrier metal film 9 by CVD to smoothly supply electrons to the surface of the thin film in the deposition process of the EPD metal thin film. seed film 10 is deposited to a thickness of several hundred microseconds.

Next, as shown in FIG. 6, the metal thin film 11 is filled in the trenches of the contact hole 7 and the wiring insulating film 5 of the interlayer insulating film 3 using the EPD process. Then, the metal thin film 11, the metal seed film 10, and the barrier metal film 9 on the wiring insulating film 5 are polished and removed by a chemical mechanical polishing (CMP) process to complete the metal wiring of the semiconductor element. . It is preferable that such metal wiring is copper wiring.

Meanwhile, even in the single damascene process in which only the first etch stop layer is formed, the first etch stop layer may be formed to easily control the density and composition ratio, and to control the etch rate with the insulating layer on the upper or lower portion. The electrical characteristics of the device can be improved.

Although the preferred embodiments of the present invention have been described in detail above, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention.

In the method of forming a metal interconnection of a semiconductor device according to the present invention, it is easy to control the density and composition ratio of the etch stop layer by forming an etch stop layer using a PE-CVD device in a dual damascene process, and the etching rate with the insulating film on the top or the bottom ( There is an advantage that you can adjust the etch rate.

In addition, it is possible to prevent a short circuit phenomenon with the lower metal wiring due to overetching, and the stress of the thin film can be reduced by adjusting the composition ratio or process parameter of the etch stop layer.

Therefore, bubbles can be prevented from occurring during the subsequent metal wiring process, and the dielectric constant (ε) of the entire insulating film can be lowered compared to the conventionally used SiN or SiON, thereby reducing the electrical characteristics of the device. Has the advantage of improving

Claims (12)

Stacking a first etch stop film, an interlayer insulating film, a second etch stop film, and a wiring insulating film on a semiconductor substrate having a predetermined substructure; Forming a contact hole pattern on the wiring insulating layer; Etching the exposed wiring insulating layer, the second etch stop layer, and the interlayer insulating layer by using the contact hole pattern as a mask to form contact holes; Removing the contact hole pattern and forming a trench pattern on the wiring insulating layer; Etching the exposed wiring insulating layer using the trench pattern as a mask to form a trench; After removing the trench pattern, removing the exposed second etch stop layer and the first etch stop layer Including, And the first etch stop layer and the second etch stop layer are oxynitride layers containing 5 to 30% of silicon. In claim 1, And the silicon is either silicon or polysilicon. In claim 1, And forming the first etch stop layer and the interlayer insulating layer in the same chamber, and the second etch stop layer and the wiring insulating layer in the same chamber. In claim 3, Forming an interlayer insulating film without forming a vacuum after forming the first etch stop layer, and forming a wiring insulating layer without forming a vacuum after forming the second etch stop layer. In claim 1, And the first etch stop film and the second etch stop film are contained oxynitride films of Si-N of 30% or more and 70% or less. In claim 1, And forming the first etch stop layer and the second etch stop layer by a PECVD method using a high frequency power source of 13.56 MHz or 100 Hz to 1 MHz. In claim 6, The PECVD method is a method for forming a metal wiring of a semiconductor device to apply a substrate bias with a plasma generation power of 0 to 2 KW. In claim 7, The PECVD method is a metal wire forming method of a semiconductor device that proceeds under a pressure of 0.5 to 20 torr. In claim 6, The PECVD method is a metal wiring method for forming a semiconductor device using a substrate a mixture of N ₂ O, from 0 to N ₂ of 50000 sccm of SiH _4, from 0 to 5000 sccm of 0 to 500 sccm. In claim 9, The PECVD method is a method of forming a metal wiring of a semiconductor device using a mixed gas for deposition diluted by adding an inert gas. In claim 10, And the inert gas is any one of He, Ne, and Ar. In claim 1, Depositing a barrier metal film on the inner wall of the contact hole and the trench and the lower structure, and depositing a metal seed film on the barrier metal film; Depositing a metal thin film in the contact hole and the trench; And removing the metal thin film, the metal seed film and the barrier metal film on the wiring insulating film by a chemical metallic polishing process.

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